CN102376633A - 一种半导体结构及其制造方法 - Google Patents
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Abstract
本发明公开了一种半导体结构及其制造方法,所述结构包括:半导体衬底,所述半导体衬底上包括器件结构;形成于所述器件结构上的层间介质层,所述层间介质层中有沟槽,所述沟槽包括一体成型的通孔槽和导电连线槽,所述导电连线槽位于通孔槽之上;填充于所述沟槽的导电层,所述导电层与所述器件结构电连接;其中,所述导电层中包括导电材料和被所述导电材料包围的纳米管/线层。所述结构的导电层具有好的导热性、导电性及高抗电迁移率,能够有效阻挡金属离子向外扩散。
Description
技术领域
本发明通常涉及一种半导体结构及其制造方法,具体来说,涉及一种具有更好性能的互连结构(Interconnect)的半导体结构及其制造方法。
背景技术
随着半导体技术的飞速发展,具有更高性能和更强功能的集成电路要求更大的元件密度,CMOS(互补型金属氧化物半导体)器件和金属连线等部件的尺寸需要进一步缩小,这使得器件的速度越来越快,由于金属连线的尺寸变小同时也导致了金属连线的电阻越来越大,因此出现了金属连线的信号传输速率跟不上器件的速度的问题。
在跨入纳米时代以后,随着器件尺寸的进一步缩小,局部互连结构,包括一体成型的通孔和金属走线,被具有更小电阻率和更高抗电迁移率的金属铜或其他材料取而代之。然而这些金属材料中的金属离子很容易扩散到半导体结构中,导致器件结构的短路或其他性能不良的问题。
因此,有必要提出一种新型的半导体结构及其制造方法,以解决上述互连结构中存在的问题。
发明内容
本发明提供了一种半导体结构的制造方法,所述方法包括:提供半导体衬底,所述半导体衬底上包括器件结构;在所述器件结构上形成层间介质层,以及图形化所述层间介质层以形成沟槽,所述沟槽包括一体成型的通孔槽和导电连线槽,所述导电连线槽位于通孔槽之上;在所述沟槽内形成填满所述沟槽的导电层,所述导电层与所述器件结构电连接;其中,所述导电层中包括导电材料和被所述导电材料包围的纳米管/线层。
本发明还提供了根据上述方法形成的半导体结构,所述结构包括:半导体衬底,所述半导体衬底上包括器件结构;形成于所述器件结构上的层间介质层,所述层间介质层中有沟槽,所述沟槽包括一体成型的通孔槽和导电连线槽,所述导电连线槽位于通孔槽之上;填充于所述沟槽中的导电层,所述导电层与所述器件结构电连接;其中,所述导电层中包括导电材料和被所述导电材料包围的纳米管/线层。
本发明实施例所述的半导体结构制造方法形成的金属连线和通孔一体成型的互连结构,由包括导电材料和导电材料包围的纳米管/线层形成,由于纳米管/线具有独特的物理结构和物理化学性质,使导电层具有好的导热性、导电性及高抗电迁移率,进而提高导电层的信号传输速率,使其信号传输速率与不断提高的器件速度相匹配。此外由于碳纳米管/线为单层碳原子或金属原子形成的结构,有利于阻挡导电材料中的金属或其他离子向半导体结构中的其他位置扩散,能够得到优质的互连接触,减少半导体结构中的短路现象。
附图说明
图1示出了根据本发明的实施例的半导体结构的制造方法流程图;
图2-14示出了根据本发明的实施例的半导体结构的各个制造阶段对应的截面示意图;
图15示出了本发明实施例中竖直方向的纳米管/线的示意图;
图16示出了本发明实施例中水平方向的纳米管/线的示意图;
图17示出了本发明实施例中纳米管/线网的示意图。
具体实施方式
本发明通常涉及制造半导体结构的方法。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。此外,本发明提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外,以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。
参考图1,图1示出了根据本发明的实施例的半导体结构的制造方法的流程图。在步骤S01,参考图2,提供半导体衬底200,所述半导体衬底200上包括器件结构300,参考图3。衬底200包括位于晶体结构中的硅衬底(例如晶片),还可以包括其他基本半导体或化合物半导体,例如Ge、SiGe、GaAs、InP、Si:C或金刚石等。根据现有技术公知的设计要求(例如p型衬底或者n型衬底),衬底200可以包括各种掺杂配置。此外,可选地,衬底200可以包括外延层,可以被应力改变以增强性能,以及可以包括绝缘体上硅(SOI)结构。
所述器件结构可以包括晶体管、二极管或其他半导体组件、以及其他电学器件或互连结构等。参考图2,图2示出了本发明的器件结构的一个实施例半导体器件300。所述半导体器件300的形成方法可以包括,首先在半导体衬底200上依次形成栅介质层202以及栅电极204。而后,进行倾角离子注入,在半导体衬底200内形成源/漏延伸区208,或者可以进一步形成晕环(Halo)注入区。而后,环绕所述栅介质层202和栅电极204的外侧壁形成侧墙206,并以栅电极204和侧墙206为掩膜,进行离子注入,在栅电极204两侧的半导体衬底内形成源/漏区210,并退火以激活注入的离子,从而在栅电极204两侧的半导体衬底内形成源/漏区210。而后,覆盖所述器件形成层间介质层212,以及在位于源/漏区210的层间介质层212内形成接触214,上述半导体衬底上的半导体器件300的结构和形成方法仅是示例,还可以是其他的器件结构,还可以包括其他的半导体部件以及其他介质层、其他的互连结构等,此处仅为示例,对本发明并不做任何限定。
在步骤S02,在所述器件结构300上形成层间介质层310,以及图形化所述层间介质层310以形成沟槽320,所述沟槽320包括一体成型的通孔槽320-1和导电连线槽320-2,参考图2。可以通过大马士革工艺(Damascene),图形化所述层间介质层310,在其内形成包括通孔槽320-1和导电连线槽320-2的沟槽320,可以先形成通孔槽320-1而后形成导电连线槽320-2,也可以先形成导电连线槽320-2,而后形成通孔槽320-1。
从图2中也可以看出,通孔槽与器件结构之间相通,从而在填充了导电材料之后,能够与器件结构之间实现电连接。
可选地,在形成沟槽320后,可以在其侧壁上形成绝缘层(图中未示出),所述绝缘层包括氮化物、氧化物或其他合适的材料,以防止之后形成的导电层中的金属离子扩散至半导体结构中。
优选地,在形成沟槽320或绝缘层后,可以在所述沟槽320的底部和侧壁形成阻挡层330,参考图2。可以通过传统的沉积工艺,例如PVD的方法,在所述沟槽320内壁沉积阻挡层330,阻挡层由包括TaN、TiN、Ta、Ti、TiSiN、TaSiN、TiW、WN或Ru中的任一种或多种的组合形成。所述阻挡层起到防止之后形成的导电层中的金属离子扩散至半导体结构中的作用。
在步骤S03,在所述沟槽320内形成填满所述沟槽320的导电层,其中所述导电层包括导电材料340和被导电材料340包围的纳米管/线层350。
具体来说,首先,可以通过例如CVD的方法,在所述阻挡层330上沉积导电材料,可以是金属材料,例如铜种子层340,金属材料还可以包括铝、钨或其他合适的材料,而后在铜种子层340上形成碳纳米管/线层350,以所述沟槽320底部平面的方向为水平方向的参考方向,在一个实施例中,碳纳米管/线层350可以是水平方向的纳米管/线,参考图3,在另外的实施例中,还可以是竖直方向的纳米管/线,参考图7,在又一个实施例中,还可以是纳米管/线网,参考图11,其中纳米线可以是金属纳米线,例如Au、Ta、Cu等,其中纳米管可以为碳纳米管或其他导体纳米管,例如金属纳米管。图15、16、17分别示出了本发明实施例中竖直方向的纳米管/线、水平方向的纳米管/线以及纳米管/线网的示意图。纳米管/线也可以与所述半导体衬底成任意倾斜角度。
形成导电材料的方法可以是PVD、CVD、ALD、PLD、MOCVD、PEALD、溅射、分子束淀积(MBE)等。形成所述碳纳米管/线可以通过例如用化学气相沉积方法、电弧放电方法或激光烧灼法或其他合适的方法来形成,所述金属纳米管/线可以通过例如硬/软模板法、光/电化学还原法、种子生长合成法或其他合适的方法来形成。具体的碳纳米管/线的形成方法可以参考现有技术,这里不再赘述。
而后,接着在纳米管线网上形成金属材料340,例如金属铜、铝、钨,在一个实施例中,例如电镀的方法,使铜填充部分沟槽,参考图4、图8和图12。
而后,再在金属材料上形成另一碳纳米管/线层350,同上一碳纳米管/线层一样,碳纳米管/线层350可以是竖直方向的纳米管/线、水平方向的纳米管/线及纳米管/线网,并在其上填充金属材料340,例如铜,可以根据需要反复形成碳纳米管/线层及填充金属材料340,直至金属材料340填满所述沟槽320,参考图5、图9和图13,上述图示仅为示例,对每一次形成的碳纳米管/线都可以是竖直方向的纳米管/线、水平方向的纳米管/线及纳米管/线网。
而后,对金属材料进行平坦化,例如CMP的方法,使导电层与所述层间介质层大致相平,参考图6、图10和图14。从附图中可以看出,沟槽的底部较窄,内部的金属材料做为通孔中的金属塞;沟槽的上部较宽,内部的金属材料作为金属连线使用,从而实现与其他半导体结构的互连。
而后可以根据需要进行后续的工艺步骤,例如在其上形成另一互连结构,以及另一层间介质层或其他部件。
本发明的实施例半导体结构的制造方法,除了用于制造第一金属层,同样也可以用于制造后道工艺中其他层的金属层。以上实施例并不用于限定本发明。
根据上述方法,本发明还提供了通过上述方法形成的半导体结构,参考图6、图10和图14,所述结构包括:半导体衬底200,所述衬底上包括以及其上的器件结构300;形成于所述器件结构300上的层间介质层310,所述层间介质层中有沟槽320,所述沟槽320包括一体成型的通孔槽320-1和导电连线槽320-2,所述导电连线槽320-2位于通孔槽320-1之上;填充于所述沟槽320的导电层,所述导电层与所述器件结构电连接;其中,所述导电层中包括导电材料340和被所述导电材料340包围的纳米管/线层350。其中所述纳米管/线层350至少为一层,所述导电材料340至少为两层,所述纳米管/线层以以下任一种或多种的组合的形式排列在所述导电层中:与所述半导体衬底平行,与所述半导体衬底垂直,与所述半导体衬底成倾斜角度,或者形成纳米管/线网结构,所述纳米管/线层包括碳纳米管线、金属纳米管/线,或其组合。其中形成所述导电层的材料可以为金属,例如可以包括:铜、铝、钨。所述纳米管/线层350包括碳纳米管/线、金属纳米管/线,或其组合。优选地,所述结构还包括形成于所述沟槽侧壁及底部与导电层之间的阻挡层。可选地,所述结构还包括形成于所述沟槽侧壁与导电层之间的绝缘层。所述绝缘层和阻挡层起到防止导电层中的金属离子扩散至半导体结构中的作用。
所述器件结构可以包括晶体管、二极管或其他半导体组件、以及其他电学器件或互连结构等。参考图2,图2示出了本发明的器件结构的一个实施例,本发明以半导体器件300为例,该半导体器件300包括:半导体衬底200上的栅介质层202和栅电极204,以及环绕所述栅介质层202和栅电极204形成的侧墙206,以及形成于所述栅电极204两侧的衬底200内的源/漏延伸区208和源/漏区210,可选地,还可以进一步包括晕环(Halo)注入区,以及覆盖源/漏区的层间介质层212,以及位于源/漏区210上、层间介质层212内的接触214。所述半导体器件300的结构仅是示例,还可以是其他的集成电路元件,还可以包括其他的半导体部件以及其他介质层、其他的互连结构等,此处仅为示例,对本发明并不做任何限定。
本发明的实施例的半导体结构,可以用于第一金属层,也可以用于后续的金属层。图2中的实施例并不用于限定本发明。
以上对具有纳米管/线层的一体成型的互连结构的半导体结构及其制造方法进行了详细描述,通过形成由包括金属材料和被金属材料包围的纳米管/线层的导电层,即互连结构,而由于纳米管/线具有独特的电子物理结构和物理化学性质,使导电层具有更好的导热性、导电性及高抗电迁移率,进而提高导电层的信号传输速率,使其信号传输速率与不断提高的器件速度相匹配。此外由于碳纳米管/线为单层C原子或金属原子形成的结构,很有利于阻挡导电材料中的金属或其他离子向半导体结构中的其他位置扩散,能够得到优质的互连接触,避免半导体结构中的器件短路。
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (14)
1.一种半导体结构的制造方法,所述方法包括:
提供半导体衬底,所述衬底上包括器件结构;
在所述器件结构上形成层间介质层,以及图形化所述层间介质层以形成沟槽,所述沟槽包括一体成型的通孔槽和导电连线槽,所述导电连线槽位于通孔槽之上;
在所述沟槽内形成填满所述沟槽的导电层,所述导电层与所述器件结构电连接;
其中,所述导电层中包括导电材料和被所述导电材料包围的纳米管/线层。
2.根据权利要求1所述的方法,其中在所述沟槽内形成填满所述沟槽的导电层的步骤包括:
a、在所述沟槽内形成导电材料,并在其上形成纳米管/线层;
b、在所述纳米管/线层上形成导电材料;
c、重复进行步骤a、b,直至导电材料填满所述沟槽。
3.根据权利要求2所述的方法,其中,步骤a之前,所述方法进一步包括:
在所述沟槽的底部和侧壁形成阻挡层。
4.根据权利要求1所述的方法,其中,在所述沟槽内形成填满所述沟槽的导电层的步骤之前,所述方法进一步包括:
在所述沟槽的侧壁形成绝缘层。
5.根据权利要求1至4中任一项所述的方法,其中所述纳米管/线层包括碳纳米管/线、金属纳米管/线,或其组合。
6.根据权利要求1至4中任一项所述的方法,所述纳米管/线层通过以下任一种或多种的组合的形式排列在所述导电层中:与所述半导体衬底平行,与所述半导体衬底垂直,与所述半导体衬底成倾斜角度,或者形成纳米管/线网结构。
7.根据权利要求1至4中任一项所述的方法,其中所述导电材料包括:铜、铝、钨,或其组合。
8.一种半导体结构,包括:
半导体衬底,所述半导体衬底上包括器件结构;
形成于所述器件结构上的层间介质层,所述层间介质层中有沟槽,所述沟槽包括一体成型的通孔槽和导电连线槽,所述导电连线槽位于通孔槽之上;
填充于所述沟槽中的导电层,所述导电层与所述器件结构电连接;
其中,所述导电层中包括导电材料和被所述导电材料包围的纳米管/线层。
9.根据权利要求8所述的结构,其中所述纳米管/线层至少为一层,所述导电材料至少为两层。
10.根据权利要求8所述的结构,还包括形成于所述沟槽侧壁及底部与导电层之间的阻挡层。
11.根据权利要求8所述的结构,还包括形成于所述沟槽侧壁与导电层之间的绝缘层。
12.根据权利要求8至11中任一项所述的结构,其中所述纳米管/线层通过以下任一种或多种的组合的形式排列在所述导电层中:与所述半导体衬底平行,与所述半导体衬底垂直,与所述半导体衬底成倾斜角度,或者形成纳米管/线网结构。
13.根据权利要求8至11中任一项所述的结构,其中所述导电材料包括:铜、铝、钨,或其组合。
14.根据权利要求8至11中任一项所述的结构,其中所述纳米管/线层包括碳纳米管/线、金属纳米管/线,或其组合。
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