CN102832165B - 经过改进的用于双镶嵌工艺的间隙填充方法 - Google Patents
经过改进的用于双镶嵌工艺的间隙填充方法 Download PDFInfo
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- CN102832165B CN102832165B CN201210003772.1A CN201210003772A CN102832165B CN 102832165 B CN102832165 B CN 102832165B CN 201210003772 A CN201210003772 A CN 201210003772A CN 102832165 B CN102832165 B CN 102832165B
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Abstract
本发明提供了一种制造半导体器件的方法。该方法包括:形成具有多个第一开口的经图案化的介电层;在经图案化的介电层的上方形成导电衬层,该导电衬层部分地填充第一开口;在第一开口外面的部分导电衬层的上方形成沟槽掩模层,从而形成多个第二开口,第二开口的一个子集形成于第一开口的上方;在第一开口中沉积导电材料以形成多个通孔,以及在第二开口中沉积导电材料以形成多个金属线;以及去除沟槽掩模层。本发明提供经过改进的用于双镶嵌工艺的间隙填充方法。
Description
技术领域
本发明涉及半导体领域,具体而言,本发明涉及用于双镶嵌工艺的间隙填充方法。
背景技术
半导体集成电路(IC)产业经历了快速发展。IC材料和设计方面的技术进步产生了IC代,其中每个代都具有比上一个代更小和更复杂的电路。然而,这些进步增加了加工和制造IC的复杂度,因此,为了实现这些进步,需要在IC加工和制造方面的同样发展。在IC发展过程中,功能密度(即每芯片面积上互连器件的数量)大幅增加了而几何尺寸(即,使用制造工艺可以做出的最小组件(或线))降低了。
为形成越来越多的互连部件如通孔和金属线已开发了双镶嵌工艺。双镶嵌工艺涉及形成间隙或者开口。传统双镶嵌工艺采用种子层加镀铜工艺来填充间隙。然而,随着半导体器件尺寸继续缩小,这种方法可能遇到问题。例如,在20纳米(nm)制造工艺中,间隙可能变得太窄,从而可能导致采用常规双镶嵌工艺不能进行合适的填充。间隙的顶部可能被阻塞了,在下面可能形成空隙。结果,降低了半导体器件的性能。
因此,虽然目前的双镶嵌工艺大体上足以实现它们的预期用途,但在各方面仍不是完全令人满意的。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种制造半导体器件的方法,包括:形成具有多个第一开口的经图案化的介电层;在所述经图案化的介电层上方形成导电衬层,所述导电衬层部分地填充所述第一开口;在所述导电衬层位于所述第一开口外的部分上方形成经图案化的沟槽掩模层,从而形成多个第二开口,其中,所述第二开口的至少一个子集设置在所述第一开口的上方;在所述第一开口中沉积导电材料以形成多个通孔,以及在所述第二开口中沉积导电材料以形成多个金属线;以及去除所述沟槽掩模层。
在上述方法中,进一步包括:在去除所述沟槽掩模层之后,去除所述导电衬层的未被所述金属线覆盖的部分;在部分所述经图案化的介电层的上方以及在所述金属线的侧壁上形成介电阻挡层,从而形成多个第三开口;用低k介电材料填充所述第三开口;以及对所述低k材料实施化学机械抛光工艺。
在上述方法中,其中,形成所述导电衬层包括原子层沉积工艺和化学汽相沉积工艺之一。
在上述方法中,其中,形成所述导电阻挡层包括原子层沉积工艺、化学汽相沉积和物理汽相沉积工艺之一。
在上述方法中,其中,所述沉积包括以以无电电镀工艺、电镀工艺或是物理汽相沉积工艺沉积铜作为所述导电材料。
在上述方法中,进一步包括,在形成所述经图案化的介电层之前:在衬底上方形成互连层,所述互连层包含多个另外的金属线;以及在所述互连层上方形成蚀刻停止层;其中:形成所述经图案化的介电层包括在所述蚀刻停止层上形成所述经图案化的介电层;以及所述经图案化的介电层包含低k介电材料。
在上述方法中,进一步包括:在形成所述导电衬层之前,在所述经图案化的介电层的上方形成导电阻挡层;并且其中,在所述导电阻挡层上形成所述导电衬层。
在上述方法中,进一步包括:在形成所述导电衬层之前,在所述经图案化的介电层的上方形成导电阻挡层,并且其中,在所述导电阻挡层上形成所述导电衬层,其中所述导电衬层包括非铜金属材料,以及所述导电阻挡层包含选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
在上述方法中,进一步包括:在形成所述导电衬层之前,在所述经图案化的介电层的上方形成导电阻挡层,并且其中,在所述导电阻挡层上形成所述导电衬层,其中,所述导电阻挡层和所述导电衬层每一个都薄于约50埃。
根据本发明的另一方面,还提供了一种制造半导体器件的方法,包括:在衬底上方形成互连层,所述互连层包括多个第一金属线组件;在所述互连层上方形成蚀刻停止层;在所述互连层上方形成第一低k介电层,所述第一低k介电层包含多个第一开口;在所述第一低k介电层上方形成导电阻挡层;在所述导电阻挡层上方形成导电衬层,所述导电阻挡层和所述导电衬层部分地填充所述第一开口,其中,形成所述导电衬层采用化学汽相沉积工艺和原子层沉积工艺之一进行实施;在所述导电衬层上方以及所述第一开口上方形成沟槽掩模层,所述沟槽掩模层包含多个第二开口,其中,所述第二开口的至少一个子集与其下面的所述第一开口对准;在所述第一开口中形成多个通孔以及在所述第二开口中形成多个第二金属线组件;之后去除所述沟槽掩模层;之后在去除所述沟槽掩模层的位置形成介电阻挡层,所述介电阻挡层包含多个第三开口;以及用第二低k介电层填充所述第三开口。
在上述方法中,其中,形成所述沟槽掩模层的步骤以使至少一些所述第二开口比在其下面设置的相应第一开口更宽的方式实施。
在上述方法中,其中,形成所述多个通孔和所述多个第二金属线组件的步骤通过以无电电镀工艺、电镀工艺或是物理汽相沉积工艺沉积铜材料实施。
在上述方法中,其中:所述导电衬层包含无铜的金属材料;以及所述导电阻挡层包含选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
在上述方法中,其中,所述导电阻挡层和所述导电衬层每一个都不厚于约50埃。
根据本发明的又一方面,还提供了一种半导体器件,包括:层,包括与多个蚀刻停止部相间错杂的多个导电阻挡部;多个第一介电部,分别被设置在所述蚀刻停止部的上方;多个导电衬部,分别被设置在所述导电阻挡部的上方,其中,部分所述导电衬部被设置在所述第一介电部的侧壁上;多个介电阻挡部,分别被设置在所述第一介电部的上方,其中,所述介电阻挡部包含多个开口;多个第二介电部,分别填充所述开口;多个通孔,分别被设置在所述导电衬部的上方;以及多个金属线组件,其中,所述金属线组件的第一子集的每一个都被设置在相应的所述通孔之一的上方,以及所述金属线组件的第二子集被设置在相应的所述第一介电部之一的上方。
在上述半导体器件中,其中,所述金属线组件与所述第二介电部相间错杂。
在上述半导体器件中,其中:所述导电衬部的每一个都包括无铜的金属材料;以及所述导电阻挡部的每一个都包括选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
在上述半导体器件中,其中,每个导电阻挡部和每个导电衬部都不厚于约50埃。
在上述半导体器件中,进一步包括:衬底;层间介电(ILD)层,被设置在所述衬底的上方;以及互连层,被设置在所述ILD层的上方,所述互连层包含多个另外的金属线组件;其中,包括所述导电阻挡部的所述层被设置在所述互连层的上方。
在上述半导体器件中,进一步包括:衬底;层间介电(ILD)层,被设置在所述衬底的上方;以及互连层,被设置在所述ILD层的上方,所述互连层包含多个另外的金属线组件;其中,包括所述导电阻挡部的所述层被设置在所述互连层的上方,其中,所述互连层进一步包括:多个另外的导电阻挡部,被设置在所述ILD层的上方;多个另外的导电衬部,分别被设置在所述导电阻挡部的上方;多个另外的介电阻挡部,被设置在所述ILD层的上方,所述另外的介电阻挡部包含多个另外的开口;以及多个第三介电部,分别填充所述另外的开口;其中:所述另外的金属线组件分别被设置在所述另外的导电衬部的上方;以及所述另外的金属线部件与所述第三介电部相间错杂。
在上述半导体器件中,进一步包括:衬底;层间介电(ILD)层,被设置在所述衬底的上方;以及互连层,被设置在所述ILD层的上方,所述互连层包含多个另外的金属线组件;其中,包括所述导电阻挡部的所述层被设置在所述互连层的上方,其中:所述第一介电部、第二介电部、和第三介电部全都包含低k介电材料;以及所述介电阻挡部全都包含是化合物的材料,所述化合物由多个选自由硅、氧、碳、氮、和硼组成的的组的元素构成。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的各方面。应该强调的是,根据工业中的标准实践,各种部件没有按比例进行绘制。实际上,为了清楚讨论起见,各种部件的尺寸可以被任意增大或缩小。
图1是示出了根据本发明的各个方面制造半导体器件以减小临界尺寸(critical dimension)的方法的流程图。
图2至图10是根据图1的方法的各个制造阶段的半导体器件的示意性横截面侧视图。
具体实施方式
应当了解为了实施各个实施例的不同部件,以下公开内容提供了许多不同的实施例或实例。在下面描述组件和布置的特定实例以简化本发明。当然这些仅仅是实例并不打算用于限定。例如,在下面的描述中第一部件在第二部件上或者上方的形成可以包括其中第一和第二部件以直接接触形成的实施例,并且也可以包括其中可以在第一和第二部件之间形成额外的部件,使得第一和第二部件不直接接触的实施例。此外,本发明可在各个实例中重复参考数字和/或字母。这种重复是为了简明和清楚,而且其本身不指定各个实施例和/或所讨论的结构之间的关系。
图1中示出了用于改进双镶嵌工艺的间隙填充性能的方法10的流程图。图2至图10是示出了在各个制造阶段期间半导体器件的实施例的横截面视图。半导体器件可以是集成电路(IC)芯片、芯片上系统(SoC)、或其部分,其可以包括各种无源和有源微电子器件如电阻器、电容器、电感器、二极管、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结晶体管(BJT)、横向扩散MOS(LDMOS)晶体管、大功率MOS晶体管、或者其它类型的晶体管。应当理解为了更好地理解本发明的发明概念简化了图2至图10。因此,应当注意到:在图1的方法10之前、期间和之后可以提供额外的工艺,以及在本文中对其它一些工艺仅进行简述。
参考图1,方法10开始于框15,在框15中,形成具有多个第一开口的经图案化的介电层。方法10继续到框20,在框20中,在经图案化的介电层上方形成导电衬层。导电衬层部分地填充第一开口。方法10继续到框25,在框25中,在第一开口外面的部分导电衬层的上方形成沟槽掩模层,从而形成多个第二开口,第二开口的一个子集形成于第一开口的上方。方法10继续到框30,在框30中,在第一开口中沉积导电材料以形成多个通孔,以及在第二开口中沉积导电材料以形成多个金属线。方法10继续到框35,在框35中,去除沟槽掩模层。应当理解,在框15至框35之前、期间、和之后可以实施其它工艺以完成半导体器件的制造,但是为了简明起见,在本文中没有示出这些工艺。
图2至图10是在各个制造阶段时的一部分半导体器件50的示意性片段横截面侧视图。参考图2,半导体器件50包括衬底60。衬底60可以是半导体晶圆的一部分。例如,衬底60可以包含硅。衬底60可以可选地由其它一些合适的元素半导体,如金刚石或锗;合适的化合物半导体,如碳化硅、砷化铟、或磷化铟;或者合适的合金半导体,如碳化硅锗、磷化镓砷、或磷化镓铟制成。在一个实施例中,衬底60包括用于各种微电子组件如互补金属氧化物半导体场效应晶体管(CMOSFET)、成像传感器、存储器单元、和/或电容组件的各种掺杂的部件。
在衬底60上形成层间介电(ILD)层70。ILD层70包含介电材料,例如硅酸盐玻璃(USG)或者磷硅酸盐玻璃(PSG)。
在ILD层70上方形成互连层80。互连层80也可以被称为金属层。在实施例中,互连层80是金属-1(M1)层。互连层80包括介电层90。在实施例中,介电层90包含低k材料,例如,由下列元素的一个子集组成的化合物:硅(Si)、氧(O)、碳(C)、和氢(H)。例如,该化合物可以是氧化硅或者碳化硅。在实施例中,介电层90具有小于约1000埃的厚度。
在示出的实施例中,介电层90包括多个部。介电层90的每个部至少部分地被介电阻挡层100围绕或者环绕。在实施例中,介电阻挡层100包括由下列元素的一个子集组成的化合物:Si、O、C、氮(N)、和硼(B)。例如,该化合物可以是氮化硅或碳化硅。在实施例中,介电阻挡层100具有小于约50埃的厚度。介电阻挡层100起减少金属扩散的作用。
互连层80还包括导电阻挡层110。导电阻挡层110包含导电材料。在实施例中,导电材料选自由下列物质组成的组:钽(Ta)、氮化钽(TaNx)、钛(Ti)、氮化钛(TiNx)、氧化锰(MnOx)、及其组合。在实施例中,导电阻挡层110具有小于约50埃的厚度。在示出的实施例中,导电阻挡层110包括多个部。导电阻挡层110的每个部被设置在ILD层70的上方和介电层90的部之间。
互连层80还包括导电衬层120。导电衬层120包含导电材料。在实施例中,导电材料是金属,例如钌(Ru)、钴(Co)、钨(W)、或其组合。在实施例中,导电衬层120具有小于约50埃的厚度。在示出的实施例中,导电衬层120包括多个部。导电衬层120的每个部被设置在导电阻挡层110上和介电层90的部之间。
互连层80还包括导电层130。导电层130包含导电材料。在实施例中,导电材料是Cu。在实施例中,导电层130具有小于约900埃的厚度。在示出的实施例中,导电层130包括多个部。导电层130的每个部被设置在导电衬层120的相应部上以及在介电层90的部之间。导电层130的部充当互连层80中的金属线。
互连层80具有行间距135。在实施例中,行间距小于约64纳米(nm)。
在互连层80上方形成蚀刻停止层140。蚀刻停止层包含介电材料。在实施例中,蚀刻停止层140包含由下列元素的一个子集组成的化合物:Si、O、C、N、和B。例如,该化合物可以是氮化硅、碳化硅、或者氧化硅。选择蚀刻停止层140的材料以使其对介电层90具有足够的蚀刻选择性。换句话说,蚀刻停止层140和介电层90包含不同的材料组分。在实施例中,蚀刻停止层140具有小于约300埃的厚度。
在蚀刻停止层140的上方形成介电层150。在实施例中,介电层150包含低k材料,例如由下列元素的一个子集组成的化合物:Si、O、C和H。例如,该化合物可以是氧化硅或碳化硅。在实施例中,介电层150具有小于约1000埃的厚度。
现在参考图3,对半导体器件50实施图案化工艺200以在介电层150中形成多个开口。图案化工艺200可以包括采用工艺如光刻、浸入式光刻、离子束书写、或者其它合适的工艺形成经图案化的光刻胶层(未示出)。例如,光刻工艺可以包括旋转涂布、软烘焙、暴露、后烘焙、显影、冲洗、干燥、以及其它合适的工艺。图案化工艺还可以包括蚀刻工艺,在蚀刻工艺中,经图案化的光刻胶层可以用作掩模以在介电层140和层150中蚀刻开口。
为了简明起见,在本文中仅示出了开口210至216,但是可以理解形成了许多其它开口。开口210至216每一个都与下面的导电层130的部中的对应部大概对准(垂直)。在实施例中,开口210至216可以比导电层130的部略微更宽。在实施例中,开口210至216的最小宽度是约32nm,或者是行间距135的约1/2。
此时,可以说介电层150构成“仅有通孔的结构(via-only structure)”。换句话说,保留开口210至216用于在随后的工艺中形成通孔,但不用于形成金属线。这与常规双镶嵌工艺是不同的,在常规双镶嵌工艺中形成包含沟槽的结构,该沟槽保留用于形成通孔以及位于通孔上方的金属线。
现在参考图4,实施沉积工艺230以在介电层150上方形成导电阻挡层240,并部分地填充开口210至216。导电阻挡层240还形成于开口210至216中的介电层150的侧壁上。导电阻挡层240位于这些侧壁上的部分是薄的,因此为了简明起见在本文中不具体示出。在实施例中,沉积工艺230包括化学汽相沉积(CVD)工艺。在另一实施例中,沉积工艺230包括原子层沉积(ALD)工艺。导电阻挡层240包含导电材料。在实施例中,导电材料选自由下列物质组成的组:钽(Ta)、氮化钽(TaNx)、钛(Ti)、氮化钛(TiNx)、氧化锰(MnOx)、及其组合。在实施例中,导电阻挡层240具有小于约50埃的厚度。
现在参考图5,实施沉积工艺250以在导电阻挡层240上方形成导电衬层260,并部分填充开口210至216。在实施例中,沉积工艺250包括CVD工艺。在另一实施例中,沉积250包括ALD工艺。导电衬层260包含导电材料。在实施例中,导电材料是金属,该金属可以是非铜材料。在实施例中,导电衬层260具有小于约50埃的厚度。与用于电镀工艺的传统种子层相比,导电衬层260具有更低的导电性。由于更低的导电性,其可以用于无电电镀工艺,将在下面对无电电镀工艺进行更详细的讨论。
现在参考图6,对半导体器件50实施图案化工艺280,以形成沟槽掩模层290。在一个实施例中,沟槽掩模层290包含光刻胶材料,采用与上面参考图3所讨论的相类似的光刻工艺对其进行图案化。在另一个实施例中,沟槽掩模层290包含介电材料,例如氧化硅,可以通过经图案化的光刻胶层对其进行图案化。沟槽掩模层290的形成实际上建立了多个额外的开口210A至216A。开口210A至216A的子集分别被设置在开口210至216的上方(并与开口210至216对准)。可选地,开口210A至216A的子集可以被视为开口210至216的延伸。开口210A至216A也可以被称为沟槽。在示出的实施例中,开口210A、212A、和216A比开口211A、213A至215A更宽。保留开口210A至216A用于在随后的工艺中形成金属线组件,而保留开口210至216用于在随后的工艺中形成通孔。
现在参考图7,对半导体器件50实施双镶嵌沉积工艺300。双镶嵌沉积工艺300沉积导电材料。在一个实施例中,导电材料是Cu。在一个实施例中,双镶嵌工艺300包括无电电镀工艺(ELD)工艺。在另一实施例中,双镶嵌沉积工艺300可以包括电镀工艺(ECP)。在另一实施例中,双镶嵌沉积工艺300可以包括物理汽相沉积工艺(PVD)。随后在双镶嵌沉积工艺300之后实施化学机械抛光(CMP)工艺。作为双镶嵌工艺和后续的CMP工艺的结果,在开口210至216中形成多个通孔310至316,以及在开口210A至216A中形成多个金属线320至326。在导电衬层260上形成通孔310至316。在通孔310至316上形成金属线320至326。在实施例中,在其上形成的通孔314和金属线324可以被视为单个通孔。对于通孔315和金属线325同样也可以这么说。以相间错杂或者交错的方式设置金属线320至326和沟槽掩模层290。
以双镶嵌工艺形成通孔的传统方法涉及采用物理汽相沉积(PVD)工艺来形成种子层。采用PVD工艺形成的这种种子层可能具有较差的一致性,意为其在一些部分中可能较薄,同时其它部分可能基本上较厚。如果种子层在侧壁部分太薄了(例如小于约50埃),则其不足以实施接种(seeding)功能。另一方面,如果在侧壁部分形成足够厚(例如大于约50埃)的种子层,则其可能具有同样太厚的顶角落,引起阻塞沟槽开口210至216(图5)的突出端(overhangs)。突出端可能阻止后续的通孔沉积,并可能导致形成空隙。
相比之下,本文所公开的导电衬层260容许使用化学沉积工艺形成通孔310至316。这也可以被称为直接镀工艺。不像形成通孔的常规工艺,对于这种工艺不需要种子层。也可以对本文用于形成导电衬层260的ALD或者CVD工艺进行调谐以具有良好的均匀性控制。因此,可以形成薄的(小于50埃)且对于底部和侧壁部分是共形的导电衬层260。这减少了突出端的可能性和存在,容许开口在后续双镶嵌沉积工艺300中更容易被通孔310至316填充。此外,因为沟槽掩模层290在形成导电衬层260之后形成,所以在沟槽掩模层290的侧壁上不形成导电衬层260的部分。这也容许沟槽开口比常规方法更宽,在常规方法中在限定通孔上方的金属线的形状的介电层的侧壁上形成种子层。出于上面所讨论的这些原因,通过本发明的方法改进了沟槽填充性能。
现在参考图8,去除沟槽掩模层290。之后,以使部分介电层150被暴露出来的方式去除未被金属线320至326覆盖的导电阻挡层240和导电衬层260的部分。
现在参考图9,在介电层150的暴露部分的上方以及在金属线320至326的顶部和侧壁上形成介电阻挡层350。介电阻挡层350包含是化合物的材料,该化合物由选自由Si、O、C、N、和B组成的组的多个元素组成。使介电阻挡层350成形以形成多个开口370至377。可以说在去除沟槽掩模层290(图7)的位置形成介电阻挡层350(和开口370至377)。
现在参考图10,在介电阻挡层350上方形成介电层380,其填充开口370至377。在实施例中,介电层380包含低k材料。然后在介电层380上实施CMP工艺,直到介电层380的上表面基本上与金属线320至326共平面。介电层380包含至少部分地被介电阻挡层350围绕或者环绕的多个部。介电阻挡层350起到减少相邻的金属结构如金属线320至326之间的金属扩散的作用。在采用常规双镶嵌工艺形成的金属层中可能没有这种介电阻挡层350。在该制造方面,以与介电层380的部相间错杂或者交错的方式设置金属线320至326,介电层380的部填充介电阻挡层350的开口370至377。
上面所讨论的工艺实际上建立了互连层400,互连层400包括金属线320至326和介电层380的部。互连层400被认为是位于互连层80的上方。因此,在互连层80是金属-1层的实施例中,互连层400是金属-2(M2)层。通孔310至316将上面的互连层400中的金属线320至326和下面的互连层80中的金属线130电连接在一起。在示出的实施例中,通孔310至316可以被认为是设置在通孔-1层内。
尽管没有详细讨论互连层80的制造工艺,但应当理解可以以相似的方式实施用于形成互连层400的工艺来同样形成互连层80。例如,根据一个实施例,在ILD层70上形成导电阻挡层110。在导电阻挡层110上形成导电衬层120。在导电衬层120上形成沟槽掩模层(与沟槽掩模层290相似)。然后图案化该沟槽掩模层以形成多个开口或者沟槽。形成金属线130,以沉积工艺接着以后续CMP工艺填充这些开口。然后去除沟槽掩模层,并实施一个或者多个蚀刻工艺来去除未被金属线130保护的导电衬层120和导电阻挡层110的部分。之后,形成介电阻挡层100。然后形成被介电阻挡层100围绕的介电层90。也应当理解可以应用用于形成互连层80和互连层400(以及它们之间的通孔层)的方法在互连层400的上方形成额外的互连层和通孔层,例如金属-3层或金属-4层。
本文所公开的实施例提供了优于常规双镶嵌方法的优势。然而,应当理解不同的实施例可能提供其它优势,并且没有特定优势是所有实施例所必需的。一个优势是:如上面所讨论的,本文所公开的实施例容许通过形成“仅有通孔”结构的方式形成较宽的沟槽,以及通过利用CVD或者ALD形成相对共形的导电衬层。不再需要厚的铜种子层。鉴于此,可以基本上减缓沟槽突出端问题,并改进间隙(沟槽)填充性能。另一个优势是本文所讨论的工艺与现有的半导体制造流程兼容。因此,本发明实施例的实施成本并不高。
本发明的一个较广泛的形式涉及制造半导体的方法,该方法包括:形成具有多个第一开口的经图案化的介电层;在经图案化的介电层的上方形成导电衬层,该导电衬层部分地填充第一开口;在第一开口外面的部分导电衬层的上方形成经图案化的沟槽掩模层,从而形成多个第二开口,其中,第二开口的至少一个子集被设置在第一开口的上方;在第一开口中沉积导电材料以形成多个通孔,以及在第二开口中沉积导电材料以形成多个金属线;以及去除沟槽掩模层。
在实施例中,该方法包括:在去除沟槽掩模层之后,去除导电衬层的未被金属线覆盖的部分;在部分经图案化的介电层的上方以及在金属线的侧壁上形成介电阻挡层,从而形成多个第三开口;用低k介电材料填充第三开口;以及对低k材料实施化学机械抛光工艺。
在实施例中,形成导电衬层包括原子层沉积工艺和化学汽相沉积工艺之一。
在实施例中,沉积包括以无电电镀工艺、电镀工艺或是物理汽相沉积工艺沉积铜作为导电材料。
在实施例中,该方法进一步包括:在形成经图案化的介电层之前:在衬底上方形成互连层,该互连层包含多个另外的金属线;以及在互连层上方形成蚀刻停止层;其中:形成经图案化的介电层包括在蚀刻停止层上形成经图案化的介电层;以及经图案化的介电层包含低k介电材料。
在实施例中,该方法包括:在形成导电衬层之前,在经图案化的介电层的上方形成导电阻挡层;并且其中,在导电阻挡层上形成导电衬层。
在实施例中,导电衬层包含非铜金属材料;以及导电阻挡层包含选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
在实施例中,导电阻挡层和导电衬层每一个都薄于约50埃。
本发明的另一个较广泛的形式涉及制造半导体器件的方法,该方法包括:在衬底上方形成互连层,该互连层包括多个第一金属线组件;在互连层上方形成蚀刻停止层;在互连层上方形成第一低k介电层,该第一低k介电层包含多个第一开口;在第一低k介电层上方形成导电阻挡层;在导电阻挡层上方形成导电衬层,该导电阻挡层和该导电衬层部分地填充第一开口,其中形成导电衬层采用化学汽相沉积工艺和原子层沉积工艺之一进行实施;在导电衬层上方以及在第一开口上方形成沟槽掩模层,该沟槽掩模层包含多个第二开口,其中第二开口的至少一个子集与其下面的第一开口对准;在第一开口中形成多个通孔以及在第二开口中形成多个第二金属线组件;之后去除沟槽掩模层;之后在去除沟槽掩模层的位置形成介电阻挡层,该介电阻挡层包含多个第三开口;以及用第二低k介电层填充第三开口。
在实施例中,形成沟槽掩模层以使至少一些第二开口比在其下面设置的相应第一开口宽的方式实施。
在实施例中,形成多个通孔和多个第二金属线组件通过以化学镀工艺沉积铜材料实施。
在实施例中,导电衬层包含无铜的金属材料;以及导电阻挡层包含选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
在实施例中,导电阻挡层和导电衬层每一个都不厚于约50埃。
本发明的又一个较广泛的形式涉及一种半导体器件。该半导体器件包括:层,包括与多个蚀刻停止部相互交叉的多个导电阻挡部;多个第一介电部,分别被设置在蚀刻停止部的上方;多个导电衬部,分别被设置在导电阻挡部的上方,其中部分导电衬部被设置在第一介电部的侧壁上;多个介电阻挡部,分别被设置在所述第一介电部的上方,其中介电阻挡部包含多个开口;多个第二介电部,分别填充开口;多个通孔,分别被设置在导电衬部的上方;以及多个金属线组件,其中,金属线组件的第一子集每一个都被设置在相应的通孔之一的上方,以及金属线组件的第二子集被设置在相应的第一介电部之一的上方。
在实施例中,金属线组件与第二介电部相间错杂。
在实施例中,导电衬部每一个都包含无铜的金属材料;以及导电阻挡部每一个都包含选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
在实施例中,每个导电阻挡部和每个导电衬部都不厚于约50埃。
在实施例中,权利要求所述的半导体器件进一步包括:衬底;在衬底上方设置的层间介电(ILD)层;以及在ILD层上方设置的互连层,该互连层包含多个另外的金属线组件;其中包含导电阻挡部的层被设置在互连层的上方。
在实施例中,互连层进一步包括:多个另外的导电阻挡部,被设置在ILD层的上方;多个另外的导电衬部,分别被设置在导电阻挡部的上方;多个另外的介电阻挡部,被设置在ILD层的上方,所述另外的介电阻挡部包含多个另外的开口;以及多个第三介电部,分别填充另外的开口;其中:另外的金属线组件分别被设置在另外的导电衬部的上方;以及另外的金属线组件与第三介电部相间错杂。
在实施例中,第一、第二、和第三介电部全都包含低k介电材料;以及介电阻挡部全都包含是化合物的材料,该化合物由多个选自由硅、氧、碳、氮、和硼的元素组成。
上面论述了若干实施例的部件,使得本领域技术人员可以更好地理解随后的具体说明。本领域技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其它工艺和结构,用于达到与本文所介绍实施例相同的目的和/或实现相同的优势。本领域技术人员也应该意识到,这种等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行各种变化、替换以及改变。
Claims (20)
1.一种制造半导体器件的方法,包括:
形成具有多个第一开口的经图案化的介电层,其中,所述经图案化的介电层包括多个横向分离段所组成的所述第一开口;
在所述经图案化的介电层上方形成导电衬层,所述导电衬层部分地填充所述第一开口;
在所述导电衬层位于所述第一开口外的部分上方形成经图案化的沟槽掩模层,从而形成多个第二开口,其中,所述第二开口的至少一个子集设置在所述第一开口的上方并与所述第一开口对准,其中,所述多个第二开口被设置在所述经图案化的沟槽掩膜层的横向分离段;
在所述第一开口中沉积导电材料以形成多个通孔,以及在所述第二开口中沉积导电材料以形成多个金属线;以及
去除所述沟槽掩模层。
2.根据权利要求1所述的方法,进一步包括:
在去除所述沟槽掩模层之后,去除所述导电衬层的未被所述金属线覆盖的部分;
在部分所述经图案化的介电层的上方以及在所述金属线的侧壁上形成介电阻挡层,从而形成多个第三开口;
用低k介电材料填充所述第三开口;以及
对所述低k材料实施化学机械抛光工艺。
3.根据权利要求1所述的方法,其中,形成所述导电衬层包括原子层沉积工艺和化学汽相沉积工艺之一。
4.根据权利要求1所述的方法,其中,所述沉积包括以化学沉积工艺或者电镀工艺沉积铜作为所述导电材料。
5.根据权利要求1所述的方法,进一步包括,在形成所述经图案化的介电层之前:
在衬底上方形成互连层,所述互连层包含多个另外的金属线;以及
在所述互连层上方形成蚀刻停止层;
其中:
形成所述经图案化的介电层包括在所述蚀刻停止层上形成所述经图案化的介电层;以及
所述经图案化的介电层包含低k介电材料。
6.根据权利要求1所述的方法,进一步包括:在形成所述导电衬层之前,在所述经图案化的介电层的上方形成导电阻挡层;
并且其中,在所述导电阻挡层上形成所述导电衬层。
7.根据权利要求6所述的方法,其中:
所述导电衬层包括非铜金属材料;以及
所述导电阻挡层包含选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
8.根据权利要求6所述的方法,其中,所述导电阻挡层和所述导电衬层每一个都薄于50埃。
9.一种制造半导体器件的方法,包括:
在衬底上方形成互连层,所述互连层包括多个第一金属线元件;
在所述互连层上方形成蚀刻停止层;
在所述互连层上方形成第一低k介电层,所述第一低k介电层包含多个第一开口,其中,将所述第一低k介电层分割成横向的多段从而组成所述多个第一开口;
在所述第一低k介电层上方形成导电阻挡层;
在所述导电阻挡层上方形成导电衬层,所述导电阻挡层和所述导电衬层部分地填充所述第一开口,其中,形成所述导电衬层采用化学汽相沉积工艺和原子层沉积工艺之一进行实施;
在所述导电衬层上方以及所述第一开口上方形成沟槽掩模层,所述沟槽掩模层包含多个第二开口,其中,所述第二开口的至少一个子集与其下面的所述第一开口对准,其中,所述第二开口的多个第二子集与多个所述第一低k介电层的分段对齐;
在所述第一开口中形成多个通孔以及在所述第二开口中形成多个第二金属线元件;
之后去除所述沟槽掩模层;
之后在去除所述沟槽掩模层的位置形成介电阻挡层,所述介电阻挡层包含多个第三开口;以及
用第二低k介电层填充所述第三开口。
10.根据权利要求9所述的方法,其中,形成所述沟槽掩模层的步骤以使至少一些所述第二开口比在其下面设置的相应第一开口更宽的方式实施。
11.根据权利要求9所述的方法,其中,形成所述多个通孔和所述多个第二金属线元件的步骤通过以化学镀工艺沉积铜材料实施。
12.根据权利要求9所述的方法,其中:
所述导电衬层包含无铜的金属材料;以及
所述导电阻挡层包含选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
13.根据权利要求9所述的方法,其中,所述导电阻挡层和所述导电衬层每一个都不厚于50埃。
14.一种半导体器件,包括:
层,包括与多个蚀刻停止部以横向分离段的形式相间错杂的多个导电阻挡部;
多个第一介电部,分别被设置在所述蚀刻停止部的上方;
多个导电衬部,分别被设置在所述导电阻挡部的上方,其中,部分所述导电衬部被设置在所述第一介电部的侧壁上;
多个介电阻挡部,分别被设置在所述第一介电部的上方,其中,所述介电阻挡部包含多个开口;
多个第二介电部,分别填充所述开口;
多个通孔,分别被设置在所述导电衬部的上方;以及
多个金属线元件,其中,所述金属线元件的第一子集的每一个都被设置在相应的所述通孔之一的上方,以及所述金属线元件的第二子集被设置在相应的所述第一介电部之一的上方;其中,所述多个金属线元件的至少一个与所述多个通孔对准。
15.根据权利要求14所述的半导体器件,其中,所述金属线元件与所述第二介电部相间错杂。
16.根据权利要求14所述的半导体器件,其中:
所述导电衬部的每一个都包括无铜的金属材料;以及
所述导电阻挡部的每一个都包括选自由钽、氮化钽、钛、氮化钛、和氧化锰组成的组的材料。
17.根据权利要求14所述的半导体器件,其中,每个导电阻挡部和每个导电衬部都不厚于50埃。
18.根据权利要求14所述的半导体器件,进一步包括:
衬底;
层间介电层,被设置在所述衬底的上方;以及
互连层,被设置在所述层间介电层的上方,所述互连层包含多个另外的金属线元件;
其中,包括所述导电阻挡部的所述层被设置在所述互连层的上方。
19.根据权利要求18所述的半导体器件,其中,所述互连层进一步包括:
多个另外的导电阻挡部,被设置在所述层间介电层的上方;
多个另外的导电衬部,分别被设置在所述导电阻挡部的上方;
多个另外的介电阻挡部,被设置在所述层间介电层的上方,所述另外的介电阻挡部包含多个另外的开口;以及
多个第三介电部,分别填充所述另外的开口;
其中:
所述另外的金属线元件分别被设置在所述另外的导电衬部的上方;以及
所述另外的金属线部件与所述第三介电部相间错杂。
20.根据权利要求18所述的半导体器件,其中:
所述第一介电部、第二介电部、和第三介电部全都包含低k介电材料;以及
所述介电阻挡部全都包含是化合物的材料,所述化合物由多个选自由硅、氧、碳、氮、和硼组成的的组的元素构成。
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US20150235963A1 (en) | 2015-08-20 |
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US20170084485A1 (en) | 2017-03-23 |
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