TWI509735B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI509735B
TWI509735B TW100139542A TW100139542A TWI509735B TW I509735 B TWI509735 B TW I509735B TW 100139542 A TW100139542 A TW 100139542A TW 100139542 A TW100139542 A TW 100139542A TW I509735 B TWI509735 B TW I509735B
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layer
openings
dielectric
conductive
forming
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TW201301436A (zh
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Chun Chieh Lin
Hung Wen Su
Minghsing Tsai
Syun Ming Jang
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Taiwan Semiconductor Mfg Co Ltd
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Description

半導體裝置及其製造方法
本發明係關於半導體製作，且特別是關於一種半導體裝置及其製造方法。
半導體積體電路工業已經歷了快速成長。積體電路材料及設計之技術演進已造就了數個世代之積體電路，且每一世代較前一世代具有更小與更為複雜的電路。然而，此些演進增加了積體電路之處理與製作的複雜度，且為了實現此些演進，需要針對積體電路的處理與製作進行發展。於積體電路評估之項目中，當幾何尺寸(geometry size，即使用製造程序所能創造出之最小元件或線路)逐漸縮小時，其功能密度(functional density，即每一晶片區之內連元件的數量)已逐漸增加。
目前已發展出了雙鑲嵌程序(dual damascene process)以形成大量的內連元件，例如介層物(vias)與金屬導線(metal lines)。雙鑲嵌製程牽涉了凹口或開口的形成。傳統雙鑲嵌程序係使用一晶種層加上一銅電鍍程序以填滿凹口。然而，隨著半導體元件尺寸持續微縮，上述方法可能遭遇問題。舉例來說，於20奈米製程中，上述凹口通常為窄的，因此可能無法藉由傳統雙鑲嵌程序將之填滿。可能於凹口的頂部產生阻擋情形，因而可能產生了位於下方的孔洞(voids)。如此，便劣化了半導體裝置之表現。
因此，雖然現今雙鑲嵌程序可大體地滿足相關目標，但其並非可完全滿足每一方面的目標。
依據一實施例，本發明提供了一種半導體裝置之製造方法，包括：形成一圖案化介電層，該圖案化介電層具有複數個第一開口；形成一導電襯層於該圖案化介電層之上，該導電襯層部分填入於該些第一開口之內；形成一圖案化溝槽罩幕層於該些第一開口以外之部分該導電襯層之上，進而形成複數個第二開口，其中至少該些第二開口之一係設置於該些第一開口之上；沈積一導電材料於該些第一開口之內以形成複數個介層物，及於該些第二開口之內以及形成複數個金屬導線；以及移除該溝槽罩幕層。
依據另一實施例，本發明提供了一種半導體裝置之製造方法，包括：形成一內連層於一基板之上，該內連層包括複數個第一金屬導線元件；形成一蝕刻停止層於該內連層之上；形成一第一低介電常數介電層於該內連層之上，該第一低介電常數介電層包括複數個第一開口；形成一導電阻障層於該第一低介電常數介電層之上；形成一導電襯層於該導電阻障層之上，該導電阻障層與該導電襯層部分填入於該些第一開口之內，其中形成該導電襯層係由下述方法之一所完成：一化學氣相沈積程序以及一原子層沈積程序；形成一溝槽罩幕層於該導電襯層之上以及該些第一開口之上，該溝槽罩幕層包括了複數個第二開口，其中至少該些第二開口之一係對準於其下方之該些第一開口；形成複數個介層物於該些第一開口之內以及形成複數個第二金屬導線元件於該些第二開口之內；接著移除該溝槽罩幕層；接著形成一介電阻障層，以取代經移除之該溝槽罩幕層，該介電阻障層包括複數個第三開口；以及於該些第三開口內填入一第二低介電常數介電層。
依據又一實施例，本發明提供了一種半導體裝置之製造方法，包括：一膜層，包括交錯設置之複數個導電阻障部以及複數個蝕刻停止部；複數個第一介電部，分別設置於該些蝕刻停止部之上；複數個導電襯層部，分別設置於該些導電阻障部之上，其中部分之該些導電襯層部係設置於該些第一介電部的側壁之上；複數個介電阻障部，分別位於該些第一介電部之上，其中該介電阻障部包括複數個開口；複數個第二介電部，分別填入該些開口；複數個介層物，分別設置於該些導電襯層部之上；以及複數個金屬導線元件，其中該些金屬導線元件之一第一子部分別設置於該些介層物之一之上，而該些金屬導線元件之一第二子部分別設置於該些第一介電部之一之上。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
可以理解的是，於下文中提供了用於施行本發明之不同特徵之多個不同實施例，或範例。基於簡化本發明之目的，以下描述了構件與設置情形之特定範例。然而，此些構件與設置情形僅作為範例之用而非用於限制本發明。舉例來說，於描述中關於於一第二元件之上或上之第一元件的形成可包括了第一元件與第二元件係為直接接觸之實施情形，且亦包括了於第一元件與第二元件之間包括了額外元件之實施情形，因而使得第一元件與第二元件之間並未直接接觸。此外，本發明於不同實施例中可能重複使用標號及/或文字。如此之重複情形係基於簡化與清楚之目的，而非用於限定不同實施例及/或討論形態內的相對關係。
第1圖為一流程圖，繪示了可改善雙鑲嵌製程之溝填表現(gap filling performance)之一方法10。第2-10圖為一系列剖面圖，繪示了一實施例之一半導體裝置於不同製造階段中的情形。此半導體裝置可為一積體電路晶片(IC chip)、一晶片系統(system on chip，SOC)或為其一部，其可包括之如電阻、電容、電感、二極體、金氧半導體場效電晶體(MOSFET)、互補型金氧半導體(CMOS)電晶體、雙極性接面電晶體(BJT)、橫向擴散型電晶體(LDMOS)、高功率金氧半導體(high power MOS)電晶體或其他類型電晶體之多種被動或主動微電子元件。可以理解的是，基於較佳地瞭解本發明之發明概念，第2-10圖係經過簡化。因此，可以理解的是於第1圖所示方法10之前、之中或之後可施行額外之製程，且於此處僅簡單描述了部份之其他製程。
請參照第1圖，方法10起使於步驟15，於步驟15中形成具有複數個第一開口之一圖案化介電層。方法10接著進行步驟20，於圖案化介電層之上形成一導電襯層。導電襯層部份填入於此些第一開口之內。方法10接著進行步驟25，於第一開口以外之導電襯層之數個部份之上形成一溝槽罩幕層，進而形成了數個第二開口，此些第二開口之一係形成於此些第一開口之上。方法10接著進行步驟30，沈積一導電材料於此些第一開口內以形成數個介層物(vias)及於此些第二開口內以形成數個金屬導線(metal lines)。方法10繼續步驟35，以移除溝槽罩幕層。可以理解的是，可於步驟15-35之前、之中或之後實施額外製程，以完成半導體裝置的製作，然而基於簡化之目的並未在此繪示此些製程。
第2-10圖為一半導體裝置50之一部於製作中之不同階段的片段剖面示意圖。請參照第2圖，半導體裝置50包括一基板60。基板60可為半導體晶圓之一部。舉例來說，基板60可包括矽。基板60亦可包括如鑽石或鍺之其他適當之元素態半導體；如碳化矽、砷化銦、磷化銦之適當之化合物半導體；或如矽鍺碳(silicon germanium carbide)、鎵砷磷(gallium arsenic phosphide)或鎵銦磷(gallium indium phosphide)之一適當合金半導體。於一實施例中，基板60包括了用於如互補型金氧半導體場效電晶體(CMOSFET)、影像感測器、記憶胞及/或電容元件等不同微電子元件之不同摻雜情形。
於基板60之上形成有一層間介電層(ILD)70。層間介電層70包括了如未摻雜矽玻璃(USG)或磷矽玻璃(PSG)之一介電材料。
於層間介電層70之上形成有一內連層(interconnect layer)80。內連層80亦可稱為一金屬層。於一實施例中，內連層80為第一金屬(metal-1，M1)層。內連層80包括了一介電層90。於一實施例中，介電層90包括了低介電常數介電材料，例如由下述元素所形成之一化合物：矽、氧、碳及氫。舉例來說，上述化合物可為氧化矽或碳化矽。於一實施例中，介電層90具有少於約1000埃之厚度。
於圖示之實施例中，介電層90包括了數個部分。介電層90之每一部分係至少為一介電阻障層100所部份地環繞或纏繞。於一實施例中，介電阻障層100包括了由下述元素所組成之一化合物：矽、氧、碳、氮與硼。舉例來說，上述化合物可為氮化矽或碳化矽。於一實施例中，介電阻障層100具有少於約50埃之厚度。介電阻障層100係作為降低金屬擴散之用。
內連層80亦包括了一導電阻障層110。導電阻障層110包括了導電材料。於一實施例中，導電材料係擇自由鉭、氮化鉭(TaNx)、鈦、氮化鈦(TiNx)、氧化錳及其組合所組成族群之一材料。於一實施例中，導電阻障層110具有少於約50埃之厚度。於圖示實施例中，導電阻障層110包括了複數個部分。導電阻障層110之每一部分係設置於層間介電層70之上且位於介電層90之數個部分之間。
內連層80亦包括了一導電襯層120。導電襯層120包括了導電材料。於一實施例中，導電材料為一金屬，例如為釕(Ru)、鈷(Co)、鎢(W)或其組合。於一實施例中，導電襯層120具有少於約50埃之厚度。於圖示實施例中，導電襯層120包括了數個部分。導電襯層120之每一部分係設置於導電阻障層110之上且位於該介電層90之數個部分之間。
內連層80亦包括一導電層130。導電層130包括一導電材料。於一實施中，導電材料為銅。於一實施例中，導電材料130具有少於900埃之厚度。於圖示之實施例中，導電層130包括數個部分。導電層130之每一部分係設置於導電襯層120之對應部分之上，並位於介電層90之數個部分之間。導電層130之數個部分係做為內連層80內之金屬導線之用。
內連層80具有一線間距(line pitch)135。於一實施例中，上述線間距135少於約60奈米。
於內連層80之上形成有一蝕刻停止層140。蝕刻停止層包括一介電材料。於一實施例中，蝕刻停止層140包括由下述元素所組成之一化合物：矽、氧、碳、氮與硼。舉例來說，上述化合物可為氮化矽、碳化矽或氧化矽。蝕刻停止層140係經過選擇，以使得其與介電層90之間具有足夠之蝕刻選擇率。換句話說，蝕刻停止層140與介電層90包括了不同之材料組成。於一實施例中，蝕刻停止層140具有少於約300埃之厚度。
於蝕刻停止層140之上形成有一介電層150。於一實施例中，介電層150包括一低介電常數介電材料，例如由下述元素所組成之一化合物：矽、氧、碳與氫。舉例來說，上述化合物可為氧化矽或碳化矽。於一實施例中，介電層150具有少於約1000埃之一厚度。
請參照第3圖，於半導體裝置50之上施行一圖案化程序200，以於介電層150之內形成數個開口。圖案化程序200可包括採用如微影、浸潤式微影、離子束直寫或其他適當程序之一程序以形成一圖案化阻劑層(未顯示)。舉例來說，上述微影程序可包括旋轉塗佈、軟烤、曝光、硬烤、顯影、清洗、乾燥及其他適當程序。上述圖案化程序亦可包括一蝕刻程序，此蝕刻程序採用了圖案化之阻劑層做為罩幕而於介電層140與150之內蝕刻形成了數個開口。
基於簡化之目的，在此僅繪示了開口210、212、214、215與216，雖然可以理解的是亦可形成許多之其他開口。開口210、212、214、215與216分別大體(垂直地)對準於其下方導電層130內之數個部分之一。於一實施例中，開口210、212、214、215與216可略寬於導電層130之部分。於一實施例中，開口210、212、214、215與216的最小寬度約為32奈米，或為線間距135的二分之一。
在此，可將介電層150視為僅包括介層物之結構。換句話說，開口210、212、214、215與216可於後續程序中用於形成介層物之用，但非用於形成金屬導線之用。如此之結構不同於習知雙鑲嵌製程，於習知雙鑲嵌製程中係形成用於形成介層物及位於介層物上之金屬導線之數個連續溝槽。
請參照第4圖，施行一沈積程序230以於介電層150之上形成一導電阻障層240並部份地將填入開口210、212、214、215與216之內。導電阻障層240亦形成於位於開口210、212、214、215與216內之介電層150的側壁之上。位於此些側壁之上的導電阻障層240部分為薄的，故基於簡化之目的而並未在此特別地將之繪示出。於一實施例中，沈積程序230包括一化學氣相沈積程序。於另一實施例中，沈積程序230包括了原子層沈積程序。導電阻障層240包括了導電材料。於一實施例中，導電材料係擇自由鉭、氮化鉭(TaNx)、鈦、氮化鈦(TiNx)、氧化錳及其組合所組成族群之一材料。於一實施例中，導電阻障層240具有少於約50埃之厚度。
請參照第5圖，施行一沈積程序250以形成導電襯層260於導電阻障層240之上並部份填入於開口210、212、214、215與216內。於一實施例中，沈積程序250包括了一化學氣相沈積程序。於另一實施例中，沈積程序250包括一原子層沈積程序。導電襯層260包括一導電材料。於一實施例中，導電材料為一金屬，其可為一非銅金屬。於一實施例中，導電襯層260具有少於50埃之厚度。相較於用於電鍍程序之習知晶種層，導電襯層260具有較低之導電率。基於上述之較低導電率，故其可使用一無電電鍍程序，上述無電電鍍程序將於下文中進一步討論。
請參照第6圖，於半導體裝置50之上施行一圖案化程序280以形成一溝槽罩幕層290。於一實施例中，溝槽罩幕層290包括了阻劑材料，而此阻劑材料係採用相似於如第3圖所討論之一微影程序而經過圖案化。於另一實施例中，溝槽罩幕層290包括了如氧化矽之一介電材料，其可藉由一圖案化阻劑層而圖案化。溝槽罩幕層290的形成實際上形成了額外之數個開口210A、211A、212A、213A、214A、215A與216A。開口210A、211A、212A、213A、214A、215A與216A之一係分別設置開口210、212、214、215與216之一之上並與之對準。或者開口210A、211A、212A、213A、214A、215A與216A之一可視為開口210、212、214、215與216的延伸。開口210A、211A、212A、213A、214A、215A與216A可稱之為溝槽。於圖示之實施例中，開口210A、212A與216A係寬於開口211A、213-215A。對於後續程序中形成之金屬導線元件而言，開口210A、211A、212A、213A、214A、215A與216A為反相的，而對於後續程序中形成介層物而言，開口210、212、214、215與216為反相的。
請參照第7圖，於半導體裝置50之上施行雙鑲嵌沈積程序300。此雙鑲嵌沈積程序300沈積了一導電材料。於一實施例中，上述導電材料為銅。於一實施例中，雙鑲嵌沈積程序300包括了一無電沈積程序。於另一實施例中，雙鑲嵌沈積程序300包括了一電鍍程序。於雙鑲嵌沈積程序300之後，施行一化學機械研磨程序。於雙鑲嵌沈積程序與後續之化學機械研磨程序之後，便於開口210、212、214、215與216內形成數個介層物310、312、314、315與316，以及於開口210A、211A、212A、213A、214A、215A與216A內形成數個金屬導線320、321、322、323、324、325與326。介層物310、312、314、315與316係形成於導電襯層260之上。金屬導線320、321、322、323、324、325與326係形成於介層物310、312、314、315與316之上，於一實施例中，介層物314及形成於其上之金屬導線324可視為單一介層物。相同情形已見於介層物315與其上之金屬導線325。金屬導線320、321、322、323、324、325與326以及溝槽罩幕層290係按照叉合(interdigitated)或插入(interleaving)之方式而設置。
於雙鑲嵌程序內之形成介層物之習知方法包括了使用一物理氣相沈積以形成一晶種層。由物理氣相沈積所形成之上述晶種層可能具有不良之順應性(conformity)，意味著其某些部份較薄而其他部份可能大體較厚。當晶種層於其側壁部份過薄時(如少於約50埃時)，其便可能無法適當地顯現出其晶種之功能。另一方面，當於側壁處之晶種層過厚時(例如大於約50埃時)，其頂角處之厚度可能太厚，進而造成了突出(overhang)問題，此突出問題會阻擋了溝槽開口210、212、214、215與216(請參照第5圖)。此突出情形亦會阻礙後續之介層物沈積並導致孔洞(voids)的產生。
相較之下，於本處揭示之導電襯層260可採用無電沈積程序以形成介層物310、312、314、315與316。其亦稱為直接鍍程序(direct plating process)。不同於習知形成介層物之方法，於本程序中不需要晶種層。在此形成導電襯層260之所使用的原子層沈積或化學氣相沈積可經過調整而具有良好的均勻度控制。因此，可於底部與側壁部之上形成順應且薄(少於50埃)之導電襯層260。如此降低了前述情形的出現及其可能性，進而允許了此些開口可為於後續雙鑲嵌沈積程序300中之介層物310、312、314、315與316所填入。此外，由於溝槽罩幕層290係於導電襯層260形成後形成，導電襯層260並沒有形成於溝槽罩幕層290之側壁上。如此可使得溝槽開口較習知方法為寬中，於習知方法中晶種層係形成於位於介層物上用於定義金屬導線形狀之介電層的側壁之上。基於上述討論理由，藉由本發明之方法可改善溝槽填入表現。
請參照第8圖，移除溝槽罩幕層290。接著，移除未為金屬導線320、321、322、323、324、325與326所覆蓋之導電阻障層240與導電襯層260之部份，並露出了介電層150之數個部份。
請參照第9圖，於露出的介電層150之數個部份以及金屬導線320、321、322、323、324、325與326之頂部與側壁之上形成一介電阻障層350。介電阻障層350包括一材料，其為擇自由下述元素：矽、氧、碳、氮與硼所組成族群之化合物。介電阻障層350於成型後而形成數個開口370、371、372、373、374、375、376與377。可以理解的是，介電阻障層350(及開口370-377)於形成後取代了經移除之溝槽罩幕層290(見於第7圖)。
請參照第10圖，於介電阻障層350上形成一介電層380並填入於開口370、371、372、373、374、375、376與377之內。於一實施例中，介電層380包括了低介電常數介電材料。接著於介電層380之上施行一化學機械研磨直至介電層380的表面大體與金屬導線320、321、322、323、324、325與326共平面。介電層380包括了至少為介電阻障層350所部份環繞或纏繞之數個部分。介電阻障層350係用於降低來自如金屬導線320、321、322、323、324、325與326之鄰近金屬結構之金屬擴散。此介電阻障層350於藉由習知雙鑲嵌製程所形成之金屬膜層中為非必要的。於此製造觀點中，金屬導線320、321、322、323、324、325與326以及填入於介電阻障層350內之開口370、371、372、373、374、375、376與377之介電層380的數個片段係依照叉合或插入方式而沈積形成。
前述之程序可製造出包括了金屬導線320、321、322、323、324、325與326以及介電層380之數個部分之一內連層(interconnect layer)400。上述內連層400可視為位於內連層80之上。如此，於一實施例中，當內連層80為第一金屬層(Metal-1)時，內連層400為一第二金屬層(Metal-2)。介層物310-316電性耦接了於內連層400內之金屬導線320、321、322、323、324、325與326及位於下方內連層80內之金屬導線130。於圖示之實施例中，介層物310、312、314、315與316可視為設置於第一介層物層(Via-1)之中。
雖然在此並未詳細討論內連層80之製程，可以理解的是用於形成內連層400之程序亦可用於形成內連層80。舉例來說，於一實施例中，導電阻障層110係形成於層間介電層70之上。導電襯層120係形成於導電阻障層110之上。溝槽罩幕層(相似於溝槽罩幕層290)係形成於導電襯層120之上。接著圖案化溝槽罩幕層以形成數個開口或溝槽。於一沈積程序中形成金屬導線130並使之填入於此些開口內，並接著施行一化學機械研磨程序。接著移除溝槽罩幕層，且可施行一或多個蝕刻程序以移除未為金屬導線所保護的導電襯層120與導電阻障層110之數個部分。接著，形成介電阻障層100。接著形成介電層90以環繞介電阻障層100。可以理解的是，亦可施行形成內連層80與內連層400之方法，以形成如為第三金屬層(metal-3)與第四金屬層(metal-4)之額外內連層與介層物層於內連層400之上。
上述之實施例提供了較習知雙鑲嵌程序為佳之優點。然而，可以理解的是於不同實施例中具有其他之優點，且所有實施例並不需具有特定優點。在此實施例之優點之一為藉由前述之”僅介層物”結構的形成可形成較寬之溝槽，並可利用了化學氣相沈積或原子層沈積以形成相對順應之導電襯層。因此便不需要較厚之晶種層。如此，大體便解決了溝槽突出(trench overhang)問題，並改善了溝槽填入表現。前述製程之另一優點為其相容於當今之半導體製造流程。如此，本發明實施例的實施並不會太昂貴。
本發明之一較廣實施形態提供了一種半導體裝置之製造方法，上述方法包括：形成一圖案化介電層，該圖案化介電層具有複數個第一開口；形成一導電襯層於該圖案化介電層之上，該導電襯層部分填入於該些第一開口之內；形成一圖案化溝槽罩幕層於該些第一開口以外之部分該導電襯層之上，進而形成複數個第二開口，其中至少該些第二開口之一係設置於該些第一開口之上；沈積一導電材料於該些第一開口之內以形成複數個介層物，及於該些第二開口之內以及形成複數個金屬導線；以及移除該溝槽罩幕層。
於一實施例中，上述方法更包括：於移除該溝槽罩幕層之後，移除未為該些金屬導線覆蓋之部分之該導電襯層；形成一介電層於部分之該圖案化介電層之上及於該些金屬導線之側壁之上，進而形成複數個第三開口；於該些第三開口內填入一低介電常數介電材料；以及對該低介電常數介電材料施行一化學機械研磨程序。
於一實施例中，該導電襯層係由下述方法之一所形成：一原子層沈積程序以及一化學氣相沈積程序。
於一實施例中，沈積該導電材料包括於一無電沈積程序或一電鍍程序中沈積銅以作為該導電材料。
於一實施例中，於形成該圖案化介電層之前，上述方法更包括：形成一內連層於一基板之上，該內連層包括複數個金屬導線；以及形成一蝕刻停止層於該內連層之上；其中形成該圖案化介電層包括：形成該圖案化介電層於該蝕刻停止層之上；以及該圖案化介電層包括一低介電常數介電材料。
於一實施例中，上述方法更包括：形成一導電阻障層於該圖案化介電層之上；以及其中該導電襯層係形成於該導電阻障層之上。
於一實施例中，該導電襯層包括一非銅之金屬材料；以及該導電阻障層包括擇自由鉭、氮化鉭、鈦、氮化鈦及氧化錳所組成族群之一材料。
於一實施例中，該導電阻障層與該導電襯層皆薄於約50埃。
本發明之另一較廣實施形態提供了一種半導體裝置之製造方法，上述方法包括：形成一內連層於一基板之上，該內連層包括複數個第一金屬導線元件；形成一蝕刻停止層於該內連層之上；形成一第一低介電常數介電層於該內連層之上，該第一低介電常數介電層包括複數個第一開口；形成一導電阻障層於該第一低介電常數介電層之上；形成一導電襯層於該導電阻障層之上，該導電阻障層與該導電襯層部分填入於該些第一開口之內，其中形成該導電襯層係由下述方法之一所完成：一化學氣相沈積程序以及一原子層沈積程序；形成一溝槽罩幕層於該導電襯層之上以及該些第一開口之上，該溝槽罩幕層包括了複數個第二開口，其中至少該些第二開口之一係對準於其下方之該些第一開口；形成複數個介層物於該些第一開口之內以及形成複數個第二金屬導線元件於該些第二開口之內；接著移除該溝槽罩幕層；接著形成一介電阻障層，以取代經移除之該溝槽罩幕層，該介電阻障層包括複數個第三開口；以及於該些第三開口內填入一第二低介電常數介電層。
於一實施例中，形成該溝槽罩幕層的施行使得至少部分之該第二開口係寬於設置於其下方之各第一開口。
於一實施例中，形成該些介層物以及該些第二金屬導線元件係藉由於一無電電鍍程序中沈積一鋼材料所完成。
於一實施例中，該導電襯層包括不含銅之一金屬材料；以及該導電阻障層包括擇自由鉭、氮化鉭、鈦、氮化鈦及氧化錳所組成族群之一材料。
於一實施例中，該導電阻障層與該導電襯層皆薄於約50埃。
本發明之又一較廣實施形態提供了一種半導體裝置。上述半導體裝置包括：一膜層，包括交錯設置之複數個導電阻障部以及複數個蝕刻停止部；複數個第一介電部，分別設置於該些蝕刻停止部之上；複數個導電襯層部，分別設置於該些導電阻障部之上，其中部分之該些導電襯層部係設置於該些第一介電部的側壁之上；複數個介電阻障部，分別位於該些第一介電部之上，其中該介電阻障部包括複數個開口；複數個第二介電部，分別填入該些開口；複數個介層物，分別設置於該些導電襯層部之上；以及複數個金屬導線元件，其中該些金屬導線元件之一第一子部分別設置於該些介層物之一之上，而該些金屬導線元件之一第二子部分別設置於該些第一介電部之一之上。
於一實施例中，該些金屬導線元件與該些第二介電部係叉合地設置。
於一實施例中，該導電襯層部包括一非銅之金屬材料；以及該導電阻障部包括擇自由鉭、氮化鉭、鈦、氮化鈦及氧化錳所組成族群之一材料。
於一實施例中，每一導電阻障部與每一導電襯層部皆不厚於50埃。
於一實施例中，上述半導體裝置更包括：一基板；一層間介電層，設置於該基板之上；以及一內連層，設置該層間介電層之上，該內連層包括複數個其他之金屬導線元件；其中包括該些導電阻障部之該膜層係設置於該內連層之上。
於一實施例中，該內連層更包括：複數個其他之導電阻障部，設置於該層間介電層之上；複數個其他之導電襯層部，分別設置於該些導電阻障部之上；複數個其他之介電阻障部，設置於該層間介電層之上，該些其他之介電阻障部包括複數個其他之開口；以及複數個第三介電部，分別填入於該些其他之開口內；其中該些其他之金屬導線元件係分別設置於該些其他導電襯層片段之上；以及該些其他金屬導線元件係與該些第三介電片段交錯地設置。
於一實施例中，該些第一、第二與第三介電部皆包括一低介電常數介電材料；以及該些介電阻障部皆包括為化合物之一材料，該化合物係由擇自由包括矽、氧、碳、氮與硼所組成族群之複數個元素所形成。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．方法
15、20、25、30、35．．．步驟
50．．．半導體裝置
60．．．基板
70．．．層間介電層
80．．．內連層
90．．．內連層
100．．．介電阻障層
110．．．導電阻障層
120．．．導電襯層
130．．．導電層
135．．．線間距
140．．．蝕刻停止層
150．．．介電層
200．．．圖案化程序
210、212、214、215、216．．．開口
210A、211A、212A、213A、214A、215A、216A．．．開口
230．．．沈積程序
240．．．導電阻障層
250．．．沈積程序
260．．．導電襯層
280．．．圖案化程序
290．．．溝槽罩幕層
300．．．雙鑲嵌沈積程序
310、312、314、315、316．．．介層物
320、321、322、323、324、325、326．．．金屬導線
350．．．介電阻障層
370、371、372、373、374、375、376、377．．．
380．．．介電層
400．．．內連層
第1圖為一流程圖，顯示了依據本發明之多個實施例之半導體裝置之製造方法，以降低其特徵尺寸；以及
第2-10圖為一系列示意剖面圖，顯示了如第1圖所示之方法中不同階段內之半導體裝置。
10．．．方法
15、20、25、30、35．．．步驟

Claims (10)

  1. 一種半導體裝置之製造方法，包括：形成一圖案化介電層，該圖案化介電層具有複數個第一開口；形成一導電襯層於該圖案化介電層之上，該導電襯層部分填入於該些第一開口之內；形成一圖案化溝槽罩幕層於該些第一開口以外之部分該導電襯層之上，進而形成複數個第二開口，其中至少該些第二開口之一係設置於該些第一開口之上；沈積一導電材料於該些第一開口之內以形成複數個介層物，及於該些第二開口之內以及形成複數個金屬導線；以及移除該溝槽罩幕層。
  2. 如申請專利範圍第1項所述之半導體裝置之製造方法，更包括：於移除該溝槽罩幕層之後，移除未為該些金屬導線覆蓋之部分之該導電襯層；形成一介電阻障層於部分之該圖案化介電層之上及於該些金屬導線之側壁之上，進而形成複數個第三開口；於該些第三開口內填入一低介電常數介電材料；以及對該低介電常數介電材料施行一化學機械研磨程序。
  3. 如申請專利範圍第1項所述之半導體裝置之製造方法，於形成該圖案化介電層之前，更包括： 形成一內連層於一基板之上，該內連層包括複數個金屬導線；以及形成一蝕刻停止層於該內連層之上；其中形成該圖案化介電層包括：形成該圖案化介電層於該蝕刻停止層之上；以及該圖案化介電層包括一低介電常數介電材料。
  4. 如申請專利範圍第1項所述之半導體裝置之製造方法，於形成該導電襯層之前，更包括：形成一導電阻障層於該圖案化介電層之上；以及其中該導電襯層係形成於該導電阻障層之上。
  5. 一種半導體裝置之製造方法，包括：形成一內連層於一基板之上，該內連層包括複數個第一金屬導線元件；形成一蝕刻停止層於該內連層之上；形成一第一低介電常數介電層於該內連層之上，該第一低介電常數介電層包括複數個第一開口；形成一導電阻障層於該第一低介電常數介電層之上；形成一導電襯層於該導電阻障層之上，該導電阻障層與該導電襯層部分填入於該些第一開口之內，其中形成該導電襯層係由下述方法之一所完成：一化學氣相沈積程序以及一原子層沈積程序；形成一溝槽罩幕層於該導電襯層之上以及該些第一開口之上，該溝槽罩幕層包括了複數個第二開口，其中至少該些第二開口之一係對準於其下方之該些第一開口；形成複數個介層物於該些第一開口之內以及形成複數個第二金屬導線元件於該些第二開口之內；接著移除該溝槽罩幕層；接著形成一介電阻障層，以取代經移除之該溝槽罩幕層，該介電阻障層包括複數個第三開口；以及於該些第三開口內填入一第二低介電常數介電層。
  6. 如申請專利範圍第5項所述之半導體裝置之製造方法，其中形成該溝槽罩幕層的施行使得至少部分之該第二開口係寬於設置於其下方之各第一開口。
  7. 一種半導體裝置，包括：一膜層，包括交錯設置之複數個導電阻障部以及複數個蝕刻停止部；複數個第一介電部，分別設置於該些蝕刻停止部之上；複數個導電襯層部，分別設置於該些導電阻障部之上，其中部分之該些導電襯層部係設置於該些第一介電部的側壁之上；複數個介電阻障部，分別位於該些第一介電部之上，其中該介電阻障部包括複數個開口；複數個第二介電部，分別填入該些開口；複數個介層物，分別設置於該些導電襯層部之上；以及複數個金屬導線元件，其中該些金屬導線元件之一第一子部分別設置於該些介層物之一之上，而該些金屬導線元件之一第二子部分別設置於該些第一介電部之一之上。
  8. 如申請專利範圍第7項所述之半導體裝置，其中：該導電襯層部包括一非銅之金屬材料；以及該導電阻障部包括擇自由鉭、氮化鉭、鈦、氮化鈦及氧化錳所組成族群之一材料。
  9. 如申請專利範圍第7項所述之半導體裝置，其中每一導電阻障部與每一導電襯層部皆薄於50埃。
  10. 如申請專利範圍第7項所述之半導體裝置，更包括：一基板；一層間介電層，設置於該基板之上；以及一內連層，設置該層間介電層之上，該內連層包括複數個其他之金屬導線元件；其中包括該些導電阻障部之該膜層係設置於該內連層之上。
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