CN101803014A - 形成用于改进微电子封装中的第一级互连和环氧树脂底部填料之间的粘结的纳米涂层的方法以及由此形成的结构 - Google Patents

形成用于改进微电子封装中的第一级互连和环氧树脂底部填料之间的粘结的纳米涂层的方法以及由此形成的结构 Download PDF

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CN101803014A
CN101803014A CN200880106316A CN200880106316A CN101803014A CN 101803014 A CN101803014 A CN 101803014A CN 200880106316 A CN200880106316 A CN 200880106316A CN 200880106316 A CN200880106316 A CN 200880106316A CN 101803014 A CN101803014 A CN 101803014A
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interconnection structure
tube core
layer
nano
microelectronics packaging
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CN101803014B (zh
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S·萨内
N·R·拉拉维卡
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Intel Corp
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Abstract

描述了形成微电子器件的方法和相关结构。这些方法可以包括利用功能化纳米粒层涂覆设置在管芯上的互连结构,其中所述功能化纳米粒散布在溶剂中,加热所述功能化纳米粒层以去除所述溶剂的一部分,并且在所述被涂覆的互连结构上施加底部填料。

Description

形成用于改进微电子封装中的第一级互连和环氧树脂底部填料之间的粘结的纳米涂层的方法以及由此形成的结构
背景技术
在用于无铅封装中时,基于环氧树脂的底部填充材料和铜互连之间的不良粘结是应该关注的。在后组装处理期间和/或可靠性测试期间,不良粘结能够导致发生故障。在一些情况下,沿着诸如铜凸块的互连结构的整个表面可能不会发生无铅焊料(例如SnAg或SnAgCu)的毛细管现象(wicking)。这能够导致暴露更大量的互连结构,然后这能够导致与在随后的处理中可能被喷点(dispense)的底部填充材料的不良粘结。
附图说明
尽管以具体指出并明确要求了被示为本发明的内容的权利要求对说明书进行了总结,但是当结合附图阅读本发明的以下说明时,从中能够容易地了解到本发明的优点,附图中:
图1a-1e表示根据本发明的实施例的结构;
图2a-2d表示根据本发明的实施例的结构;
图3a-3b表示根据本发明的实施例的流程图;
图4表示根据本发明的实施例的系统。
具体实施方式
在以下详细的说明中参考附图,参照了附图,附图以说明的方式示出了可以实施本发明的具体实施例。对这些实施例进行了充分详细的说明,以使本领域技术人员能够实施本发明。应该理解的是,本发明的各实施例尽管不同,但并非彼此排斥。例如,于此结合一个实施例描述的特定特征、结构或特性可以在另一实施例中实施而不偏离本发明的精神和范围。此外,应该理解的是,可以修改在每个所公开的实施例中的单个元件的位置或布置而不偏离本发明的精神和范围。因此,以下详细的说明不是限制性的,本发明的范围仅由被恰当理解的所附权利要求以及权利要求有权要求的等价物的全部范围来限定。在附图中,遍及几个视图,类似的参考标记表示相同或相似的功能性。
描述了形成纳米涂覆结构的方法和相关结构。这些方法可以包括利用功能化纳米粒涂覆设置在管芯上的互连结构,其中所述功能化纳米粒散布在溶剂中,加热所述功能化纳米粒的层以去除所述溶剂的一部分,然后在所述被涂覆的互连结构上施加环氧树脂底部填料。本发明的方法可以改善微电子封装中第一级互连和环氧树脂底部调料之间的粘结。
图1a-1e示出了用于改进互连结构和底部填充材料之间的粘结的方法的实施例。图1a示出了纳米粒悬浮液100的一部分。纳米粒悬浮液100可以包括至少一种功能化纳米粒103,所述功能化纳米粒103可以散布在溶剂104中。在一些实施例中,功能化纳米粒103可以包括但是不限于二氧化硅和/或氧化铝纳米粒102,其中所述至少一种纳米粒102的表面化学可以被功能化,并且功能化纳米粒103可以包括官能团106。例如,在一些实施例中,官能团106可以包括如下的官能团:硫醇、硅烷、氨-硅烷盐(ammonium-silane salt)、硅烷偶联剂和/或其他这种与铜和底部填充材料具有良好粘结的聚合物。
在一个实施例中,溶剂104可以包括易于流动的稀释的浓度。在一些实施例中,溶剂104可以包括丙酮、甲苯、水、乙二醇和异丙醇,以及其他这种挥发性、低粘度的溶剂。在一个实施例中,可以在管芯108下面喷点113纳米粒溶液100以涂覆互连结构110(图1b)。在一个实施例中,管芯108可以包括微电子封装115的一部分,其中,可以将焊料凸块112设置在微电子封装115的衬底部分114上。
在一个实施例中,互连结构110可以包括诸如例如SnAg或SnAgCu的无铅焊料互连结构以及铜互连结构中的至少一种。在一个实施例中,在将互连结构110连接到焊料凸块112之后,可以在管芯108周围喷点纳米粒溶液100,例如在芯片连接处理之后但是在底部填充喷点步骤之前。
在一个实施例中,纳米粒溶液100可以涂覆互连结构110、环绕互连结构110的管芯区域111、衬底114的一部分以及可以设置在互连结构110上的焊料凸块112(图1c)。在一个实施例中,纳米粒溶液100可以形成互连结构110上的功能化纳米粒层116。在一个实施例中,层110可以是薄层,并且可以包括大约10纳米到大约500纳米的厚度。
在一个实施例中,基本不利用纳米粒悬浮液100填充设置在管芯108和衬底114之间的管芯间隙区域117。在一个实施例中,可以在芯片连接后执行的喷点处理113可以仅使用在管芯腔的内壁(即,在管芯108、焊球112、互连结构110和衬底114的内壁上)上生成薄层所需的那么多量的功能化纳米粒悬浮液100,所述管芯腔可以存在于管芯108和衬底114之间。
在一个实施例中,根据特定的应用,可以在一个或者多个喷点周期中喷点功能化颗粒层116。例如,相对更大的管芯可以需要多个喷点周期,而相对更小的管芯可以需要更少或单个喷点周期。在互连结构110上形成层116之后,通过加热层116可以蒸发来自功能化纳米粒层116的溶剂104的一部分(图1d)。在一个实施例中,在通过烘培处理去掉溶剂104的一部分之后,例如,功能化纳米粒层116可以粘结和/或润湿互连结构110的表面。
在诸如功能化纳米粒103的纳米涂层中,表面润湿性改变(增加或减小)的依据如下:由于其纳米级的表面特征,纳米涂层提供非常高效的表面面积。这可以使得在其润湿性质中引起步骤改变。如果液体一开始润湿大尺寸(微米级)材料,那么其趋于更润湿纳米级材料。这被称为半毛细(hemi-wicking)。对于非润湿液体这也可能是正确的。也就是说,如果液体一开始不润湿大尺寸的给定材料,那么它对该材料的纳米涂层更具疏水性。为了任何两表面之间的良好粘结,润湿是必不可少的,根据如下公式:G=fn(P,cosθ),其中G是粘结强度,θ是接触角,P是施加的负载。
根据本领域中公知的方法,可以在管芯108和衬底112之间喷点底部填充材料120(图1e)。在一个实施例中,如本领域中所公知的,然后可以固化底部填充材料120。通过调整纳米粒的表面官能团化学性质,可以将功能化纳米粒层116稳定在互连结构110上,并且功能化纳米粒层116能够润湿可以被喷点在管芯108和衬底112之间的底部填充材料120。因此,功能化纳米粒层116在互连结构110上提供非常高效的表面面积涂层,该涂层增强互连结构110和底部填充材料120之间的润湿性。在一个实施例中,喷点在互连结构110、环绕互连结构110的管芯区域111、衬底114的一部分和焊料凸块112上的纳米管和/或纳米线涂层216可以包括纳米涂覆封装互连结构122。
图2a示出了排列碳纳米管阵列200的一部分。碳纳米管阵列200可以包括任何种类的碳纳米管(即,它们可以包括单壁和/或多壁纳米管)。碳纳米管润湿有机液体以及诸如环氧树脂的聚合物树脂是公知的。因此,若纳米管形成诸如排列阵列的开放网络(open network),其中纳米管表面面积适于环氧树脂润湿和浸润,则预期环氧树脂底部填充材料与涂覆有碳纳米管的表面的粘结很好。与此反,诸如碳纳米管纸(巴克纸)的纳米管网络中的一些可以具有随机取向的纳米管的密集网络(dense network),其中可能难以进行环氧树脂浸润,并且能够导致滞留的空隙。
在一个实施例中,排列纳米管阵列200可以单独(离位)生长,然后可以将排列纳米管阵列200放置204到诸如例如铜凸块的互连结构210上,所述互连结构210可以被设置在管芯208上。在一个实施例中,在诸如硅和/或石英衬底的给定衬底上,可以通过化学气相沉积(CVD)离位生长排列碳纳米管阵列200。在一个实施例中,碳纳米管排列阵列200可以生长在镀镍铜岛和/或适当的金属催化剂上,随后通过本领域中公知的方法将其转移到互连结构上。
在另一实施例中,可以直接在互连结构上原位生长纳米管排列阵列200。在一个实施例中,例如使用CVD技术,可以直接在互连结构210表面上原位生长纳米管排列阵列200。镍涂层可以被施加至互连结构210,然后镍涂层可以用作排列碳纳米管200生长的催化剂。碳纳米管排列阵列200能够表现出与互连结构良好的粘结。
或者,能够在较低的温度下通过掠射法生长非常短的金属或陶瓷纳米线202,并且该非常短的金属或陶瓷纳米线202可以用来涂覆互连结构210。经由表面面积的增加,这种线将能够用作粘结提升涂层。在一个实施例中,当互连结构210包括铜时,纳米线202可以直接在互连结构210上生长。在这种情况下,所述线可以增加粘结以及改进互连结构210的电流承载能力。
在一个实施例中,纳米管200可以涂覆互连结构210和管芯208(图2b)。在一个实施例中,纳米管200可以在互连结构210上以及在管芯208的一部分上形成纳米管200构成的层216。在一个实施例中,层216可以是薄层,并且可以包括大约10埃至大约500纳米的厚度。
在一个实施例中,在形成层216之后,通过利用任何适当的方法,例如通过利用芯片连接处理可以将设置在衬底214上的焊料凸块212连接至互连结构210(图2c)。在一个实施例中,通过利用焊料回流,可以将纳米管涂覆互连结构210接合至诸如例如无铅焊料凸块的焊球212,其中层216可以接合至焊料凸块212。在一个实施例中,在芯片连接和/或焊料回流之后可以进行去焊剂处理。
在一个实施例中,其中层216由纳米线202构成,可以通过溶剂喷点方法来施加涂层216。在一些实施例中,在芯片连接之前直接生长在互连上的纳米线能够导致潜在的电迁移和焊接接合处可靠性(例如凸块疲劳、裂缝)问题,因此,纳米线可以在芯片连接之后形成在互连结构210上。总之,碳纳米管生长或转移至互连结构210上可以在芯片连接处理之前执行,并且纳米线或纳米粒生长和转移可以在芯片连接之后执行。
在一个实施例中,设置在管芯208和衬底214之间的管芯间隙区域217基本未填充有纳米管和/或纳米线阵列200、202。在一个实施例中,底部填充材料220可以施加于涂覆有纳米管和/或纳米线层的互连结构(图2d)。设置在互连结构210和管芯208的一部分上的纳米管和/或纳米线涂层216可以用作底部填充材料220的粘结增强剂,在一些实施例中所述底部填充材料220可以包括环氧树脂底部填料。在一个实施例中,设置在互连结构210和管芯208的一部分上的纳米管和/或纳米线涂层216可以包括纳米涂覆封装互连结构222。与这里先前描述的纳米粒涂层相比,碳纳米管具有改进电流承载能力的优点,因为纳米管涂层将不会不利地影响电流承载能力。
图3a描述了根据本发明实施例的流程图。在步骤310,设置在管芯上的互连结构可以涂覆有功能化纳米粒层,其中所述功能化纳米粒散布在溶剂中。在步骤312,可以加热功能化纳米粒层以去除溶剂的一部分,并且在步骤314,可以在被涂覆的互连结构上施加底部填充材料。
图3b描述了本申请另一实施例的流程图。在步骤316,排列纳米管阵列层可以形成在设置在管芯上的互连结构上。在步骤318,焊料凸块可以连接至互连结构,并且在步骤320,底部填充材料可以施加至互连结构。
图4是示出了示例性系统400的示意图,所述系统400能够利用本发明的诸如例如图1e的纳米涂覆封装互连结构122的微电子结构进行操作。应理解的是,本实施例仅是可以使用本发明的纳米涂覆封装互连结构的很多可能系统之一。
在系统400中,纳米涂覆封装互连结构424可以通过I/O总线408通讯上耦合至印刷电路板(PCB)418。纳米涂覆封装互连结构424的通讯耦合可以通过物理方法来建立,例如通过使用用于安装纳米涂覆封装互连结构424至PCB 418(例如通过芯片封装、插件和/或平面栅格阵列插座)的封装和/或插座连接。如本领域中所公知的,纳米涂覆封装互连结构424还可以通过各种无线方法(例如,不利用到PCB的物理连接)通讯耦合到PCB418。
系统400可以包括诸如处理器的计算设备402以及高速缓冲存储器404,计算设备402和高速缓冲存储器404通过处理器总线405彼此通讯上耦合。处理器总线405和I/O总线408可以通过主桥406进行桥接。通讯上耦合至I/O总线408并且还耦合至纳米涂覆封装互连结构424的可以是主存储器412。主存储器412的示例可以包括但是不限于静态随机存取存储器(SRAM)和/或动态随机存取存储器(DRAM),和/或一些其他状态保存介质。系统400还可以包括图形协处理器413,然而将图形协处理器413并入系统400对于系统400的运行并不是必需的。例如,耦合至I/O总线408的还可以是显示设备414、大容量存储设备420以及键盘和点击设备422。
这些元件执行它们在本领域中公知的常规功能。具体而言,大容量存储器420可以用来提供对用于形成根据本发明实施例的纳米涂覆封装互连结构的方法的可执行指令的长期存储,然而,在计算设备402执行期间,主存储器412可以用来短期存储用于形成根据本发明实施例的纳米涂覆封装互连结构的方法的可执行指令。另外,指令可以被存储,否则和与系统通讯上耦合的机器可访问的介质有关,所述介质诸如例如是致密光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)、软盘、载波和/或其他传播信号。在一个实施例中,主存储器412可以为计算设备202(例如可以为处理器)提供用于执行的可执行指令。
本发明的益处包括但不限于:通过在由焊料回流形成互连之后在凸块表面周围施加大表面面积的纳米涂层,改进了铜凸块和底部填料之间的粘结。这些纳米涂层用来改进底部填料到铜互连凸块的润湿性,并且从而改进铜-底部填料的粘结。因此,得到的封装将更鲁棒。在一些实施例中,可以改进微电子封装中的第一级互连和环氧树脂底部填料之间的粘结。
尽管上述说明已经具体说明了可以在本发明的方法中使用的某些步骤和材料,但是本领域技术人员应该理解的是,可以作出许多修改和替换。因此,所有这种修改、变化、替换和添加都应当被看作落入如所附权利要求限定的本发明的精神和范围内。此外,应该理解的是诸如微电子封装的微电子器件的某些方面在本领域中是公知的。因此,应该理解的是在本文中提供的附图仅示出了示例性微电子器件的与实施本发明有关的部分。因此本发明不限于本文所述的结构。

Claims (28)

1.一种方法,包括:
利用功能化纳米粒层和纳米线层中的至少一种涂覆设置在管芯上的互连结构,其中所述功能化纳米粒散布在溶剂中;
加热包括功能化纳米粒层和纳米线层中的至少一种的所述层,以去除所述溶剂的一部分;以及
在所述被涂覆的互连结构上施加底部填料。
2.根据权利要求1所述的方法,还包括,其中在所述互连结构被连接至焊料凸块之后将所述层散布在所述管芯周围。
3.根据权利要求2所述的方法,还包括,其中将所述互连结构设置在所述管芯上,其中所述管芯包括微电子封装的一部分,并且其中将所述焊料凸块设置在所述微电子封装的衬底部分上。
4.根据权利要求1所述的方法,还包括,其中将所述功能化纳米粒散布在低粘度、挥发性溶剂中。
5.根据权利要求4所述的方法,还包括,其中所述溶剂包括丙酮、甲苯、水、乙二醇和异丙醇中的至少一种。
6.根据权利要求1所述的方法,其中涂覆所述互连结构包括将纳米粒悬浮液喷点在所述管芯周围。
7.根据权利要求6所述的方法,其中在所述管芯周围喷点所述纳米粒悬浮液包括利用多个喷点步骤在所述管芯周围喷点所述纳米粒悬浮液。
8.根据权利要求1所述的方法,其中所述纳米粒功能性可以包括氨-硅烷盐、硅烷偶联剂、硫醇基和聚合物中的至少一种。
9.根据权利要求1所述的方法,还包括,其中所述互连结构包括无铅焊料互连结构和铜互连结构中的至少一种。
10.根据权利要求6所述的方法,还包括,其中设置在所述管芯和衬底之间的管芯间隙区域基本未填充有所述纳米粒悬浮液。
11.一种方法,包括:
在设置在管芯上的互连结构上形成包括排列纳米管阵列的层;
连接焊料凸块至所述互连结构;以及
施加底部填充材料至涂覆有所述层的所述互连结构。
12.根据权利要求11所述的方法,还包括,其中通过离位和原位方法中的至少一种形成所述层。
13.根据权利要求11所述的方法,还包括,其中所述焊料凸块在连接所述焊料凸块至所述互连结构期间回流,并且其中将所述层接合至所述焊料凸块。
14.根据权利要求11所述的方法,还包括,其中所述管芯包括微电子封装的一部分,并且其中将所述焊料凸块设置在所述微电子封装的衬底上。
15.一种结构,包括:
设置在互连结构上的功能化纳米粒层,所述互连结构设置在管芯上;以及
设置在所述功能化纳米粒层上的底部填充材料。
16.根据权利要求15所述的结构,其中所述底部填充材料包括环氧树脂底部填料并且基本润湿涂覆有所述功能化纳米粒的所述互连结构。
17.根据权利要求15所述的结构,其中所述管芯包括微电子封装的一部分,并且其中焊料凸块设置在所述微电子封装的衬底部分上。
18.根据权利要求15所述的结构,其中所述纳米粒功能性可以包括氨-硅烷盐、硅烷偶联剂、硫醇基和聚合物中的至少一种。
19.根据权利要求15所述的结构,其中所述互连结构包括无铅焊料互连结构和铜互连结构中的至少一种。
20.根据权利要求17所述的结构,其中设置在所述管芯和所述衬底之间的管芯间隙区域基本未填充有纳米粒悬浮液。
21.根据权利要求17所述的结构,其中所述层的厚度包括大约10至大约500纳米。
22.一种结构,包括:
设置在互连结构上的排列纳米管阵列的层和排列纳米线层中的至少一种,所述互连结构设置在管芯上;以及
设置在所述排列纳米管阵列和所述排列纳米线层中的所述至少一种上的底部填充材料。
23.根据权利要求22所述的结构,其中所述排列纳米管阵列的所述层和所述排列纳米线层中的所述至少一种包括润湿所述底部填充材料的开放网络阵列。
24.根据权利要求22所述的结构,其中所述排列纳米管阵列的所述层和所述排列纳米线层中的所述至少一种中的各个基本彼此平行。
25.根据权利要求22所述的结构,其中所述互连结构包括无铅焊料互连结构和铜互连结构中的至少一种。
26.根据权利要求22所述的结构,其中所述管芯包括微电子封装的一部分,并且其中焊料凸块设置在所述微电子封装的衬底部分上。
27.根据权利要求22所述的结构,还包括一种系统,所述系统包括:
通讯上耦合至所述结构的PCB;以及
通讯上耦合至所述结构的DRAM。
28.根据权利要求22所述的结构,其中所述层的厚度包括大约10纳米至大约500纳米。
CN200880106316.1A 2007-09-11 2008-09-03 形成用于改进微电子封装中的第一级互连和环氧树脂底部填料之间的粘结的纳米涂层的方法以及由此形成的结构 Expired - Fee Related CN101803014B (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012024918A1 (zh) * 2010-08-26 2012-03-01 中国科学院微电子研究所 一种半导体结构及其制造方法
CN102468220A (zh) * 2010-11-08 2012-05-23 中国科学院微电子研究所 一种金属互连结构及其形成方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7534648B2 (en) * 2006-06-29 2009-05-19 Intel Corporation Aligned nanotube bearing composite material
US9101931B2 (en) 2007-12-28 2015-08-11 Intel Corporation Controlled fluid delivery in a microelectronic package
KR101709959B1 (ko) * 2010-11-17 2017-02-27 삼성전자주식회사 범프 구조물, 이를 갖는 반도체 패키지 및 반도체 패키지의 제조 방법
JP5708512B2 (ja) * 2012-01-30 2015-04-30 豊田合成株式会社 半導体装置の製造方法及び半導体装置
US8970034B2 (en) * 2012-05-09 2015-03-03 Micron Technology, Inc. Semiconductor assemblies and structures
US9321245B2 (en) 2013-06-24 2016-04-26 Globalfoundries Inc. Injection of a filler material with homogeneous distribution of anisotropic filler particles through implosion
US9734927B2 (en) 2015-04-09 2017-08-15 International Business Machines Corporation Optical capture and isolation of circulating tumor cells in a micro-fluidic device utilizing size selective trapping with optical cogwheel tweezers
US20160368821A1 (en) 2015-06-17 2016-12-22 International Business Machines Corporation Method of glass fabric production including resin adhesion for printed circuit board formation
US20170162536A1 (en) 2015-12-03 2017-06-08 International Business Machines Corporation Nanowires for pillar interconnects
FR3047604B1 (fr) * 2016-02-04 2018-02-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif electronique hybride protege contre l'humidite et procede de protection contre l'humidite d'un dispositif electronique hybride
US11031364B2 (en) 2018-03-07 2021-06-08 Texas Instruments Incorporated Nanoparticle backside die adhesion layer
US10796976B2 (en) * 2018-10-31 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6741019B1 (en) * 1999-10-18 2004-05-25 Agere Systems, Inc. Article comprising aligned nanowires
US6492252B1 (en) * 2000-10-13 2002-12-10 Bridge Semiconductor Corporation Method of connecting a bumped conductive trace to a semiconductor chip
US6605491B1 (en) * 2002-05-21 2003-08-12 Industrial Technology Research Institute Method for bonding IC chips to substrates with non-conductive adhesive
CN100521869C (zh) * 2002-05-23 2009-07-29 3M创新有限公司 纳米颗粒填充的底层填料
US6600222B1 (en) * 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US20050014313A1 (en) * 2003-03-26 2005-01-20 Workman Derek B. Underfill method
US7645512B1 (en) * 2003-03-31 2010-01-12 The Research Foundation Of The State University Of New York Nano-structure enhancements for anisotropic conductive adhesive and thermal interposers
JP4412072B2 (ja) * 2003-10-09 2010-02-10 株式会社日立製作所 電子部品の実装方法,半導体モジュール及び半導体装置
US7327037B2 (en) * 2004-04-01 2008-02-05 Lucent Technologies Inc. High density nanostructured interconnection
TWI393226B (zh) * 2004-11-04 2013-04-11 Taiwan Semiconductor Mfg 基於奈米管之填充物
US7309658B2 (en) * 2004-11-22 2007-12-18 Intermolecular, Inc. Molecular self-assembly in substrate processing
US7615476B2 (en) * 2005-06-30 2009-11-10 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012024918A1 (zh) * 2010-08-26 2012-03-01 中国科学院微电子研究所 一种半导体结构及其制造方法
CN102376633A (zh) * 2010-08-26 2012-03-14 中国科学院微电子研究所 一种半导体结构及其制造方法
CN102468220A (zh) * 2010-11-08 2012-05-23 中国科学院微电子研究所 一种金属互连结构及其形成方法
CN102468220B (zh) * 2010-11-08 2013-12-25 中国科学院微电子研究所 一种金属互连结构及其形成方法

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