JP4412072B2 - 電子部品の実装方法,半導体モジュール及び半導体装置 - Google Patents
電子部品の実装方法,半導体モジュール及び半導体装置 Download PDFInfo
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- JP4412072B2 JP4412072B2 JP2004190639A JP2004190639A JP4412072B2 JP 4412072 B2 JP4412072 B2 JP 4412072B2 JP 2004190639 A JP2004190639 A JP 2004190639A JP 2004190639 A JP2004190639 A JP 2004190639A JP 4412072 B2 JP4412072 B2 JP 4412072B2
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Description
10mm,高さ3.7mmと小型化されている。
50nmで構成する。そして、好ましくは、その厚さが5〜100μmである金属層を構成する。
Ni粒子に代えて、該コアの表面に粒子混合物塗布後の乾燥や接合工程における温度において変形や分解が生じない特性を有するものとする。或いは、前記コアは、Cu粒子であり、該コアの表面にNiめっきを施し、その表面層にAu、またはAu合金、或いはAg、またはAg合金をめっきしてなるものとする。或いは、前記コアとして、Cu粒子に代えて、該コアの表面に粒子混合物塗布後の乾燥や接合工程における温度において変形や分解が生じない特性を有するものとする。
図1は、本発明の一実施例である半導体モジュール100の構成を示した概略図であり、図2は、図1のA−A′線に沿う縦断面図である。本実施例の半導体モジュールの厚さは約0.45mmである。
101と基板1とを電気的に接続するためであり、平均粒径5nmの粒子で構成されている。電極108は、回路基板103上に形成され、Sn系ろう材106を介して基板1と電気的に接続されている。基板1上には、コンデンサ,ソレノイド,抵抗等の受動部品
111が、金属ろう材(図示せず)を介して搭載される。エポキシ樹脂110は、基板1上に搭載されたコンデンサ,ソレノイド,抵抗等の受動部品111及びMOSFET素子
101を覆っている。
104の接合部詳細を示したものである。Auバンプ104は、平均粒径5nmの粒子で構成され、電極501を覆っている。基板1上に形成され表面がAuで覆われたNi製電極501は、基板1内部で配線107,106と接続している。MOSFET上に形成した電極502の表面はAuで被覆されている。
Ni電極上に形成させる(c)。乾燥させる際、30℃〜80℃程度の熱を加えてもよい。
MOSFETを接続する(c),(e)。このとき80℃程度の熱を60分間加える。次に、ガラス−セラミック基板上の所定の位置にコンデンサ,ソレノイド,抵抗等の受動部品をPb90wt%、Snを10wt%含むペーストろう材を介して配置する。このPbを主体としたペーストろう材の融点は、MOSFET搭載後のアルミナ基板を回路基板上に搭載する際に用いられるSnを主体としたペーストろう材よりも高い。
MOSFET素子と基板1の接合部の拡大図、すなわち、Auバンプ104の接合部詳細を示したものである。
図1及び図2を参照して本実施例の半導体モジュールの製造方法を説明する。
MOSFET搭載面には金属配線が形成されており、表面はAuめっきされている。コンデンサ,ソレノイド,抵抗等の受動部品111を搭載する側の面にはコンデンサ,ソレノイド,抵抗等の受動部品111の搭載に対応するように電極配線が形成されている。
Auが皮膜されたNi電極501上の撥水膜をレーザ露光法により剥離し、Auが皮膜されたNi電極上のみを親水領域にする(a)。
本実施例では、実施例1及び実施例2におけるAu製バンプをAg製バンプに置換する。以上説明した各実施例は、セルラー電話機等の送信部に用いる高周波電力増幅装置の製造に適用できる。
図9は本発明の実施例の一つである絶縁型半導体装置の構造を示した図である。図9
(a)は上面図、図9(b)は図9(a)A−A′部の断面図である。半導体素子
(MOSFET)301をセラミック絶縁基板302上に、セラミック絶縁基板302をベース材303上にそれぞれろう付け搭載した後、エポキシ系樹脂ケース304,ボンディングワイヤ305,エポキシ系樹脂ふた306を設け、同一ケース内にシリコーンゲル樹脂307を充填した。
311は温度検出用サーミスタ素子で、Sn−3wt%Ag−0.5 wt%Cuはんだ
309でろう付けされ、電極302と端子310との間を直径300μmのAl線305でワイヤボンディングし、外部へ連絡されている。
210には穴210′がそれぞれ設けられ、絶縁型半導体装置1000を外部回路と接続するためのネジ(図示せず)が装着されるようになっている。端子210はあらかじめ所定形状に打抜き、成形された銅板にNiめっきを施したものであり、エポキシ系樹脂ケース220に取り付けられている。
302b,302c、及び302dの表面には厚さ2μmのNiめっき(図示せず)が施されている。また、AlN焼結体302の代替物として窒化珪素焼結体(熱膨張率3.1
ppm/℃,熱伝導率120W/m・K)を用いることができる。
301が4個並列に配置されたブロック1001は、直列に接続され、入力端子Ain,出力端子Aout等が所定の位置から引き出される。また、この回路の稼動時における温度を検出するためのサーミスタ211が絶縁型半導体装置1000内に独立して配置される。
図13は、IGBTを構成する半導体素子のエミッタ電極上に応力緩衝効果のある金属で構成した板を実装した絶縁配線基板の概略図である。IGBTは、IGBTチップ132のエミッタ電極にAuナノ粒子層を介して、応力緩衝板134が設けられている。応力緩衝板134の材質は、Cu,Cu−Cu2O 複合材,Cu−Mo複合材,Cu−W複合材,Cu−インバー−Cu積層材,Cu−Cコンポシット材等で構成される。応力緩衝材
134の表面にはNiめっきを施すことが望ましく、また、厚さは0.05mm〜0.1mm程度の範囲であることが望ましい。応力緩衝板134は、前述と同様の方法で接合されている。
図16は本発明を用いた非絶縁型半導体装置における他の実施例の一つを示した図である。
本実施例は、実施例1で用いた接合層の別の形態を用いた例を説明する。なお、MOSFET素子と基板1との接合層であるAuバンプ104以外の構成,モジュールの製造方法は実施例1と同様である。
106と接続している。MOSFET上に形成した電極502の表面はAuで被覆されている。本実施例では、異なる平均粒径を持つ粒子により構成された層を接合層として用いている。ここで、接合層としては、1乃至50nmの微粒子と1乃至100μmの金属粒子で構成された層とすることが好ましい。
μmの金属粒子としては、AuまたはAu合金からなるもの、あるいはAgまたはAg合金からなるものや、ニッケル粒子をコアとし表面にAuまたはAu合金、あるいはAgまたはAg合金をめっきしたもの、または銅のコア粒子表面にニッケルめっきを施しさらにその表層にAuまたはAu合金、あるいはAgまたはAg合金をめっきしたものを用いることができる。また、コアとなる粒子は金属だけではなく、ポリイミドやポリエーテルイミド等のように粒子混合物塗布後の乾燥や接合工程における温度において変形や分解が生じないものであれば、コア材として使用可能であり、この粒子の表面に無電解法あるいはめっき用導電膜を形成した後に電解法でニッケルめっきを行い、さらに金属粒子の場合と同様にその表面にAuまたはAu合金、あるいはAgまたはAg合金にめっきを施して用いることもできる。
図20を参照して本実施例の半導体モジュールの製造方法を説明する。
Sn系ろう材、107…伝送配線、108…電極、109…集積回路素子、110…樹脂、111…受動部品、112…封止樹脂、113,203…キャップ、115…ボンディングワイヤ、201…放熱フランジ、202…ガラス−セラミック基板、204…リード、205…面付用フィン、206…高周波パワーモジュール。
Claims (10)
- 基板に形成された電極と、電子部品に形成された電極とを接合し、前記基板と外部実装基板または放熱板とを接合する半導体モジュールの実装方法であって、
前記基板と前記電子部品とを平均粒径が1〜50nmで、かつ、Au,Au合金,Ag,Ag合金から選択される少なくとも1種類の微粒子と1〜100μmの金属粒子で構成される金属層により接合した後、
前記基板と前記外部実装基板または放熱板とをSnを主体とするろう材または鉛フリーはんだ材のいずれかで接合することを特徴とする半導体モジュールの実装方法。 - 請求項1において、前記金属層の厚さが5〜100μmであることを特徴とする半導体モジュールの実装方法。
- 請求項1において、前記1〜100μmの金属粒子は、コアと、該コアの表面にコーティングを施して構成されているものを含むことを特徴とする半導体モジュールの実装方法。
- 請求項3において、前記コアは、Ni粒子であり、該コアの表面にAu、またはAu合金、或いはAg、またはAg合金をめっきしてなることを特徴とする半導体モジュールの実装方法。
- 請求項3において、前記コアは、Cu粒子であり、該コアの表面にNiめっきを施し、その表面層にAu、またはAu合金、或いはAg、またはAg合金をめっきしてなることを特徴とする半導体モジュールの実装方法。
- 基板に形成された第一の電極と、半導体素子の電極が形成された領域上に設けられた第二電極とを有し、前記第一の電極と前記第二の電極とが、平均粒径1〜50nmのAu、またはAgから選択される少なくとも一種類の金属の粒子と1〜100μmの金属粒子で構成された金属層により接合され、前記基板と放熱基板とがSnを主体とするろう材,鉛フリーはんだ材のいずれかで接合されていることを特徴とする半導体モジュール。
- 複数の半導体素子が第一の接続材を介して電極が形成された基板に接続され、該基板が外部実装基板に第二の接続材を介して接続された構造を有する半導体モジュールであって、
前記第一の接続材が、平均粒径1〜50nmのAu、またはAgから選択される少なくとも一種類の金属の粒子と1〜100μmの金属粒子で構成された金属層であり、前記第二の接続材がSnを主体とするろう材,鉛フリーはんだ材のいずれかであることを特徴とする半導体モジュール。 - 基板表面に形成した電極と、表面に電極が形成された電子部品が、Au、またはAgから選択される少なくとも1種類以上の金属であって、平均粒径1〜50nmの金属粒子と1〜100μmの金属粒子で構成された層を介して接合され、前記基板と放熱基板とがSnを主体とするろう材,鉛フリーはんだ材のいずれかで接合されていることを特徴とする半導体モジュール。
- 請求項8において、前記平均粒径が1〜100μmの金属粒子がニッケル粒子表面にAuまたはAu合金の層を形成してなることを特徴とする半導体モジュール。
- 請求項8において、前記平均粒径が1〜100μmの粒子表面に平均粒径1〜50nmの微粒子が結合してなることを特徴とする半導体モジュール。
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US10/996,038 US7393771B2 (en) | 2004-06-29 | 2004-11-24 | Method for mounting an electronic part on a substrate using a liquid containing metal particles |
CN2004100978824A CN1717156B (zh) | 2004-06-29 | 2004-11-30 | 电子部件的安装方法、半导体模块及半导体器件 |
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JP4378239B2 (ja) | 2004-07-29 | 2009-12-02 | 株式会社日立製作所 | 半導体装置及びそれを使用した電力変換装置並びにこの電力変換装置を用いたハイブリッド自動車。 |
JP4872663B2 (ja) | 2006-12-28 | 2012-02-08 | 株式会社日立製作所 | 接合用材料及び接合方法 |
DE102007037538A1 (de) * | 2007-08-09 | 2009-02-12 | Robert Bosch Gmbh | Baugruppe sowie Herstellung einer Baugruppe |
US7781260B2 (en) * | 2007-09-11 | 2010-08-24 | Intel Corporation | Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby |
US8513534B2 (en) | 2008-03-31 | 2013-08-20 | Hitachi, Ltd. | Semiconductor device and bonding material |
JP5363839B2 (ja) * | 2008-05-12 | 2013-12-11 | 田中貴金属工業株式会社 | バンプ及び該バンプの形成方法並びに該バンプが形成された基板の実装方法 |
JP5355219B2 (ja) * | 2008-05-21 | 2013-11-27 | 京セラ株式会社 | 発光素子搭載用基板および発光装置 |
DE102009000192A1 (de) * | 2009-01-14 | 2010-07-15 | Robert Bosch Gmbh | Sinterwerkstoff, Sinterverbindung sowie Verfahren zum Herstellen eines Sinterverbindung |
JP5812090B2 (ja) | 2011-03-10 | 2015-11-11 | 富士電機株式会社 | 電子部品および電子部品の製造方法 |
JP2013077745A (ja) * | 2011-09-30 | 2013-04-25 | Rohm Co Ltd | 半導体装置およびその製造方法 |
DE112012006812T5 (de) | 2012-08-17 | 2015-05-21 | Fuji Electric Co., Ltd. | Elektronische Komponente und Fertigungsverfahren für elektronische Komponente |
JP6387048B2 (ja) * | 2016-06-09 | 2018-09-05 | ローム株式会社 | 半導体装置の製造方法 |
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