CN100355063C - 芯片尺寸封装和制备晶片级的芯片尺寸封装的方法 - Google Patents

芯片尺寸封装和制备晶片级的芯片尺寸封装的方法 Download PDF

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CN100355063C
CN100355063C CNB991002563A CN99100256A CN100355063C CN 100355063 C CN100355063 C CN 100355063C CN B991002563 A CNB991002563 A CN B991002563A CN 99100256 A CN99100256 A CN 99100256A CN 100355063 C CN100355063 C CN 100355063C
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chip
layer
semiconductor packages
insulating barrier
patterned conductive
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CN1246731A (zh
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金南锡
张东铉
姜思尹
权兴奎
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

根据本发明，芯片尺寸封装CSP以晶片级制造。CSP包括芯片、用于再分布芯片的芯片焊盘的导电层、一个或两个绝缘层以及通过导电层与相应芯片焊盘相连并为CSP的端子的多个凸起。此外，为改善CSP的可靠性，提供了加强层、边缘保护层和芯片保护层。加强层吸收当CSP安装在线路板上并被长期使用时作用于凸起的应力，并延长凸起及CSP的寿命。边缘保护层和芯片保护层防止外力损坏CSP。在半导体晶片上形成所有构成CSP的元件之后，锯切半导体晶片，得到单个CSP。

Description

芯片尺寸封装和制备晶片级的芯片尺寸封装的方法
技术领域
本发明涉及芯片尺寸封装和制备晶片级的芯片尺寸封装的方法。
背景技术
电子设备的小型化是电子工业的主要趋势之一，已引起制备小封装的许多技术的发展，特别是与半导体集成电路芯片几乎同等大小的封装。联合电子设备工程协会(JEDEC)已提出名称为“芯片尺寸封装(CSP)”的一种小封装。JEDEC对CSP的定义是其封装具有的外形为封装所含的半导体芯片外形的1.2倍或更小。
许多公司和学会已研制他们自己的CSP制造技术，有些已使他们自己的技术或产品商业化。然而，大多数新研制的CSP与在半导体工业中成熟的塑料封装相比，在产品可靠性、工艺可靠性和制造成本方面存在许多缺陷。因此，为广泛和成功商业化CSP，要寻找具有更好工艺和产品可靠性以及较低制造成本的新的CSP。
发明内容
按本发明，以晶片级制备芯片尺寸封装(CSP)。CSP包括用于在半导体芯片上再分布芯片焊盘的导电层；一个或两个绝缘层和作为CSP端子并通过导电层与各自芯片焊盘互连的焊料球。在一个实施例中，导电层直接形成在半导体晶片表面或钝化层上，而在另一实施例中，在半导体晶片表面上形成绝缘层之后，导电层形成在绝缘层上。在这两个实施例中，另一绝缘层形成在导电层上，附加的金属层形成在芯片焊盘与导电层之间以及焊料球与导电层之间，用于改善界面完整性。
此外，为改善CSP的可靠性，提供加强层、边缘层保护层和芯片保护层。形成在绝缘层上的加强层吸收当CSP安装在线路板上并被长期使用时作用于焊料球的应力，并且延长焊料球的寿命。边缘保护层在半导体晶片上沿着半导体晶片上的划片线形成，而芯片保护层形成在半导体晶片的背面。边缘保护层和芯片保护层防止外部力损坏CSP。在半导体晶片上形成CSP的所有元件之后，锯切半导体晶片以产生单个CSP。
按本发明的CSP制造方法采用了现有的技术，因此不需要开发新技术或设备。而且，本发明的晶片级CSP制造比将半导体晶片锯切成集成电路芯片之后一次对一个芯片制造CSP的芯片级CSP制造有更高生产率。
附图说明
图1是包括半导体集成电路芯片和形成在其上的划片线的半导体晶片的顶部示意图。
图2是图1的半导体晶片的部分截面图。
图3表示在半导体晶片表面形成金属层之后的图2的结构。
图4表示在金属层上形成图形化光刻胶层之后的图3的结构。
图5表示利用图形化光刻胶层作为掩模，蚀刻金属层以产生图形化导电层之后的图4的结构。
图6表示清除图形化光刻胶层之后的图5的结构。
图7表示在包括图形化导电层的半导体晶片的整个表面上形成绝缘层之后的图6的结构。
图8表示为使图形化导电层露出，金属凸起与图形化导电层互连，在形成开口之后的图7的结构。
图9表示在半导体晶片的整个表面上形成阻挡层之后的图8的结构。
图10表示为使绝缘层的开口和围绕开口的部分绝缘层露出，在形成另一光刻胶层之后的图9的结构。
图11表示在未被光刻胶层覆盖的区域上形成中间凸起之后的图10的结构。
图12表示清除光刻胶层之后的图11的结构。
图13表示清除阻挡层之后的图12的结构。
图14表示在绝缘层上形成加强层之后的图13的结构和根据本发明实施例的CSP的示意横截面图。
图15是按本发明的CSP的示意底视图。
图16表示在除芯片焊盘之外的半导体晶片的整个表面上形成下绝缘层之后的结构。
图17表示在半导体晶片的整个表面上形成粘合层之后的图16的结构。
图18表示在粘合层上形成图形化光刻胶层之后的图17的结构。
图19表示在粘合层上形成图形化导电层之后的图18的结构，此处没有图形化光刻胶层。
图20表示清除图形化光刻胶层和图形化光刻胶层下的粘合层之后的图19的结构。
图21表示在除将形成焊料球的地方以外的半导体晶片的整个表面上形成上绝缘层之后的图20的结构。
图22表示加强层形成在上绝缘层上之后的图21的结构和按本发明另一实施例的CSP的示意横截面图。
图23表示按本发明的包括边缘保护层和芯片保护层的部分半导体晶片。
图24是由图23的半导体晶片锯切的CSP的横截面图。
图25是在没有边缘保护层和芯片保护层时会发生损坏的CSP的横截面图。
不同图中的相同参考标号表示类似或同一元件。
具体实施方式
本发明提供包括多个特征的CSP，它可改善封装的可靠性和CSP的晶片级制造方法。
图2-14说明了按本发明实施例的CSP和制造CSP的方法。特别是，图14表示CSP的部分横截面图。
如图1所示，图14的CSP制造由具有多个半导体集成电路芯片50和在半导体芯片50之间的划片线52的半导体晶片40开始。图2是表示芯片焊盘12和半导体芯片50的钝化层14的半导体晶片40的部分截面图。芯片焊盘12是连接半导体芯片50的外围电路(未示出)的多个芯片焊盘中的一个，并提供外部电连接的入口。由于制造图1的半导体晶片40为公知技术，这里不再详细解释其制备。
参考图3，金属层16在包括芯片焊盘12和钝化层14的半导体晶片的整个表面上形成，从而在金属层16与芯片焊盘12之间形成电连接。金属层16的厚度大于构成钝化层14下面的芯片电路图形的金属层(未示出)厚度，优选1-5μm。金属层16可由多种材料构成，包括铜、铝、镍、铜合金、铝合金和镍合金，但不限定于此。
在半导体晶片40表面上形成金属层16之后，进行金属层16的构图以形成图形化导电层17，如图4-6所示。首先，如图4所示，在金属层16上形成图形化光刻胶层18。图形化光刻胶层18只覆盖将构成图形化导电层17的区域。然后，蚀刻金属层16(图5)并清除图形化光刻胶层18(图6)得到图形化导电层17，其图形相应于按芯片焊盘12再分布方案。
形成图形化导电层17的另一方法是在芯片焊盘12和钝化层14上直接丝网印刷导电胶(未示出)，并固化导电胶以产生图形化导电层17。导电胶的具体例可以是金属颗粒与粘合树脂的混合物。
图7表示图形化导电层17形成之后的在半导体晶片40的整个表面上形成的绝缘层24。绝缘层24变成图14的CSP的一部分，因此，它应具有希望的性能，例如，低吸湿率、低介电常数和低热膨胀系数。考虑到这些性能，BCB(苯并环丁烯)适合绝缘层24。象BCB一样，如聚酰亚胺与环氧的其他聚合物和如四氮化三硅、二氧化硅以及四氮化三硅与二氧化硅混合的无机材料也可用于绝缘层24。传统的旋涂法可形成聚合物绝缘层，而传统的化学气相淀积法可形成无机绝缘层。在两种情况下，绝缘层厚度优选2-50μm。
参考图8，部分清除绝缘层24以形成对着凸起焊盘22的开口，凸起焊盘22是经该开口露出的部分图形化导电层17。凸起焊盘22称为再分布芯片焊盘12，而凸起焊盘22的位置取决于包括凸起焊盘22的CSP表面安装的线路板的设计。
开口形成之后，形成金属阻挡层26，覆盖绝缘层24和凸起焊盘22，如图9所示。阻挡层26不仅防止图14的图形化导电层17与凸起32之间的扩散，还提高了图形化导电层17与凸起之间的粘合力。而且，阻挡层26为凸起焊盘22上的凸起32提供电镀金属中的电供给介质。阻挡层26通常包括两个或三个子层，例如，包括钛/铜、钛/钛-铜/铜、铬/铬-铜/铜、钛-钨/铜、铝/镍/铜或铝/镍-钒/铜的结构。在形成钛/钛-铜/铜或铬/铬-铜/铜的结构中，溅射设备同时采用两个靶以便该结构由中间层、钛-铜层或铬-铜层形成。在形成图3的金属层16之前，与阻挡层26结构相同的粘合层(未示出)形成在芯片焊盘12与金属层16之间。阻挡层26与粘合层的厚度为1μm或更小，优选0.8-1.0μm。
如图10所示，阻挡层26上形成另一光刻胶层28，使绝缘层24中的开口和围绕开口的区域露出。然后，凸起32的金属，优选焊料合金中的金属被镀覆，以在未被光刻胶层28覆盖的区域上形成中间凸起30，如图11所示。替代镀覆法，焊料膏的丝网印刷、预制焊料球的置换或在绝缘层中的开口处溅射液体焊料剂的金属喷溅法也可产生中间凸起30。形成中间焊料球30之前，在凸起焊盘22的阻挡层26上形成几微米到数十微米厚的铜层(未示出)，以防止回流处理过程中由中间焊料球30与阻挡层26之间扩散而引起的可靠性问题，回流处理熔化中间焊料球30，再成型焊料球32。
形成中间焊料球30之后，通过蚀刻清除光刻胶层28和阻挡层26，而只有中间焊料球30下面的阻挡金属部分27被保留，如图12所示。然后，传统的回流方法再成型中间焊料球30成焊料球32，如图13所描述。在该实施例中，焊料球32的高度在350μm到500μm之间。
此外，如图1 4所示，绝缘层24上形成加强层34，以支撑焊料球32并吸收当CSP安装在线路板(未示出)上并长期使用时作用于焊料球32的应力。由此应力引起的断裂是形成覆盖层34的现有CSP的常见问题，具有低粘度的液体聚合物可被分配并固化。低粘度的液体聚合物使得表面张力将聚合物向上凸起31的侧面并形成凸起32的凹型支撑。优选固化后高抗弯强度的聚合物，这是由于抗弯强度越高，加强层34越能从焊料球32吸收更多应力。加强层34不应覆盖焊料球32的顶部。优选地，加强层34在比焊料球32的顶部低焊料球高度的1/4的点处与焊料球32相交。
最后，沿划片线52锯切经过图2-14所示步骤的半导体晶片40，产生图15示意的各个CSP。
在实际应用中为对CSP提供更多个保护，使CSP免受外来冲击和作用于CSP的热-机械应力，本发明另一实施例包括两个绝缘层和附加保护层。该实施例参考图16-24来描述。
参考图16，在包括芯片焊盘12和钝化层14的半导体晶片40上形成下绝缘层60。在半导体晶片40的整个表面上形成绝缘层之后，蚀刻芯片焊盘12上的绝缘层，产生为下一步互连接的开口。传统的蚀刻方法可清除芯片焊盘12上的绝缘层。下绝缘层60变成图22的CSP的一部分，其应具有理想的性能，如低吸湿率、低介电常数和低热膨胀系数。如BCB、聚酰亚胺与环氧的聚合物和如四氮化三硅、二氧化硅以及四氮化三硅与二氧化硅混合的无机材料可用于下绝缘层60。在它们当中优选BCB用于下绝缘层60。形成下绝缘层60的工艺与如上所述形成绝缘层24的工艺一样。下绝缘层60的厚度优选2-50μm。
形成下绝缘层之后，形成粘合层62，它覆盖下绝缘层60和芯片焊盘12，如图17所示。粘合层62能增强图19的图形化导电层66与芯片焊盘12之间的粘合力。粘合层62通常包括两个或三个子层，如钛/铜、钛/钛-铜/铜、铬/铬-铜/铜、钛-钨/铜、或铝/镍/铜。粘合层62的厚度约为0.5μm。
参考图18-20，解释图形化导电层66的形成。首先，在其上包括粘合层62的下绝缘层60上形成图形化光刻胶层64，使图形化光刻胶层64不存在于将形成图形化导电层66的地方。然后，在粘合层62上利用沉积法形成图形化导电层66，经图形化光刻胶层64使粘合层62暴光。剥离法清除图形化光刻胶层64而蚀刻法使粘合层62暴露。图形化导电层66由多种材料组成，包括铜、铝、镍、铜合金、铝合金和镍合金，但不限定于此。另一方面，能以与参考图3-6所示的类似方法完成图形化导电层66的形成。
如图21所示，形成图形化导电层66之后，形成上绝缘层68，将形成凸起74的部分图形化导电层66暴露。之后，形成阻挡层72、凸起74和加强层76，产生图22所示的CSP。由上绝缘层68形成到加强层76形成的制造步骤与参考图7-14所描述的步骤一致。上绝缘层68、阻挡层72、凸起74和加强层76的特征也与如上所述的一致。
实施例还包括更多的保护层：边缘保护层80与芯片保护层82。图23表示沿划片线52形成在半导体晶片40上的边缘保护层80和形成在半导体晶片40背面上的芯片保护层82。锯切图23的半导体晶片40得到图24的CSP100。在不存在边缘保护层80和芯片保护层82的情况下，晶片锯切和CSP100的随后处理会使CSP存在缺陷，如图25所示的边缘修整。
边缘保护层80可在使用掩模通过丝网印刷或刻印如环氧树脂的聚合物并固化聚合物形成凸起74之前形成。边缘保护层80最好比划片线52宽，从而边缘保护层80一部分沿周边保留在CSP上，如图24所示。边缘保护层80的高度小于凸起74的高度。边缘保护层80的高度优选小于凸起74的高度的1/10。
芯片保护层82可在通过旋涂如聚酰亚胺和环氧的聚合物于半导体晶片的背面上完成半导体晶片的制备之后形成。优选芯片保护层的厚度为2-50μm。
按本发明制备的CSP与以前工艺的其它CSP相比具有许多优点。其优点包括提高的焊料球可靠性、由边缘保护层与芯片保护层对CSP的保护以及改善的可制造性。加强层吸收当CSP安装在线路板上并被长期使用时作用于焊料球的应力，并延长焊料球及CSP的寿命。边缘保护层和芯片保护层防止了外来力对CSP的损坏。按本发明的CSP制造方法应用了现有技术，因此不需要研制新技术或设备。而且，，本发明的晶片级CSP制造方法与在锯切半导体集成电路芯片之后产生CSP的芯片级CSP制造相比有更高生产率。
尽管本发明已参考特定实施例进行描述，但该描述是本发明应用的例子但并不限定于此。所公开的实施例特征的各种应用与结合均在附属权利要求所确定的范围内。

Claims (27)

1.一种半导体封装，包括：
具有多个芯片焊盘和钝化层的半导体集成电路芯片：
与相应芯片焊盘电连接的多个凸起的外端子；
将芯片焊盘与相应外端子相连的图形化导电层；
形成在图形化导电层上的上绝缘层，上绝缘层具有多个开口，经开口该外端子与图形化导电层相连；以及
覆盖并填充外端子之间的空间的加强层，该加强层为外端子提供围绕支撑。
2.权利要求1的半导体封装，其特征在于上绝缘层包含从苯并环丁烯、聚酰亚胺和环氧树脂组成的组中选择的聚合物材料。
3.权利要求1的半导体封装，还包括形成在图形化导电层与半导体芯片的钝化层之间的下绝缘层，下绝缘层具有多个开口，芯片焊盘经开口与图形化导电层相连。
4.权利要求1的半导体封装，还包括形成在半导体芯片背面上的芯片保护层。
5.权利要求4的半导体封装，其特征在于芯片保护层包含聚合物。
6.权利要求4的半导体封装，其特征在于芯片保护层的厚度为2-50μm。
7.权利要求1的半导体封装，还包括在半导体封装顶表面上沿周边形成的边缘保护层。
8.权利要求7的半导体封装，其特征在于边缘保护层由聚合物组成。
9.权利要求1的半导体封装，其特征在于加强层位于与外端子尖端相连的表面之下。
10.一种制造半导体封装的方法，包括：
提供具有多个半导体集成电路芯片和多个划片线的半导体晶片，每个半导体芯片在其上具有多个芯片焊盘与钝化层：
在钝化层上形成图形化导电层；
在图形化导电层上形成绝缘层；
形成多个半导体封装的外端子；以及
锯切晶片以分离半导体集成电路芯片，
其中图形化导电层将每个芯片焊盘与相应的外端子相连，绝缘层包括多个开口，外端子经此开口与图形化导电层相连。
11.权利要求10的制造半导体封装的方法，其特征在于形成外端子的步骤包括：
在绝缘层的开口处设置焊料球，以使每个焊料球位于相关的开口上；以及
加热焊料球使之重新成型，并将焊料球附着于图形化导电层。
12.权利要求10的制造半导体封装的方法，其特征在于形成外端子的步骤包括：
利用具有多个掩模开口的掩模来丝网印刷焊料膏，每个掩模开口对应每个凸起开口；以及
加热焊料膏以形成附着于凸起焊盘的焊料球。
13.权利要求10的制造半导体封装的方法，还包括在绝缘层上形成加强层，其中外端子经加强层露出。
14.权利要求13的制造半导体封装的方法，其特征在于加强层由聚合物组成。
15.权利要求14的制造半导体封装的方法，其特征在于形成加强层包括分配液体聚合物给加强层并固化该聚合物。
16.权利要求13的制造半导体封装的方法，其特征在于加强层位于与外端子尖端相连的表面之下。
17.权利要求10的制造半导体封装的方法，其特征在于形成图形化导电层包括丝网印刷导电胶并固化该胶。
18.权利要求10的制造半导体封装的方法，其特征在于形成图形化导电层包括镀覆金属层并蚀刻该金属层。
19.权利要求10的制造半导体封装的方法，其特征在于绝缘层包含从苯并环丁烯、聚酰亚胺和环氧树脂组成的组中选择的聚合物材料。
20.权利要求10的制造半导体封装的方法，还包括在半导体晶片背侧上形成芯片保护层。
21.权利要求20的制造半导体封装的方法，其特征在于芯片保护层由旋涂法形成。
22.权利要求10的制造半导体封装的方法，还包括沿在半导体晶片的上表面上的划片线形成芯片边缘保护层。
23.权利要求22的制造半导体封装的方法，其特征在于形成芯片边缘保护层包括在晶片的划片线上分配液体材料。
24.一种制造半导体封装的方法，包括：
提供具有多个半导体集成电路芯片和多个划片线的半导体晶片，每个半导体芯片具有在其上的多个芯片焊盘和钝化层；
在半导体芯片的钝化层上形成下绝缘层，下绝缘层具有在芯片焊盘上方的开口；
形成经下绝缘层中的开口与芯片焊盘相连的图形化导电层；
在图形化导电层上形成上绝缘层，上绝缘层具有开口，该开口使图形化导电层的一部分露出；
在上绝缘层的开口处形成半导体封装的多个外端子，该外端子与图形化导电层相连，其中图形化导电层将每个芯片焊盘与相应的外端子相连；
在上绝缘层上形成加强层；以及
锯切晶片以分离半导体集成电路芯片。
25.权利要求24的制造半导体封装的方法，其特征在于上绝缘层包含从苯并环丁烯、聚酰亚胺和环氧树脂组成的组中选择的聚合物材料。
26.权利要求24的制造半导体封装的方法，其特征在于下绝缘层包含从苯并环丁烯、聚酰亚胺和环氧树脂组成的组中选择的聚合物材料。
27.权利要求24的制造半导体封装的方法，其特征在于下绝缘层由无机材料构成。
CNB991002563A 1998-08-28 1999-01-25 芯片尺寸封装和制备晶片级的芯片尺寸封装的方法 Expired - Fee Related CN100355063C (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101924042A (zh) * 2009-03-20 2010-12-22 台湾积体电路制造股份有限公司 裸片堆叠密封结构的形成方法

Families Citing this family (167)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW396462B (en) * 1998-12-17 2000-07-01 Eriston Technologies Pte Ltd Bumpless flip chip assembly with solder via
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
JP3756689B2 (ja) * 1999-02-08 2006-03-15 沖電気工業株式会社 半導体装置及びその製造方法
EP1168912B1 (en) 1999-03-23 2007-05-09 Hibernation Therapeutics Limited Organ arrest, protection and preservation
US6277669B1 (en) * 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
KR100313706B1 (ko) 1999-09-29 2001-11-26 윤종용 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6528349B1 (en) * 1999-10-26 2003-03-04 Georgia Tech Research Corporation Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability
US6507113B1 (en) * 1999-11-19 2003-01-14 General Electric Company Electronic interface structures and methods of fabrication
JP2001185845A (ja) * 1999-12-15 2001-07-06 Internatl Business Mach Corp <Ibm> 電子部品の製造方法及び該電子部品
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
MY131961A (en) * 2000-03-06 2007-09-28 Hitachi Chemical Co Ltd Resin composition, heat-resistant resin paste and semiconductor device using them and method for manufacture thereof
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
JP2002050647A (ja) * 2000-08-01 2002-02-15 Sharp Corp 半導体装置及びその製造方法
TW494548B (en) * 2000-08-25 2002-07-11 I-Ming Chen Semiconductor chip device and its package method
JP2002198374A (ja) * 2000-10-16 2002-07-12 Sharp Corp 半導体装置およびその製造方法
US6693358B2 (en) * 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
US6498088B1 (en) 2000-11-09 2002-12-24 Micron Technology, Inc. Stacked local interconnect structure and method of fabricating same
US7498196B2 (en) * 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
KR100424168B1 (ko) * 2001-06-07 2004-03-24 주식회사 하이닉스반도체 웨이퍼 레벨 패키지의 제조방법
JP2003045877A (ja) * 2001-08-01 2003-02-14 Sharp Corp 半導体装置およびその製造方法
US6747348B2 (en) * 2001-10-16 2004-06-08 Micron Technology, Inc. Apparatus and method for leadless packaging of semiconductor devices
KR100429856B1 (ko) * 2001-11-15 2004-05-03 페어차일드코리아반도체 주식회사 스터드 범프가 있는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
KR100403352B1 (ko) * 2001-12-21 2003-10-30 주식회사 하이닉스반도체 솔더 페이스트 웨이퍼 레벨 패키지 및 그 제조 방법
US6750547B2 (en) * 2001-12-26 2004-06-15 Micron Technology, Inc. Multi-substrate microelectronic packages and methods for manufacture
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6635503B2 (en) * 2002-01-28 2003-10-21 Cree, Inc. Cluster packaging of light emitting diodes
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
KR100461718B1 (ko) * 2002-03-18 2004-12-14 삼성전기주식회사 칩 패키지 및 그 제조방법
KR100452819B1 (ko) * 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6836023B2 (en) * 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
US6903001B2 (en) * 2002-07-18 2005-06-07 Micron Technology Inc. Techniques to create low K ILD for BEOL
JP2004063672A (ja) * 2002-07-26 2004-02-26 Oki Electric Ind Co Ltd 有機絶縁膜の形成方法、及び半導体装置の製造方法
US6845901B2 (en) * 2002-08-22 2005-01-25 Micron Technology, Inc. Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece
US6885101B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20050012225A1 (en) * 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
US20050176233A1 (en) * 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
KR100490886B1 (ko) * 2002-11-22 2005-05-23 삼성물산 주식회사 삼축압축시험기
CA2551169A1 (en) * 2002-12-23 2004-07-08 Global Cardiac Solutions Pty Ltd Organ preconditioning, arrest, protection, preservation and recovery
US6762074B1 (en) 2003-01-21 2004-07-13 Micron Technology, Inc. Method and apparatus for forming thin microelectronic dies
JP3918936B2 (ja) * 2003-03-13 2007-05-23 セイコーエプソン株式会社 電子装置及びその製造方法、回路基板並びに電子機器
SG137651A1 (en) * 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
US6885108B2 (en) * 2003-03-18 2005-04-26 Micron Technology, Inc. Protective layers formed on semiconductor device components so as to reduce or eliminate the occurrence of delamination thereof and cracking therein
TWI242848B (en) * 2003-03-26 2005-11-01 Advanced Semiconductor Eng Chip scale package and method for marking the same
DE10318074B4 (de) * 2003-04-17 2009-05-20 Qimonda Ag Verfahren zur Herstellung von BOC Modul Anordnungen mit verbesserten mechanischen Eigenschaften
US7312101B2 (en) * 2003-04-22 2007-12-25 Micron Technology, Inc. Packaged microelectronic devices and methods for packaging microelectronic devices
US6992001B1 (en) * 2003-05-08 2006-01-31 Kulicke And Soffa Industries, Inc. Screen print under-bump metalization (UBM) to produce low cost flip chip substrate
TWI231555B (en) * 2003-06-30 2005-04-21 Advanced Semiconductor Eng Wafer level package and fabrication process thereof
US6974776B2 (en) * 2003-07-01 2005-12-13 Freescale Semiconductor, Inc. Activation plate for electroless and immersion plating of integrated circuits
TWI228306B (en) * 2003-07-21 2005-02-21 Advanced Semiconductor Eng Method for forming a bump protective collar
US6937047B2 (en) * 2003-08-05 2005-08-30 Freescale Semiconductor, Inc. Integrated circuit with test pad structure and method of testing
JP4360873B2 (ja) * 2003-09-18 2009-11-11 ミナミ株式会社 ウエハレベルｃｓｐの製造方法
US7256074B2 (en) * 2003-10-15 2007-08-14 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US20050104171A1 (en) * 2003-11-13 2005-05-19 Benson Peter A. Microelectronic devices having conductive complementary structures and methods of manufacturing microelectronic devices having conductive complementary structures
CN100350580C (zh) * 2004-03-02 2007-11-21 沈育浓 半导体晶片封装体及其封装方法
CN100350578C (zh) * 2004-03-02 2007-11-21 沈育浓 半导体晶片封装体的封装方法
CN100350600C (zh) * 2004-03-02 2007-11-21 沈育浓 半导体晶片封装体及其封装方法
JP4094574B2 (ja) * 2004-03-08 2008-06-04 シャープ株式会社 半導体装置及びその製造方法
JP4264823B2 (ja) * 2004-03-08 2009-05-20 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP4747508B2 (ja) * 2004-04-21 2011-08-17 カシオ計算機株式会社 半導体装置
US7259468B2 (en) * 2004-04-30 2007-08-21 Advanced Chip Engineering Technology Inc. Structure of package
US20050247039A1 (en) * 2004-05-04 2005-11-10 Textron Inc. Disposable magnetic bedknife
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7242102B2 (en) * 2004-07-08 2007-07-10 Spansion Llc Bond pad structure for copper metallization having increased reliability and method for fabricating same
KR100630698B1 (ko) * 2004-08-17 2006-10-02 삼성전자주식회사 솔더볼 접착 신뢰도를 높이는 반도체 패키지 및 그 제조방법
US7425499B2 (en) * 2004-08-24 2008-09-16 Micron Technology, Inc. Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US7417305B2 (en) * 2004-08-26 2008-08-26 Micron Technology, Inc. Electronic devices at the wafer level having front side and edge protection material and systems including the devices
SG120200A1 (en) 2004-08-27 2006-03-28 Micron Technology Inc Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
JP4379284B2 (ja) * 2004-09-29 2009-12-09 株式会社日立製作所 電子装置
TWI273682B (en) * 2004-10-08 2007-02-11 Epworks Co Ltd Method for manufacturing wafer level chip scale package using redistribution substrate
US7339275B2 (en) * 2004-11-22 2008-03-04 Freescale Semiconductor, Inc. Multi-chips semiconductor device assemblies and methods for fabricating the same
KR101030238B1 (ko) * 2004-12-27 2011-04-22 매그나칩 반도체 유한회사 반도체 소자의 범프 형성 방법
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20060162850A1 (en) * 2005-01-24 2006-07-27 Micron Technology, Inc. Methods and apparatus for releasably attaching microfeature workpieces to support members
US7316572B2 (en) * 2005-02-03 2008-01-08 International Business Machines Corporation Compliant electrical contacts
US8384189B2 (en) * 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
US7795134B2 (en) * 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7169248B1 (en) * 2005-07-19 2007-01-30 Micron Technology, Inc. Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods
KR100647483B1 (ko) * 2005-08-19 2006-11-23 삼성전자주식회사 반도체 패키지의 배선 구조물 및 이의 제조 방법, 이를이용한 웨이퍼 레벨 패키지 및 이의 제조 방법
US7807505B2 (en) * 2005-08-30 2010-10-05 Micron Technology, Inc. Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7271086B2 (en) * 2005-09-01 2007-09-18 Micron Technology, Inc. Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7622377B2 (en) * 2005-09-01 2009-11-24 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
DE102005055280B3 (de) * 2005-11-17 2007-04-12 Infineon Technologies Ag Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements
US7749349B2 (en) * 2006-03-14 2010-07-06 Micron Technology, Inc. Methods and systems for releasably attaching support members to microfeature workpieces
US7910385B2 (en) * 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
WO2007137321A1 (en) 2006-05-29 2007-12-06 Hibernation Therapeutics Limited Improved tissue maintenance
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US8592977B2 (en) * 2006-06-28 2013-11-26 Megit Acquisition Corp. Integrated circuit (IC) chip and method for fabricating the same
TWI328844B (en) * 2006-07-12 2010-08-11 Ind Tech Res Inst A packaging structure with protective layers and manufacture method thereof
SG139573A1 (en) * 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
KR101490836B1 (ko) * 2006-07-25 2015-02-09 하이버네이션 테라퓨틱스, 어 케이에프 엘엘씨 외상 치료법
US7944048B2 (en) * 2006-08-09 2011-05-17 Monolithic Power Systems, Inc. Chip scale package for power devices and method for making the same
US7749882B2 (en) 2006-08-23 2010-07-06 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US7868440B2 (en) * 2006-08-25 2011-01-11 Micron Technology, Inc. Packaged microdevices and methods for manufacturing packaged microdevices
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
KR100848198B1 (ko) * 2006-09-19 2008-07-24 어드벤스드 칩 엔지니어링 테크놀로지, 인크. 반도체 디바이스 보호 구조체 및 그 제조 방법
KR100818101B1 (ko) 2006-11-08 2008-03-31 주식회사 하이닉스반도체 웨이퍼 레벨 칩 사이즈 패키지
SG143098A1 (en) * 2006-12-04 2008-06-27 Micron Technology Inc Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US20080169539A1 (en) * 2007-01-12 2008-07-17 Silicon Storage Tech., Inc. Under bump metallurgy structure of a package and method of making same
KR101506356B1 (ko) 2007-01-22 2015-03-26 크리, 인코포레이티드 외부적으로 상호연결된 발광 장치의 어레이를 사용하는 조명 장치 및 그 제조 방법
JP2010517273A (ja) * 2007-01-22 2010-05-20 クリー レッド ライティング ソリューションズ、インコーポレイテッド フォールト・トレラント発光体、フォールト・トレラント発光体を含むシステムおよびフォールト・トレラント発光体を作製する方法
TW200832542A (en) * 2007-01-24 2008-08-01 Chipmos Technologies Inc Semiconductor structure and method for forming the same
TWI419242B (zh) * 2007-02-05 2013-12-11 Chipmos Technologies Inc 具有加強物的凸塊結構及其製造方法
EP2173353B1 (en) * 2007-03-02 2015-05-06 Hibernation Therapeutics, a KF LLC Composition including Adenosine and Lignocaine
US7750449B2 (en) 2007-03-13 2010-07-06 Micron Technology, Inc. Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
CN101295688B (zh) * 2007-04-24 2011-05-11 中芯国际集成电路制造(上海)有限公司 再分布结构及其制作方法和再分布凸点及其制作方法
US20080265394A1 (en) * 2007-04-30 2008-10-30 Mtekvision Co., Ltd. Wafer level package and fabricating method thereof
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
US20090008764A1 (en) * 2007-07-02 2009-01-08 Hsin-Hui Lee Ultra-Thin Wafer-Level Contact Grid Array
SG149726A1 (en) 2007-07-24 2009-02-27 Micron Technology Inc Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
CN103493799A (zh) * 2007-07-25 2014-01-08 低温药理有限公司 改进的器官保护、维护和康复
SG150396A1 (en) * 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
KR100905779B1 (ko) 2007-08-20 2009-07-02 주식회사 하이닉스반도체 반도체 패키지
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
CN101459088B (zh) * 2007-12-13 2010-06-09 中芯国际集成电路制造(上海)有限公司 再分布金属层及再分布凸点的制作方法
CN101459087B (zh) * 2007-12-13 2011-03-23 中芯国际集成电路制造(上海)有限公司 再分布金属线及再分布凸点的制作方法
US7767496B2 (en) 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US8343809B2 (en) 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US20090294961A1 (en) * 2008-06-02 2009-12-03 Infineon Technologies Ag Semiconductor device
US8076786B2 (en) * 2008-07-11 2011-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for packaging a semiconductor package
US7982311B2 (en) * 2008-12-19 2011-07-19 Intel Corporation Solder limiting layer for integrated circuit die copper bumps
CN101882589B (zh) * 2009-05-06 2013-01-16 台湾积体电路制造股份有限公司 集成电路结构的形成方法
KR101055491B1 (ko) * 2009-05-26 2011-08-08 주식회사 네패스 반도체 패키지 및 그 제조 방법
KR101018172B1 (ko) 2009-08-18 2011-02-28 삼성전기주식회사 웨이퍼 레벨 디바이스 패키지의 제조 방법
JP2010016397A (ja) * 2009-09-09 2010-01-21 Seiko Epson Corp 半導体装置、回路基板及び電子機器
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US8362612B1 (en) * 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR101680082B1 (ko) 2010-05-07 2016-11-29 삼성전자 주식회사 웨이퍼 레벨 패키지 및 웨이퍼 레벨 패키지의 형성방법
US8198739B2 (en) 2010-08-13 2012-06-12 Endicott Interconnect Technologies, Inc. Semi-conductor chip with compressible contact structure and electronic package utilizing same
JP2012129452A (ja) * 2010-12-17 2012-07-05 Toshiba Corp 半導体装置、半導体パッケージおよび半導体装置の製造方法
US8912649B2 (en) 2011-08-17 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy flip chip bumps for reducing stress
US9368398B2 (en) 2012-01-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9607921B2 (en) 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US9589862B2 (en) 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US10015888B2 (en) 2013-02-15 2018-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect joint protective layer apparatus and method
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US9437564B2 (en) 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9082780B2 (en) 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
CN102623429A (zh) * 2012-04-11 2012-08-01 日月光半导体制造股份有限公司 封装载体结构
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
KR101514137B1 (ko) * 2013-08-06 2015-04-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
CN105789368B (zh) * 2014-12-22 2017-07-21 中国科学院微电子研究所 半导体器件
KR102333092B1 (ko) * 2015-07-15 2021-12-01 삼성전기주식회사 회로 기판 및 그 제조 방법
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US10787303B2 (en) 2016-05-29 2020-09-29 Cellulose Material Solutions, LLC Packaging insulation products and methods of making and using same
JP6562467B2 (ja) 2016-06-21 2019-08-21 サムスン エレクトロニクス カンパニー リミテッド ファン−アウト半導体パッケージ
KR101952863B1 (ko) * 2016-06-21 2019-02-28 삼성전기주식회사 팬-아웃 반도체 패키지
US11078007B2 (en) 2016-06-27 2021-08-03 Cellulose Material Solutions, LLC Thermoplastic packaging insulation products and methods of making and using same
CN112736052A (zh) * 2020-11-24 2021-04-30 上海艾为电子技术股份有限公司 一种封装结构及其制备方法、封装芯片
CN114038814A (zh) * 2021-11-18 2022-02-11 苏州通富超威半导体有限公司 封装结构及封装结构的形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0845990A (ja) * 1994-07-28 1996-02-16 Mitsubishi Electric Corp 樹脂封止型半導体装置の製造方法
US5683942A (en) * 1994-05-25 1997-11-04 Nec Corporation Method for manufacturing bump leaded film carrier type semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287983A (en) * 1976-01-19 1977-07-22 Hitachi Ltd Production of semiconductor device
JPH053249A (ja) * 1991-06-25 1993-01-08 Sony Corp 半導体装置及びその製造方法
HUT73312A (en) * 1992-09-14 1996-07-29 Badehi Method and apparatus for producing integrated circuit devices, and integrated circuit device
US5904546A (en) * 1996-02-12 1999-05-18 Micron Technology, Inc. Method and apparatus for dicing semiconductor wafers
US5682065A (en) * 1996-03-12 1997-10-28 Micron Technology, Inc. Hermetic chip and method of manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5683942A (en) * 1994-05-25 1997-11-04 Nec Corporation Method for manufacturing bump leaded film carrier type semiconductor device
JPH0845990A (ja) * 1994-07-28 1996-02-16 Mitsubishi Electric Corp 樹脂封止型半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101924042A (zh) * 2009-03-20 2010-12-22 台湾积体电路制造股份有限公司 裸片堆叠密封结构的形成方法
CN101924042B (zh) * 2009-03-20 2012-02-29 台湾积体电路制造股份有限公司 裸片堆叠密封结构的形成方法

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