TW411536B - Chip scale packages and methods for manufacturing the chip scale packages at wafer level - Google Patents

Chip scale packages and methods for manufacturing the chip scale packages at wafer level Download PDF

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Publication number
TW411536B
TW411536B TW088100193A TW88100193A TW411536B TW 411536 B TW411536 B TW 411536B TW 088100193 A TW088100193 A TW 088100193A TW 88100193 A TW88100193 A TW 88100193A TW 411536 B TW411536 B TW 411536B
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Taiwan
Prior art keywords
layer
wafer
patent application
insulating layer
semiconductor
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TW088100193A
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English (en)
Inventor
Nam-Seog Kim
Dong-Hyeon Jang
Sa-Yoon Kang
Heung-Kyu Kwon
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Samsung Electronics Co Ltd
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Publication of TW411536B publication Critical patent/TW411536B/zh

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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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經濟部中央樣车局貝工消費合作社印裝 411536 A7 _____B7_ 五、發明説明(1 ) 發明背景 發明領域 本發明係有關晶片規格包裝物及製備晶元程度之包裝 物之方法。 相關技術之描述 電子裝置之迷你化(其係電子工業之主要趨勢之一) 已導致許多製備小包裝物之技術之發展,特別是具有近乎 與半導體積體電路晶片等大小之包裝物。Joint Eiectronic Engineering Council(JEDEC)已提出“晶片規格包裝物 ’’(CSP)之名詞’其係一種小包裝物,即,CSP之JEDEC之 定義係具有外形為包含於包裝物内之半導體晶片外形之 1.2倍或更小之包裝物》 許多公司及機構已發展其自己之CSP製備技術,且一 些已將其自己之技術或產品商業化。但是,當與半導趙工 業中已建立之塑膠包裝物相比’大部份之此等新發展之 CSP於產品之信賴度、製程之信賴度及製備成本等領域具 有許多缺失。因此,為了商業化之CSP之廣泛及成功,具 有較佳方法及產品可信賴度及較低製備成本之新的CSP被 建議6 綜述 依據本發明,晶片大小之包裝物(csp)以晶元程度製 備之。CSP包含用以使晶片塾再分佈於半導體晶片上之導 體層,一或二個絕緣層及焊料塊,其係作為CSp之終端且 藉由導體層連接至個別之晶片塾。於一實施例中,導體層 本紙張尺度適用中國囷家標隼(CNS ) Μ规格(210父297公^~5 -- ;— I 1 n I n I I : I i n ^ n f ^ *-, (請先聞讀背面之注意事項再¥寫本頁) 411536 A7 B7 五、發明説明(2 ) 係直接形成於半導體晶元之表面或惰性層,於另一實施例 中,於絕緣層形成於半導體晶元表面上後,導體層形成於 絕緣層上。於二實施例中,另一絕緣層係形成於導體層上 ,且額外之金屬層可形成於晶片墊及導體層之間,及焊料 塊及導體層之間,以改良界面整體性。 此外」一之可信賴性,強化層、端緣保護層 及晶片尾瘦供之。形成於上絕緣層上之強化層吸收 CSP置於電路板及被作為延伸期時之施於焊料塊之應力, 且延申焊料塊之生命期。端緣保護層係形成於沿著半導體 晶元上之刻劃線,且晶片保護層係形成於半導體晶元之背 面。端緣保護層及晶片」^護避—兔XLSP屋力。於半 導體晶元上形成所有元素後,半導體晶元切割而製備個別 之CSP。 依據本發礼之方法使用現今可用之技術,因 此,無需發展新的技術或裝f *再者,本發明之晶元程度 之CSP製備係比於使半導體晶元切割成積體電路晶片後於 晶片上製備CSP之晶片程度之更具生產性。 圖示簡要說明 第1圊係半導體晶元之上視圖,其包含半導體積體電 路晶片及形成於其上之刻劃線。 第2圖係第1圖之半導體晶元之部份之截面圍。 第3圖係顯示第2圖之於半導體晶元表面上形成金屬層 後之結構。 第4圖顯示第3圖之於金屬層上形成具圖案之光阻層之 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公着) 1— 1111 7 Γ-裳 .I n 線 (請先閲讀背面之注意事項再壤寫本頁) 經濟部中央標準局貝工消費合作社印装 經濟部中央梂隼局月工消費合作社印製 411536 A7 ___ B7五、發明説明(3 ) 結構》 第5圖顯示第4圖於使用圖案光阻層為光罩蝕刻金屬層 以製備具圖案之導體層之結構。 第6圖係顯示第5圖於移除囷案之光阻層後之結構。 第7圈圖顯示第6圓於包含圖案導體層之半導體晶元之 整個表面上形成絕緣層後之結構》 第8圖顯示第7圖於形成開口如此圈案之導體層被曝露 ’而金屬塊被連接至囷案導體層後之結構。 第9圖類示第8圖之於半導體晶元之整個表面上形成障 壁層後之結構。 第10囷顯示第9圓於形成另一光阻層如此絕緣層開口 及圍繞於開口之絕緣層部份被曝露後之結構。 第π圈顯示第ίο囷於在未以光阻層覆蓋之區域上形成 中間產物塊後之結構》 第12圖顯示第11圖之於移除光阻層後之結構。 第13圖顯示第12圖之於移除障壁層後之結構。 第14圖顯示第13圖於絕緣層上形成強化層後之結構, 且例示依據本發明之實施例之CSP之截面圖》, 第15圖係依據本發明之CSP之底視圖。 第16圖顯示於除晶元墊之半導體晶元之整個表面上形 成較低絕緣層後之結構。 第17圖顯示第16圖於半導體晶元之整個表面上形成黏 著層後之結構。 第18圖顯示第17圖於黏著層上形成具圊案之光阻層後 本紙法尺度適用中SH家標率(CNS )八4胁(21GX297公釐) ~~ -------'--1^-----—-ST-------& m (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印装 411536 五、發明説明(4 ) 之結構。 第19圖顯示第18圖於其間缺乏具圖案之光阻層之黏著 層上形成具圈案之導體層後之結構。 第20圖顯示第19圖之於移除具圖案之光阻層及在具圊 案之光阻層下之黏著層後之結構。 第21圖係第20圖於除其間焊料塊形成者外之半導體晶 元之整個表面上之上絕緣層形成後之結構。 第22圓顯示第21圖於上絕緣層上形成強化層後之結構 及例示依據本發明之例一實施例之截面圓。 第23圊顯示部份之依據本發明之包含端緣保護層及晶 片保護層之半導體晶元。 第24圖係由第23圖之半導體晶元切割而成之CSP之截 面。 第25圖係具有可產生於缺乏端緣保護層及晶片保護層 時產生之受損之CSP之載面圖》 於不同囷中使用相同之參考符號表示相似或相同之項 目0 較佳實施例之詳細描述 本發明提供包含能改良包裝物之信賴性之許多特徵之 CSP及CSP之晶元程度之製造方法。 第2-14圖例示依據本發明之SCP及製備CSP之方法》 特別是,第14圖顯示CSP之部份截面圖。 如第1圖所示’製備第14圖之CSP開始於具有數個半 導體積艘電路晶片50及位於半導體晶片5〇間之刻劃線52之 本紙張尺度適用中国國家標隼(CNS ) A4規格(210 X 297公兼) I 1 n ^ IH ^ 訂 ^ 線 (請先閱讀背面之注意事項再球寫本頁) A7 B7 —»-—4ll53fi 五、發明説明( 半導體晶丨40«第2圈係半導體晶元4〇之-部份之截面圖 ’其顯不晶片塾丨2及半導體晶片5〇之惰性層14。晶片墊12 係連接至半導趙晶片5〇之電路(未示出)之許多晶片墊之 一者,且提供對於外電連接之可能。因製備第〗圖之半導 體晶凡40係已知技術,其製備之詳細解釋在此不為之。 參考第3圖,金屬層16形成於包含晶片墊12及惰性層14 之半導艘晶元40之整個表面上,如此,使金屬層16及晶 片墊12間之電相連接)金屬層i6之厚度係大於構成惰性層 14下之晶片電路圖之金屬層之厚度,且較佳係丨-〜^。金 屬層16可由各種不同金屬製成,包含銅、鋁、鎳、銅合金 '銘合金及鎳合金,但不限於此。 於半導體晶元40表面上形成金屬層後,形成圖案之 導趙層之金屬層16之形成圖案依循之,如第4_6圊所示。 首先’如第4圖所示’具圖案之光阻層18形成於金屬層16 上°具圈案之光阻層18僅覆蓋將構成具圖案之導體層17之 區域。然後’蝕刻金屬層(第5圊)及移除具圖案之光阻 層(第6圖)留下具圖案之導體層17’其具有依據晶片墊12 之再分佈平面之蹰案。 形成具圓案之導體層17之另一方法係直接於晶片墊12 及惰性層14上篩網印刷導體漿料(未示出),且固化該聚 料以製備具圖案之導體層17 »例示之漿料可為金屬顆粒及 黏合樹脂之混合物。 第7圖顯示於形成具圖案之導體層17後形成於整個半 導體晶元40表面上之絕緣層24。絕緣層24變成第14圖中 冬紙張尺度適用中國國家標準(CNS Μ4規格(2丨0X297公釐) τ -·.丨裝丨 .丨訂線 {許先閱讀背面之注$項*.'填寫本頁) 經濟部中央標準局貝工消費合作社印製 8 經濟部中央樣準局員工消費合作社印製 A7 411536 B7 五、發明説明(6 ) 之C S P之·—部份,因此’具有所欲之性質,例如,低済氣 吸收率'低介電常數及低熱膨脹係數》考量此等性質,bcb( 笨并環丁烯)係適於絕緣層24。除BCB外,其它之聚合物 ’例如,聚醯亞胺及環氧化物及無機材料,例如,氮化發 、二氧化矽及氮化矽及二氧化矽之混合可被作為絕緣唐24 。傳統之旋轉塗覆方法可形成聚合物絕緣層,且傳統之化 學蒸氣沈精法可形成無機絕緣層。於此二情況中,絕緣廣 之厚度較佳係2-50um。 參考第8圖’絕緣層24被部份移除以形成塊狀塾22之 開口’其係具圓案之導想層17之一部份,其曝露於開口。 塊狀墊22可被稱為重新分佈之晶片墊12,且晶片墊22之位 置依包含塊狀墊22被表面置放之CSP之板之設計而定。 於形成開口後,金屬障壁層26被形成以覆蓋絕緣層24 及塊狀墊22,如第9圓所示。障壁層26不僅壁免具圖案之 導體層17與塊狀物32間之擴散,如第14圖,亦促進具圈案 之導體層與塊狀物32間之黏者》再者,障壁層26於塊狀墊 22上提供塊狀物32之電子電鑛金質。障壁層 26通常包含二或三個副層,且例如,包含敛/銅、欽/欽-銅 /銅、鉻/鉻-銅/銅、鈦-鎢/藏、鋁/鎳/銅或鋁/鎳-釩/銅之結 橡^於形成鈦/鈦-銅/銅或鉻/鉻-銅/銅之結構中,喷濺裝置 使用二目標以同時形成中壯層,結構中之鈦·銅層或鉻_銅 層。黏著層(未示出),其具有與障壁層26相同之結構, 可於第3圖中之金屬層16形成前形成於晶片墊12及金屬層 16之間》障壁層26及黏著層之厚度係1 u啊或更少,較佳係 本紙張尺度適用中困國家標準(CNS ) A4規格(2! Ο X 297公釐) 9 -----.--_---I^-- {請先聞讀背面之注意事項為填寫本頁) 訂 411536 A7 經濟部中央樣準局員工消費合作社印製 B7五、發明説明(7 ) 0.8-lum。於障壁層26上,如第10圖所示,另一保護層28 形成以使絕緣層24之開口及圍繞開口之區域被曝露》然後 ,塊狀物32之金屬,較佳係焊料合金,被電鍍以於未以光 阻層28覆蓋之區域上形成中間塊狀物30 t如第11圖所示。 替代電鍍方法,焊料漿料之篩網印刷、預形成之焊料球之 置放及金屬喷射方法,其將液態焊料喷於絕觔層内之開口 ,亦可產生中間塊狀物30。於形成絕緣焊料塊狀物30前, 銅層(未示出)可於塊狀墊22之障壁層26上形成數um至 數十um厚,以避免於使金屬中間焊料塊狀物30再成形成 焊料塊狀物32之再流動方法期間因中間焊料塊狀物30與障 壁層26間之擴散而造成之信賴性問題》 於形成中間焊料塊狀物30後,光阻層28及障壁層26藉 料蝕刻移除之,且僅有中間焊料塊30下之障障金屬部份27 保留,如第12圖所示。然後,傳統之重新流動方法使中間 焊料塊30重新成形成焊料塊32,如第13圖所示。於此實施 例中,焊料塊32之高度係位於350um與500um之間。 再者,如第14圖所示,<化層34可形成於絕緣層24上 ,以支持焊料塊32及吸收CSP被置於電路板(未示出\及 作為延伸期使用時施於焊料塊32之應力。此應力造成之失 敗於先前之CSP中係平常之問題》對於形成覆蓋層34,具 有低黏度之液態聚合物可被分散及固化。液態聚合物之低 黏度使表面張力拉伸聚合物至塊狀物31之侧邊,而產生塊 狀物32之凹支持。於固化後之具有較高斷裂強度之聚合物 係較佳,因為斷裂強度愈高,強化層34可自焊料塊32吸收 ----------.丨裝-----^丨訂_------線 - - (請先閱讀背面之注意事項再镇寫本頁) 本紙張尺度適用中國國家梯率(CNS } A4規格(210X297公釐) 411536 A7 B7 經濟部中央樣準局貝工消費合作社印裳 五、發明説明(8 ) 之強化層3 4不應覆蓋焊料塊佳者 係強化層34於低於焊料塊32頂部1/4焊料塊高度之一點與 焊料塊32會面。 最後,經由第2-14圖所例示之步驟之半導體晶元40 沿著刻劃線52切割以製備第15圖所示之個別CSP。 為對CSP提供更多保護以免於實際使用時之外在衝擊 及施用於CSP之熱-機械應力,本發明之另一實施例包含 二絕緣層及另外之保護層。此實施例係描述於第16-24圖 〇 參考第16圊,較低之絕緣層60係成於包含晶片墊12及 惰性層14之半導體晶元40上。於半導體晶元40之整個表 面上形成絕緣層之後,晶片墊12上之絕緣層被蝕刻以製備 作為進一步接連之開口。傳統之蝕刻方法可移除晶片墊12 上之絕緣層。較低之絕緣層60變為CSP1—部价,第22圖 所示,且需具有所欲之性質,諸如,低濕氣吸收率、低介 電常數及低熱膨脹係數。諸如BCB、聚醯亞胺及環氧化物 之聚合物及諸如氮化矽、二氧化矽及氮化矽及二氧化創之 混合物之無機材料可被用於較低之絕緣層60。此等中BCB 係較佳之作為較低絕緣層60 »形成較低絕緣層60之方法基 本上係相同於形成如上所述之絕緣層24之方法。較低絕緣 層60之厚度係較佳為2-5 Oum。 於形成較低絕緣層後,黏著層形成而覆蓋較低絕緣層 60及晶片墊12,如第17圖所示=黏著層62促進第19圖之具 圖案之導體層66與晶片墊12間之黏著。黏著層62 —般包含 本紙張尺度適用中國國家標準(CNS)A4規格( 210X297公釐) ^ 11 ^ ^ 裝 ^ 訂 線 {請先閣讀背面之注意事項异填寫本頁) Α7 Β7 411536 i、發明説明(9 ) 二或三個副層,諸如,鈦/銅、鈦/鈦-銅/銅、鉻/鉻-銅/銅 、欽-鋒/鋼或銘/錄/銅。黏著層62之厚度係約0·5νπχι。 參考第18-20圖,具圖案之導體層66之形成被解釋。 首先,具囷案之光阻層64形成於包含於其上之黏著層62之 較低絕緣層60上,如此具圖案之光阻層於會形成具困案之 導體層66處係缺乏〃然後,沈積方法於黏著層62上形成具 圖案之導體層66,其間黏著層62經由具圖案之光阻層64嗓 露。脫離方法移除具圖案之光阻層64且蝕刻方法曝露黏著 層62。具圖案之導體層66係由各種材料形成,其包含銅、 鋁、鎳、銅合金、鋁合金及鎳合金,但不限於此。另外, 形成具圖案之導體層66可藉由相似於上述參考第3-6圖所 解釋者之方式完成。如第21圖所示,於形成具圖案之導體 層66後,上絕緣層68形成,其曝露具圖案之導體層66之部 份,其間塊狀物74形成。其後,障壁層72,塊狀物74及強 化層76形成’產生如第22囷所示之CSP »自形成上絕緣層 68至形成強化層76之製備步驟係相同於參考第7-14圖所述 之步驟。上絕緣層68,障壁層72,塊狀物74及強化層76之特 徵亦係相同於上述者。 此實施例可進一步包含多個保護層:端緣保護層8〇及 晶片保護層82。第23圖顯示沿著刻劃線52形成於半導體晶 元40上之端緣保護層及形成於半導體晶元4〇背後之晶片 保護層82。切割第23圖中之半導體晶元40造成第24圖中 之CSP100。於缺乏端緣保護層80及晶片保護層82令,晶 元切割及其後之CSP100處理可產生CSP之缺失,諸如,如 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公着) (請先閱讀背面之注意事項再填寫本頁〕 裝 訂 經濟部中央標準局貝工消費合作社印製 12 411536 A7 五、發明説明(10) 第25圖所示之端緣晶片。 於瑰狀物74形成前,端緣保護層80可藉由使用防護罩 或點計聚合物(例如,環氧樹脂)及固化聚合物而形成之 。端緣保護層80較佳係較刻劃線52寬,如此,部份端緣保 護層80沿著週圍留於CSP100上,如第24圖所示》端緣保 護層80之高度係較塊狀物74小。較佳係端緣保護層80之高 度小於塊狀物74之高度之1/10。 晶片保護層8 2可於半導體晶元最後製備後藉由使聚合 物(諸如,聚醯亞胺及環氧化物)旋轉塗覆於半導體晶元 之背後而形成之。晶片保護層之較佳厚度係2-50um。 經濟部中央標準局負工消費合作杜印製 依據本發明製備CSP顯示許多優於習知技藝之其它 CSP之優點。優點包含見可該賴性、藉由端緣 保護層及晶片保護層保護CSP,及改良之可製備性j強化 層吸收當CSP置於電路板上且用於延伸期時施於焊料塊之 應力,且延伸焊料塊之使用期,因此v^OlCSP之先月^ 。端緣保護層及晶片保護層避免CSP受外力而損害。依據 本發明之CSP製備方法使用現今可用之技術,因此,無需 發展新的技術及裝置《再者,本發明之晶元程度之CSP製 備係較晶片程度之製備(其於切割半導體積體電路晶片後 製備CSP)更具生產力》 雖然本發明已參考特殊實施例描述,此等描述及本發 明應用之一例子,且不應被作為限制。所揭露之實施例之 特徵之各種應用及結合係位於如下申請專利範圍所界定之 範圍内。 13 (請先閲讀背面之注意事項寫本頁} 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 411536 A7 B7 五、發明説明(η ) 元件對照表 12…晶片整 40···半導體晶元 14*··惰性層 50…半導體積體電路晶片 16…金屬層 52···刻劃線 17…導體層 60…絕緣層 18…光阻層 62…黏著層 22…塊狀墊 64…光阻層 24…絕緣層 66-··導體層 26…金屬障壁層 68…上絕緣層 27…障壁金屬 72…障壁層 28…保護層 74…塊狀物 30…中間塊狀物 76+*·強化層 3 1…塊狀物 80…端緣保護層 32…塊狀物 82…晶片保護層 34…強化層 ------Γ--,丨裝-----:丨訂_------線 f 0 (請先閱讀背面之注^^項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家橾準(CNS) A4規格(2!0X297公羞) 14

Claims (1)

  1. 經濟部中央標準局員工消費合作社印製 15 A8 B8 C8 * _________D8 六、申請專利ϋ ' ~~~~ i· 一種半導想包裝物,包含: 半導體積體電路晶片,具有數個晶片墊及惰性層 * 數個凸山之外終端,其係電連接至個別之晶片墊 t 具圖案之導體層,其使該晶片幸與個別之外終端 連接;及 強化層,其覆蓋及填充該外終端間之空間,該強 化層提供該外終端之週圍支持。/ 2. 如申請專利範圍第丨項之半導體包裝物,其另外包含 上絕緣層,其係形成於該具囷案之導體層上,該上絕 緣層具有數個開口,經由該等開口,該外終端連接至 該具圖案之導體層。 3. 如申請專利範圍第2項之半導體包裝物,其中該上絕 緣層含有聚合物材料,其係選自苯并環丁烯、聚醯亞 胺及環氧樹脂。 4·如申請專利範圍第1項之半導體包裝物’其另外包含 較低之絕緣層,其係形成於該具圖案之導體層與該半 導體晶片之該惰性層之間,該較低絕緣層具有數個開 口,經由該等開口該晶片墊接連至該具圖案之導體層 〇 5·如申請專利範圍第1項之半導體包裝物,其另外包含 晶片保護層,其係形成於該半導體晶月月後表面上 本纸張尺度適用中國國家橾準(CNS ) A4洗格(210X297公釐)一 (請先閲讀背面之注f項再填寫本頁) .裝- 1T. 線 ABCD 411536 A、申請專利範圍 6. 如申請專利範圍第5項之半導體包裝物,其中該晶片 保護層含有聚合物。 7. 如申請專利範圍第5項之半導體包裝物,其中該晶片 保護層之厚度係2與50um之間。 8-如申請專利範圍第1項之半導體包裝物,其另外包含 端緣保護層’其沿著週圍形成於該半導體包裝物之上 表面。 9. 如申請專利範園第8項之半導體包裝物,其中該端緣 保護層係由聚合物製成。 10. 如申請專利範圍第丨項之半導體包裝物,其中該強化 層係低於連接該外終端之頂部之表面 11·如申請專利範圍第10項之半導體包裝物,其中從該表 面至其間該強化層與該外終端會面之點之垂直距離係 约100um 。 12. —種製備半導艘包裝物之方法,包含: 提供半導體晶元’其具有數個半導體積體電路晶 片及數個刻劃線,每一半導體晶片具有數個晶片墊及 位於其上之惰性層; 於該惰性層上直接形成具圖案之導體層; 於該具圖案之導體層上形成絕緣層; 形成該半導體包裝物之數個外終端;及 本紙張尺度適用中國國家揉率(CNS )八4規格(2ΐ〇χ297公釐) 丨_^ I-_---Γ丨裝------—訂------線 (請先閲讀背面之注$項再填寫本頁) 經濟部中央橾率局員工消費合作社印裝 16 A8 B8 C8 DB 411536 申請專利範圍 將該晶元切割以分離該半導體積體電路晶片; 其中’該具圖案之導體層連接每一晶片塾至個別 之外終端,該絕緣層包含數個開口,經由該等開口, 該外終端連接至該具圖案之導體層。 13. 如申請專利範圍第12項之方法,其中形成該外終端包 含: 於該絕緣層内之開口置放焊料球,如此,每一焊 料球位於相關之開口上;及 加熱該焊料球以使該焊料球重新成形且使該焊料 球附接於該具囷案之導體層。 14. 如申請專利範圍第12項之方法,其中形成該外終端包 含: 使用具有數個防護罩開口之防護罩篩網印刷焊料 漿料,每一個防護罩開口係對應於每一塊狀物開口; 及 加熱該焊料漿液,以形成附著於該塊狀塾上之該 焊料塊狀物β 15. 如申请專利範圍第〗2項之方法,其另外包含於該絕緣 層上形成強化層,其中該外侧終端係經由該強化層曝 出。. 16. 如申請專利範圍第15項之方法,其中該強化層係由聚 合物形成。 i I r! J 裝 訂 111 —ί !線 (錆先閲讀背面之注意事項再填寫本頁) 經濟部中央樣準局負工消費合作社印聚 17 - 411536 Α8 Β8 C8 D8 六、申請專利範圍 17. 如申請專利範圍第16項之方法,其令形成該強化層包 含分散作為該強化層之液態聚合物及固化該聚合物。 18. 如申請專利範圍第15項之方法,其中該強化層低於連 接該外終端之頂部之表面。 19. 如申請專利範圍第18項之方法,其中從該表面至其間 該強化層與該外終端會面之點之垂直距離係約1〇〇um 〇 20. 如申請專利範圍第〗2項之方法,其中該具圈案之導艘 層包含篩網印刷導電漿料及固化該漿料。 21·如申請專利範圍第12項之方法,其中形成該具圈案之 導體層包含電鍍金屬層及蝕刻該金屬層β 22.如申請專利範圍第12項之方法,其中該絕緣層含有聚 合物材料’其係選自苯并環丁烯、聚醯亞胺及環氧樹 脂。 23_如申請專利範圍第12項之方法’另外包含於該半導雜 晶元之後侧上形成晶片保護層。 經濟部中央樣準局貝工消費合作社印裝 24.如申請專利範圍第23項之方法,其中該晶片保護層係 藉由旋轉塗覆方法形成。 25·如申請專利範圍第丨2項之方法,另外包含於該半導艘 晶元之上表面沿著刻劃線形成晶片端緣保護層。 26·如申請專利範圍第25項之方法,其中形成該晶片端緣 保護層包含使液體材料分散於該晶元上之該刻劃線上 18 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家榇準(CNS ) Α4規格(210 X 297公釐) 411536 A8 B8 C8 D8 經濟部中央標準局員工消費合作社印製 夂、申請專利範圍 〇 广 27. —種製備半導體包裝物之方法,包含: 提供半導體晶元’其具有數個半導體積體電路晶 片及數個刻劃線,每一半導體晶片具有數個晶片墊及 位於其上之惰性層; 於該半導艘晶片之該惰性層上形成較啤之絕緣層 ’該較低絕緣層具有位於該晶片墊之開口; 形成具圖案之導體層’其經由該較低絕緣層内之 該等開口連接至該晶片墊; 於該具圖案之導想層上形成上絕緣層,該上絕緣 層具有開口’其曝露該具囷案之導趙層之部份: 於該上絕緣層之開口處形成該半導體包裝物之數 個外終端’該外終端連接至該具圖案之導體層,其中 該具圖案之導體層接連至該個別外終端之每一晶片塾 t 於該上絕緣層上形成強化層;及 將該晶元切割以分離該半導體積體電路晶片。 28. 如申請專利範圍第27項之方法,其中該上絕緣層包含 聚合物材料,其係選自苯并環丁烯、聚醯亞胺及環氣 樹脂。 29_如申請專利範圍第27項之方法,其中該較低絕緣層含 有聚合材料’其係選自笨并環丁烯、聚醯亞胺及環氧 本紙張XAiW t gl國家標率(CNS ) ( 2丨GX297公釐) 19 裝-----^訂------線 (請先閎讀背面之注項再填寫本頁) A8 B8 C8 D8 六、申請專利範圍 樹脂。 30.如申請專利範圍第27項之方法,其中該較低絕緣層係 由無機材料形成" IM 1— T- i裝— : 訂 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印策 20 本紙張尺度適用中國國家標準(CNS ) A4规格(2l〇X25>7公釐)
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10204866B2 (en) 2010-03-12 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US10998248B2 (en) 2007-12-14 2021-05-04 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die

Families Citing this family (166)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW396462B (en) * 1998-12-17 2000-07-01 Eriston Technologies Pte Ltd Bumpless flip chip assembly with solder via
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
JP3756689B2 (ja) * 1999-02-08 2006-03-15 沖電気工業株式会社 半導体装置及びその製造方法
EP1168912B1 (en) 1999-03-23 2007-05-09 Hibernation Therapeutics Limited Organ arrest, protection and preservation
US6277669B1 (en) * 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
KR100313706B1 (ko) 1999-09-29 2001-11-26 윤종용 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6528349B1 (en) * 1999-10-26 2003-03-04 Georgia Tech Research Corporation Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability
US6507113B1 (en) * 1999-11-19 2003-01-14 General Electric Company Electronic interface structures and methods of fabrication
JP2001185845A (ja) * 1999-12-15 2001-07-06 Internatl Business Mach Corp <Ibm> 電子部品の製造方法及び該電子部品
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
MY131961A (en) * 2000-03-06 2007-09-28 Hitachi Chemical Co Ltd Resin composition, heat-resistant resin paste and semiconductor device using them and method for manufacture thereof
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
JP2002050647A (ja) * 2000-08-01 2002-02-15 Sharp Corp 半導体装置及びその製造方法
TW494548B (en) * 2000-08-25 2002-07-11 I-Ming Chen Semiconductor chip device and its package method
JP2002198374A (ja) * 2000-10-16 2002-07-12 Sharp Corp 半導体装置およびその製造方法
US6693358B2 (en) * 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
US6498088B1 (en) 2000-11-09 2002-12-24 Micron Technology, Inc. Stacked local interconnect structure and method of fabricating same
US7498196B2 (en) * 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
KR100424168B1 (ko) * 2001-06-07 2004-03-24 주식회사 하이닉스반도체 웨이퍼 레벨 패키지의 제조방법
JP2003045877A (ja) * 2001-08-01 2003-02-14 Sharp Corp 半導体装置およびその製造方法
US6747348B2 (en) * 2001-10-16 2004-06-08 Micron Technology, Inc. Apparatus and method for leadless packaging of semiconductor devices
KR100429856B1 (ko) * 2001-11-15 2004-05-03 페어차일드코리아반도체 주식회사 스터드 범프가 있는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
KR100403352B1 (ko) * 2001-12-21 2003-10-30 주식회사 하이닉스반도체 솔더 페이스트 웨이퍼 레벨 패키지 및 그 제조 방법
US6750547B2 (en) * 2001-12-26 2004-06-15 Micron Technology, Inc. Multi-substrate microelectronic packages and methods for manufacture
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6635503B2 (en) * 2002-01-28 2003-10-21 Cree, Inc. Cluster packaging of light emitting diodes
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
KR100461718B1 (ko) * 2002-03-18 2004-12-14 삼성전기주식회사 칩 패키지 및 그 제조방법
KR100452819B1 (ko) * 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6836023B2 (en) * 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
US6903001B2 (en) * 2002-07-18 2005-06-07 Micron Technology Inc. Techniques to create low K ILD for BEOL
JP2004063672A (ja) * 2002-07-26 2004-02-26 Oki Electric Ind Co Ltd 有機絶縁膜の形成方法、及び半導体装置の製造方法
US6845901B2 (en) * 2002-08-22 2005-01-25 Micron Technology, Inc. Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece
US6885101B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20050012225A1 (en) * 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
US20050176233A1 (en) * 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
KR100490886B1 (ko) * 2002-11-22 2005-05-23 삼성물산 주식회사 삼축압축시험기
CA2551169A1 (en) * 2002-12-23 2004-07-08 Global Cardiac Solutions Pty Ltd Organ preconditioning, arrest, protection, preservation and recovery
US6762074B1 (en) 2003-01-21 2004-07-13 Micron Technology, Inc. Method and apparatus for forming thin microelectronic dies
JP3918936B2 (ja) * 2003-03-13 2007-05-23 セイコーエプソン株式会社 電子装置及びその製造方法、回路基板並びに電子機器
SG137651A1 (en) * 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
US6885108B2 (en) * 2003-03-18 2005-04-26 Micron Technology, Inc. Protective layers formed on semiconductor device components so as to reduce or eliminate the occurrence of delamination thereof and cracking therein
TWI242848B (en) * 2003-03-26 2005-11-01 Advanced Semiconductor Eng Chip scale package and method for marking the same
DE10318074B4 (de) * 2003-04-17 2009-05-20 Qimonda Ag Verfahren zur Herstellung von BOC Modul Anordnungen mit verbesserten mechanischen Eigenschaften
US7312101B2 (en) * 2003-04-22 2007-12-25 Micron Technology, Inc. Packaged microelectronic devices and methods for packaging microelectronic devices
US6992001B1 (en) * 2003-05-08 2006-01-31 Kulicke And Soffa Industries, Inc. Screen print under-bump metalization (UBM) to produce low cost flip chip substrate
TWI231555B (en) * 2003-06-30 2005-04-21 Advanced Semiconductor Eng Wafer level package and fabrication process thereof
US6974776B2 (en) * 2003-07-01 2005-12-13 Freescale Semiconductor, Inc. Activation plate for electroless and immersion plating of integrated circuits
TWI228306B (en) * 2003-07-21 2005-02-21 Advanced Semiconductor Eng Method for forming a bump protective collar
US6937047B2 (en) * 2003-08-05 2005-08-30 Freescale Semiconductor, Inc. Integrated circuit with test pad structure and method of testing
JP4360873B2 (ja) * 2003-09-18 2009-11-11 ミナミ株式会社 ウエハレベルcspの製造方法
US7256074B2 (en) * 2003-10-15 2007-08-14 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US20050104171A1 (en) * 2003-11-13 2005-05-19 Benson Peter A. Microelectronic devices having conductive complementary structures and methods of manufacturing microelectronic devices having conductive complementary structures
CN100350580C (zh) * 2004-03-02 2007-11-21 沈育浓 半导体晶片封装体及其封装方法
CN100350578C (zh) * 2004-03-02 2007-11-21 沈育浓 半导体晶片封装体的封装方法
CN100350600C (zh) * 2004-03-02 2007-11-21 沈育浓 半导体晶片封装体及其封装方法
JP4094574B2 (ja) * 2004-03-08 2008-06-04 シャープ株式会社 半導体装置及びその製造方法
JP4264823B2 (ja) * 2004-03-08 2009-05-20 Okiセミコンダクタ株式会社 半導体装置の製造方法
JP4747508B2 (ja) * 2004-04-21 2011-08-17 カシオ計算機株式会社 半導体装置
US7259468B2 (en) * 2004-04-30 2007-08-21 Advanced Chip Engineering Technology Inc. Structure of package
US20050247039A1 (en) * 2004-05-04 2005-11-10 Textron Inc. Disposable magnetic bedknife
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7242102B2 (en) * 2004-07-08 2007-07-10 Spansion Llc Bond pad structure for copper metallization having increased reliability and method for fabricating same
KR100630698B1 (ko) * 2004-08-17 2006-10-02 삼성전자주식회사 솔더볼 접착 신뢰도를 높이는 반도체 패키지 및 그 제조방법
US7425499B2 (en) * 2004-08-24 2008-09-16 Micron Technology, Inc. Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US7417305B2 (en) * 2004-08-26 2008-08-26 Micron Technology, Inc. Electronic devices at the wafer level having front side and edge protection material and systems including the devices
SG120200A1 (en) 2004-08-27 2006-03-28 Micron Technology Inc Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
JP4379284B2 (ja) * 2004-09-29 2009-12-09 株式会社日立製作所 電子装置
TWI273682B (en) * 2004-10-08 2007-02-11 Epworks Co Ltd Method for manufacturing wafer level chip scale package using redistribution substrate
US7339275B2 (en) * 2004-11-22 2008-03-04 Freescale Semiconductor, Inc. Multi-chips semiconductor device assemblies and methods for fabricating the same
KR101030238B1 (ko) * 2004-12-27 2011-04-22 매그나칩 반도체 유한회사 반도체 소자의 범프 형성 방법
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20060162850A1 (en) * 2005-01-24 2006-07-27 Micron Technology, Inc. Methods and apparatus for releasably attaching microfeature workpieces to support members
US7316572B2 (en) * 2005-02-03 2008-01-08 International Business Machines Corporation Compliant electrical contacts
US8384189B2 (en) * 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
US7795134B2 (en) * 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7169248B1 (en) * 2005-07-19 2007-01-30 Micron Technology, Inc. Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods
KR100647483B1 (ko) * 2005-08-19 2006-11-23 삼성전자주식회사 반도체 패키지의 배선 구조물 및 이의 제조 방법, 이를이용한 웨이퍼 레벨 패키지 및 이의 제조 방법
US7807505B2 (en) * 2005-08-30 2010-10-05 Micron Technology, Inc. Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7271086B2 (en) * 2005-09-01 2007-09-18 Micron Technology, Inc. Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7622377B2 (en) * 2005-09-01 2009-11-24 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
DE102005055280B3 (de) * 2005-11-17 2007-04-12 Infineon Technologies Ag Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements
US7749349B2 (en) * 2006-03-14 2010-07-06 Micron Technology, Inc. Methods and systems for releasably attaching support members to microfeature workpieces
US7910385B2 (en) * 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
WO2007137321A1 (en) 2006-05-29 2007-12-06 Hibernation Therapeutics Limited Improved tissue maintenance
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US8592977B2 (en) * 2006-06-28 2013-11-26 Megit Acquisition Corp. Integrated circuit (IC) chip and method for fabricating the same
TWI328844B (en) * 2006-07-12 2010-08-11 Ind Tech Res Inst A packaging structure with protective layers and manufacture method thereof
SG139573A1 (en) * 2006-07-17 2008-02-29 Micron Technology Inc Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
KR101490836B1 (ko) * 2006-07-25 2015-02-09 하이버네이션 테라퓨틱스, 어 케이에프 엘엘씨 외상 치료법
US7944048B2 (en) * 2006-08-09 2011-05-17 Monolithic Power Systems, Inc. Chip scale package for power devices and method for making the same
US7749882B2 (en) 2006-08-23 2010-07-06 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US7868440B2 (en) * 2006-08-25 2011-01-11 Micron Technology, Inc. Packaged microdevices and methods for manufacturing packaged microdevices
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
KR100848198B1 (ko) * 2006-09-19 2008-07-24 어드벤스드 칩 엔지니어링 테크놀로지, 인크. 반도체 디바이스 보호 구조체 및 그 제조 방법
KR100818101B1 (ko) 2006-11-08 2008-03-31 주식회사 하이닉스반도체 웨이퍼 레벨 칩 사이즈 패키지
SG143098A1 (en) * 2006-12-04 2008-06-27 Micron Technology Inc Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US20080169539A1 (en) * 2007-01-12 2008-07-17 Silicon Storage Tech., Inc. Under bump metallurgy structure of a package and method of making same
KR101506356B1 (ko) 2007-01-22 2015-03-26 크리, 인코포레이티드 외부적으로 상호연결된 발광 장치의 어레이를 사용하는 조명 장치 및 그 제조 방법
JP2010517273A (ja) * 2007-01-22 2010-05-20 クリー レッド ライティング ソリューションズ、インコーポレイテッド フォールト・トレラント発光体、フォールト・トレラント発光体を含むシステムおよびフォールト・トレラント発光体を作製する方法
TW200832542A (en) * 2007-01-24 2008-08-01 Chipmos Technologies Inc Semiconductor structure and method for forming the same
TWI419242B (zh) * 2007-02-05 2013-12-11 Chipmos Technologies Inc 具有加強物的凸塊結構及其製造方法
EP2173353B1 (en) * 2007-03-02 2015-05-06 Hibernation Therapeutics, a KF LLC Composition including Adenosine and Lignocaine
US7750449B2 (en) 2007-03-13 2010-07-06 Micron Technology, Inc. Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
CN101295688B (zh) * 2007-04-24 2011-05-11 中芯国际集成电路制造(上海)有限公司 再分布结构及其制作方法和再分布凸点及其制作方法
US20080265394A1 (en) * 2007-04-30 2008-10-30 Mtekvision Co., Ltd. Wafer level package and fabricating method thereof
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
US20090008764A1 (en) * 2007-07-02 2009-01-08 Hsin-Hui Lee Ultra-Thin Wafer-Level Contact Grid Array
SG149726A1 (en) 2007-07-24 2009-02-27 Micron Technology Inc Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
CN103493799A (zh) * 2007-07-25 2014-01-08 低温药理有限公司 改进的器官保护、维护和康复
SG150396A1 (en) * 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
KR100905779B1 (ko) 2007-08-20 2009-07-02 주식회사 하이닉스반도체 반도체 패키지
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
CN101459088B (zh) * 2007-12-13 2010-06-09 中芯国际集成电路制造(上海)有限公司 再分布金属层及再分布凸点的制作方法
CN101459087B (zh) * 2007-12-13 2011-03-23 中芯国际集成电路制造(上海)有限公司 再分布金属线及再分布凸点的制作方法
US7767496B2 (en) 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US8343809B2 (en) 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US20090294961A1 (en) * 2008-06-02 2009-12-03 Infineon Technologies Ag Semiconductor device
US8076786B2 (en) * 2008-07-11 2011-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for packaging a semiconductor package
US7982311B2 (en) * 2008-12-19 2011-07-19 Intel Corporation Solder limiting layer for integrated circuit die copper bumps
US8426256B2 (en) * 2009-03-20 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming stacked-die packages
CN101882589B (zh) * 2009-05-06 2013-01-16 台湾积体电路制造股份有限公司 集成电路结构的形成方法
KR101055491B1 (ko) * 2009-05-26 2011-08-08 주식회사 네패스 반도체 패키지 및 그 제조 방법
KR101018172B1 (ko) 2009-08-18 2011-02-28 삼성전기주식회사 웨이퍼 레벨 디바이스 패키지의 제조 방법
JP2010016397A (ja) * 2009-09-09 2010-01-21 Seiko Epson Corp 半導体装置、回路基板及び電子機器
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US8362612B1 (en) * 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
KR101680082B1 (ko) 2010-05-07 2016-11-29 삼성전자 주식회사 웨이퍼 레벨 패키지 및 웨이퍼 레벨 패키지의 형성방법
US8198739B2 (en) 2010-08-13 2012-06-12 Endicott Interconnect Technologies, Inc. Semi-conductor chip with compressible contact structure and electronic package utilizing same
JP2012129452A (ja) * 2010-12-17 2012-07-05 Toshiba Corp 半導体装置、半導体パッケージおよび半導体装置の製造方法
US8912649B2 (en) 2011-08-17 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy flip chip bumps for reducing stress
US9368398B2 (en) 2012-01-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9607921B2 (en) 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US9589862B2 (en) 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US10015888B2 (en) 2013-02-15 2018-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect joint protective layer apparatus and method
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US9437564B2 (en) 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9082780B2 (en) 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
CN102623429A (zh) * 2012-04-11 2012-08-01 日月光半导体制造股份有限公司 封装载体结构
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
KR101514137B1 (ko) * 2013-08-06 2015-04-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
CN105789368B (zh) * 2014-12-22 2017-07-21 中国科学院微电子研究所 半导体器件
KR102333092B1 (ko) * 2015-07-15 2021-12-01 삼성전기주식회사 회로 기판 및 그 제조 방법
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US10787303B2 (en) 2016-05-29 2020-09-29 Cellulose Material Solutions, LLC Packaging insulation products and methods of making and using same
JP6562467B2 (ja) 2016-06-21 2019-08-21 サムスン エレクトロニクス カンパニー リミテッド ファン−アウト半導体パッケージ
KR101952863B1 (ko) * 2016-06-21 2019-02-28 삼성전기주식회사 팬-아웃 반도체 패키지
US11078007B2 (en) 2016-06-27 2021-08-03 Cellulose Material Solutions, LLC Thermoplastic packaging insulation products and methods of making and using same
CN112736052A (zh) * 2020-11-24 2021-04-30 上海艾为电子技术股份有限公司 一种封装结构及其制备方法、封装芯片
CN114038814A (zh) * 2021-11-18 2022-02-11 苏州通富超威半导体有限公司 封装结构及封装结构的形成方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287983A (en) * 1976-01-19 1977-07-22 Hitachi Ltd Production of semiconductor device
JPH053249A (ja) * 1991-06-25 1993-01-08 Sony Corp 半導体装置及びその製造方法
HUT73312A (en) * 1992-09-14 1996-07-29 Badehi Method and apparatus for producing integrated circuit devices, and integrated circuit device
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
JP3278533B2 (ja) * 1994-07-28 2002-04-30 三菱電機株式会社 樹脂封止型半導体装置の製造方法
US5904546A (en) * 1996-02-12 1999-05-18 Micron Technology, Inc. Method and apparatus for dicing semiconductor wafers
US5682065A (en) * 1996-03-12 1997-10-28 Micron Technology, Inc. Hermetic chip and method of manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10998248B2 (en) 2007-12-14 2021-05-04 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US10204866B2 (en) 2010-03-12 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation

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