JP3769418B2 - 半導体パッケージ及びその製造方法 - Google Patents
半導体パッケージ及びその製造方法 Download PDFInfo
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- JP3769418B2 JP3769418B2 JP18899199A JP18899199A JP3769418B2 JP 3769418 B2 JP3769418 B2 JP 3769418B2 JP 18899199 A JP18899199 A JP 18899199A JP 18899199 A JP18899199 A JP 18899199A JP 3769418 B2 JP3769418 B2 JP 3769418B2
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- layer
- chip
- semiconductor package
- metal wiring
- insulating layer
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Description
【発明の属する技術分野】
本発明は、半導体パッケージ及びその製造方法に関し、特にチップスケールパッケージ及びウェーハレベルでこれを製造する方法に関する。
【0002】
【従来の技術】
近年、電子産業は、機器を軽量化、小形化、高速化、多機能化、高性能化し、高い信頼性を有する製品を安価に製造することを求められている。このような製品設計の目標達成を可能とする重要技術の一つが、パッケージの組立技術である。チップスケールパッケージ(以下「チップスケールパッケージ」を「CSP」という。)またはチップサイズパッケージは、最近、開発および提案されている新たなパッケージの類型であり、典型的なプラスチックパッケージに比べて多くの長所を有する。チップスケールパッケージの一番大きな長所は、パッケージのサイズである。JEDEC(Joint Electron Device Engineering Council)、EIAJ(Electronic Industry Association of Japan)のような国際半導体協会の定義によると、チップスケールパッケージは、半導体チップの1.2倍以内のパッケージサイズを有する。
【0003】
しかしながら、CSPは、サイズの面において利点を有するが、まだ、既存のプラスチックパッケージに比べ種々の短所がある。その中の一つは、信頼性の確保が難しいということで、他の一つは、チップスケールパッケージの製造に追加投入される製造設備や所要資材が多く、製造コストが高く価格競争力が劣るということである。
【0004】
【発明が解決しようとする課題】
そこで、本発明の目的は、パッケージの信頼性を向上させることができるチップスケールパッケージ及びウェーハレベルでこれを製造する方法を提供することにある。
【0005】
【課題を解決するための手段】
本発明によると、CSPはウェーハ状態で製造される。CSPは、半導体チップ上にチップパッドを再配列するための金属配線層と、一つまたは二つの絶縁層と、CSPの端子として働き前記金属配線層により各々のチップパッドに接続されるソルダボールとを含む。本発明による第1実施例において、金属配線層は、半導体ウェーハの表面又はパッシベーション層の上に直接形成され、第2実施例においては、半導体ウェーハの表面に絶縁層が形成された後、絶縁層上に金属配線層が形成される。第1実施例及び第2実施例において、金属配線層上に他の絶縁層を形成し、また、界面保全性(interface integrity)を向上するため、チップパッドと金属配線層の間及びソルダボールと金属配線層の間に、付加的な金属障壁層を形成することができる。
【0006】
加えて、CSPの信頼性を向上するため、補強層、エッジ保護層及びチップ保護層が提供される。絶縁層の上部に形成された補強層は、CSPが回路基板に実装されて使用される場合、ソルダボールに加えられる衝撃を緩和し、ソルダボールの寿命を延長させる。エッジ保護層は、半導体ウェーハ上のチップ切断線に沿って半導体ウェーハの上面に形成され、チップ保護層は、半導体ウェーハの裏面に形成される。エッジ保護層及びチップ保護層は、外部圧力によるCSPの損傷を防ぐ。半導体ウェーハ上にCSPの構成要素を全部形成した後、半導体ウェーハが切断され、個別CSPを形成する。
【0007】
本発明によるCSPの製造方法は、広く利用可能な技術を使用し、よって、新たな技術や設備の開発は要求されない。さらに、本発明によるウェーハレベルでCSPを製造する方法は、従来のチップレベルCSPの製造方法に比べて生産性の点から有利である。
【0008】
【発明の実施の形態】
以下、図面を参照しつつ、本発明の二つの実施例をより詳しく説明する。
(第1実施例)
図2乃至図14は、本発明の第1実施例によるCSP及びその製造方法に関する。特に図14はCSPの部分断面図である。
【0009】
図1に示すように、図14のCSPを製造するためには、まず、複数の半導体集積回路チップ50ならびに半導体チップ50間のチップ切断線52を有する半導体ウェーハ40を準備する。図2は、半導体チップのチップパッド12及びパッシベーション層14を示す半導体ウェーハ40の一部横断面図である。チップパッド12は、半導体チップの回路素子(図示せず)と接続する複数のチップパッドの一つであり、外部との電気的接続のためのアクセスを提供する。図1における半導体ウェーハ40の作製は公知の技術であるため、その詳細な説明は省略する。
【0010】
図3を参照すると、チップパッド12及びパッシベーション層14を含む半導体ウェーハ40の全面に金属層16が形成され、これにより、金属層16とチップパッド12とが電気的に接続される。金属層16の厚さは、パッシベーション層14の下部にチップ回路パターンを構成する金属層(図示せず)より大きく、約1〜5μmであることが望ましい。金属層16は、銅、アルミニウム、ニッケル、銅合金、アルミニウム合金及びニッケル合金等の種々の材質で形成されるが、これらに限るものではない。
【0011】
半導体ウェーハ40の表面上に金属層16を形成した後、図4乃至図6に示すように、金属層16をパターニングして金属配線層17を形成する。まず、図4に示すように、金属層16上に所定のパターンを有するホトレジスト層18を形成する。ホトレジスト層18は、金属配線層17となる領域だけを覆う。その後、図5に示すように金属層16をエッチングし、図6に示すようにホトレジスト層18を除去すると、金属配線層17が形成される。金属配線層17のパターンは、チップパッド12をどのように再配列すべきかによって任意に形成することができる。
【0012】
金属配線層17を形成するための他の方法としては、導体ペースト(図示せず)をチップパッド12及びパッシベーション層14の上面に直接スクリーンプリントし、ペーストを硬化することにより金属配線層17を形成する方法がある。ペーストの好ましい例としては、金属粒子とバインダー樹脂の混合物が用いられる。
【0013】
図7は、金属配線層17を形成した後、半導体ウェーハ40の全面に絶縁層24を形成した状態を示す。絶縁層24は、図14におけるCSPの一部となり、そのため、例えば、低吸湿率、低誘電率及び低熱膨張係数を有するような望ましい特性を有しなければならない。このような特性を考慮すると、絶縁層24としては、ベンゾシクロブテン(BCB:Benzo Cyclo Butene)が好適である。絶縁層24としては、BCBだけでなく、例えば、ポリイミド、エポキシのような他のポリマー、ならびに窒化ケイ素、二酸化ケイ素、窒化ケイ素と二酸化ケイ素の化合物のような無機材料などが用いられる。ポリマー絶縁層は、従来のスピン−コーティング法により形成し、無機絶縁層は、従来の気相蒸着法により形成することができる。これら両方の方法において、絶縁層の厚さは2〜50μmであることが望ましい。
【0014】
図8を参照すると、絶縁層24を部分的に除去してバンプパッド22のための開口部を形成し、前記バンプパッド22は、開口部から露出する金属配線層17の一部である。バンプパッド22は、再配列されたチップパッド12と言うことができ、バンプパッド22の位置は、バンプパッド22を含んだCSPが実装される基板の形態による。
【0015】
開口部を形成した後、図9に示すように、絶縁層24及びバンプパッド22を覆うように金属障壁層26が形成される。障壁層26は、図14における金属配線層17とソルダボール32間の拡散を防ぐとともに、金属配線層17とソルダボール32間の接着を強化する。さらに、障壁層26は、電気メッキによりバンプパッド22上にバンプ32を形成する際、電気的供給媒体を提供する。障壁層26は、通常二つ又は三つの層を含み、例えば、チタニウム/銅、チタニウム/チタニウム−銅/銅、クロム/クロム−銅/銅、チタニウム−タングステン/銅、アルミニウム/ニッケル/銅、又はアルミニウム/ニッケル−バナジウム/銅の構造を含む。チタニウム/チタニウム−銅/銅またはクロム/クロム−銅/銅の構造において、中間層であるチタニウム−銅層またはクロム−銅層を形成するために、二つのターゲットをもって同時にスパッタリングする同時スパッタリング(co-sputtering)法を用いる。図3の金属層16を形成する前、チップパッド12と金属層16の間に金属障壁層26と同様の構造を有する接着層(図示せず)を形成することができる。障壁層26及び接着層の厚さは1μm以下であり、好ましくは、0.8〜1.0μmである。
【0016】
図10に示すように、絶縁層24の開口部及び開口部を取り囲む領域が露出するように、障壁層26の上部には他のホトレジスト層28が形成される。その後、ソルダバンプ30のための金属、好ましくはソルダ合金がメッキされて、図11に示すように、ホトレジスト層28で被覆されない領域にソルダバンプ30が形成される。メッキ法の代わりに、スクリーンプリント法、ボール配置(ball placement)法またはメタルジェット(metaljet)法により、バンプ30を形成することができる。ここで、スクリーンプリント法は、マスクを用いてソルダペーストを印刷する方法であり、ボール配置法は、直ちにボールの形態を有するソルダを載置する方法であり、メタルジェット法は、絶縁層の開口部に液状のソルダをスプレーする方法である。ソルダバンプ30を形成する前、数μm〜数十μmの厚さを有する銅層(図示せず)をバンプパッド22の障壁層26に形成することができる。この銅層は、ソルダバンプ30を溶融してソルダボール32を形成するリフロー工程の間、ソルダバンプ30と障壁層26間の拡散により発生する信頼性不良を防止するためのものである。
【0017】
ソルダバンプ30を形成した後、エッチングによりホトレジスト層28及び障壁層26が除去され、図12に示すように、ソルダバンプ30下の障壁金属部27だけが残る。それから、図13に示すように、従来のリフロー法により、ソルダバンプ30がソルダボール32の形態を取ることになる。本実施例において、ソルダボール32の高さは、350μm〜500μmである。
【0018】
さらに、図14に示すように、ソルダボール32を支持し、且つCSPが回路板(図示せず)上に実装される際にソルダボール32に加わるストレスを吸収するため、絶縁層24の上部に補強層34を形成することができる。また、補強層34は、耐久寿命を向上させる効果がある。従来のCSPにおいて、前記のようなストレスに起因する不良が時々起こる。補強層34を形成するため、低粘度を有する液状のポリマーを供給し硬化させることができる。低粘度の液状ポリマーは、表面張力によりポリマーをソルダボール32の側面に引き付けることが可能であり、ボール32の凹状支持部を形成することになる。補強層は、曲げ強さ(flexural strength)が高いほど、ソルダボール32からより多くのストレスを吸収することができるので、硬化した後のポリマーは、高い曲げ強さを有することが好ましい。補強層34は、ソルダボール32の最上部を被覆してはならない。また、補強層34は、ソルダボールの高さの1/4程度ソルダボール32の最上部より低い地点までソルダボール32と接触することが好ましい。
【0019】
終わりに、図2乃至図14で図示された段階を経た半導体ウェーハ40は、チップ切断線52に沿って切断され、図15で概略的に示す個別CSP90が製造される。
【0020】
(第2実施例)
実際に使用する間、CSPに加わる外部衝撃及び熱・機械的ストレスからCSPを保護するため、本発明の第2実施例は、二つの絶縁層及び付加的な保護層を含む。この第2実施例を図16乃至図24を参照して説明する。
図16を参照すると、チップパッド12及びパッシベーション層14を含む半導体ウェーハ40の上に、下部絶縁層60が形成される。半導体ウェーハ40の全面に絶縁層を形成した後、チップパッド12上の絶縁層をエッチングし、開口部を形成する。従来のエッチング法によりチップパッド12上の絶縁層を除去することができる。下部絶縁層60は、図22に示すCSPの一部となり、低吸湿率、低誘電率及び低熱膨張係数を有するような好ましい特徴を有しなければならない。下部絶縁層60としては、BCB、ポリイミド及びエポキシのようなポリマー、並びに窒化ケイ素、二酸化ケイ素、窒化ケイ素と二酸化ケイ素の化合物のような無機材料が用いられる。その中でBCBが好ましい。下部絶縁層60を形成する工程は、前述したように、絶縁層24を形成する工程と同様である。下部絶縁層60の厚さは2〜50μmであることが望ましい。
【0021】
下部絶縁層60を形成した後、図17に示すように、下部絶縁層60及びチップパッド12を覆うように、接着層62が形成される。接着層62は、図19の金属配線層66とチップパッド12間の接着を強化する。接着層62は、チタニウム/銅、チタニウム/チタニウム−銅/銅、クロム/クロム−銅/銅、チタニウム−タングステン/銅又はアルミニウム/ニッケル/銅のような、通常二つまたは三つの層を含む。接着層62の厚さは約0.5μmである。
【0022】
図18乃至図20を参照して、金属配線層66の形成を説明する。まず、金属配線層66が形成される部分を除き、接着層62を含む下部絶縁層60上に所定のパターンを有するホトレジスト層64を形成する。次に、蒸着法により、ホトレジスト層64を介して露出される接着層62上に金属配線層66を形成する。剥離法によりホトレジスト層64を除去し、エッチング法により接着層62を露出させる。金属配線層66は、銅、アルミニウム、ニッケル、銅合金、アルミニウム合金及びニッケル合金を含む種々の材料で形成されるが、これらに限定されるものではない。金属配線層66は、図3乃至図6を参照して説明した前述の方法と類似の方法で形成することもできる。
【0023】
図21に示すように、金属配線層66を形成した後、金属配線層66の上部にバンプ74が形成されるべき部分を残して上部絶縁層68を形成する。その後、障壁層72、ソルダボール74及び補強層76を形成し、図22に示すCSPを製造する。上部絶縁層68の形成から補強層76の形成に至る製造段階は、図7乃至図14を参照して説明した前述の段階と同様である。また、上部絶縁層68、障壁層72、ソルダボール74及び補強層76の特徴も、前述したものと同様である。
【0024】
本実施例は保護層、即ち、エッジ保護層80及びチップ保護層82をさらに含むことができる。図23は、チップ切断線52に沿って半導体ウェーハ40上に形成されたエッジ保護層80及び半導体ウェーハ40の裏面に形成されたチップ保護層82を示す。図23の半導体ウェーハ40を切断すると、図24のCSP100になる。エッジ保護層80及びチップ保護層82が形成されていない場合、ウェーハの切断及び後続のCSP100の取扱過程で、図25に示すようなエッジチッピング(edge chipping)という問題をもたらすことができる。
【0025】
エッジ保護層80は、ソルダボール74を形成する前、例えば、エポキシ樹脂のようなポリマーをドッティングするか、スクリーンプリントし、ポリマーを硬化することにより形成することができる。エッジ保護層80の幅はチップ切断線52より広いことが好ましく、これによりエッジ保護層80の一部は、図24に示すように、外周に沿ってCSP100上に残る。エッジ保護層80の高さはソルダボール74より低い。好ましくは、エッジ保護層80の高さは、ソルダボール74の高さの1/10より低い。
【0026】
チップ保護層82は、半導体ウェーハを作製した後、ポリイミド及びエポキシのようなポリマーを半導体ウェーハの裏面にスピンコーティングすることにより形成することができる。チップ保護層の厚さは2〜50μmであることが好ましい。
【0027】
【発明の効果】
本発明によるCSPは、従来のCSPとは異なり、多くの長所を有する。即ち、ソルダボールの信頼性を向上させ、エッジ保護層及びチップ保護層によりCSPを保護することができ、コスト低減を図ることができる。補強層は、CSPが回路基板に実装される際、ソルダボールに加えられるストレスを吸入し、ソルダボールの寿命を延長させ、そのため、CSPの寿命が延長される。エッジ保護層及びチップ保護層は、CSPが外部の圧力により損することを防止する。本発明によるCSPの製造方法は、既存の設備及び技術を使用し、そのため、新たな技術や設備を必要としない。さらに、本発明によるウェーハレベルCSPの製造は、半導体集積回路チップを切断した後にCSPを製造するチップレベルCSPの製造より生産性面において有利である。
【図面の簡単な説明】
【図1】本発明の第1実施例に用いられる半導体集積回路チップ及び切断線を含む半導体ウェーハの概略的な平面図である。
【図2】本発明の第1実施例による図1における半導体ウェーハの部分断面図である。
【図3】本発明の第1実施例において、半導体ウェーハの上面に金属層を形成した後の構造を示す。
【図4】本発明の第1実施例において、金属層上に所定のパターンを有するホトレジスト層を形成した後の構造を示す。
【図5】本発明の第1実施例において、金属配線層を形成するため、マスクとしてホトレジスト層を用いて金属層をエッチングした後の構造を示す。
【図6】本発明の第1実施例において、ホトレジスト層を除去した後の構造を示す。
【図7】本発明の第1実施例において、金属配線層を含んだ半導体ウェーハの全面に絶縁層を形成した後の構造を示す。
【図8】本発明の第1実施例において、金属バンプが金属配線層に接続される部分の導体層を露出するため、開口部を形成した後の構造を示す。
【図9】本発明の第1実施例において、半導体ウェーハの全面に障壁層を形成した後の構造を示す。
【図10】本発明の第1実施例において、絶縁層の開口部及び開口部を取り囲む絶縁層の一部が露出されるように、他のホトレジスト層を形成した後の構造を示す。
【図11】本発明の第1実施例において、ホトレジストで被覆されていない領域にバンプを形成した後の構造を示す。
【図12】本発明の第1実施例において、ホトレジスト層を除去した後の構造を示す。
【図13】本発明の第1実施例において、障壁層を除去した後の構造を示す。
【図14】絶縁層上に補強層を形成した後の構造を示し、本発明の第1実施例によるCSPの概略断面図である。
【図15】本発明によるCSPの底面図である。
【図16】本発明の第2実施例において、チップパッドを除いた半導体ウェーハの全面に下部絶縁層を形成した後の構造を示す。
【図17】本発明の第2実施例において、半導体ウェーハの全面に接着層を形成した後の構造を示す。
【図18】本発明の第2実施例において、接着層上に所定のパターンを有するホトレジスト層を形成した後の構造を示す。
【図19】本発明の第2実施例において、ホトレジスト層で被覆されない接着層上に金属配線層を形成した後の構造を示す。
【図20】本発明の第2実施例において、ホトレジスト層及びホトレジスト層下部の接着層を除去した後の構造を示す。
【図21】本発明の第2実施例において、ソルダボールが形成されるべき部分を除いた半導体ウェーハの全面に上部絶縁層を形成した後の構造を示す。
【図22】上部絶縁層上に補強層が形成された後の構造を示し、本発明の第2実施例によるCSPの断面図である。
【図23】本発明によるエッジ保護層及びチップ保護層を含む半導体ウェーハの一部を示す。
【図24】図23の半導体ウェーハから切断されたCSPの断面図を示す。
【図25】エッジ保護層及びチップ保護層が形成されていない場合、発生し得る損傷を有するCSPの断面図を示す。
【符号の説明】
12:チップパッド
14:パッシベーション層
17、66:金属配線層
24:絶縁層
27、63、72:金属障壁層
32、74:ボール
34、76:補強層
40:半導体ウェーハ
50:半導体チップ
60:下部絶縁層
70:ボールパッド
68:上部絶縁層
80:エッジ保護層
82:チップ保護層
Claims (10)
- 複数のチップパッド及びパッシベーション層を有する半導体集積回路チップと、
前記各々のチップパッドに電気的に接続される複数の突出した外部端子と、
前記外部端子の各々に前記チップパッドを接続する金属配線層と、
前記複数の外部端子間の空間を被覆し、前記外部端子を支持する補強層と、
前記半導体パッケージの上面のうち周縁部のみを覆うように形成されるエッジ保護層と、
を含むことを特徴とする半導体パッケージ。 - 前記金属配線層上に形成される上部絶縁層をさらに含み、
前記上部絶縁層は、前記外部端子と前記金属配線層とを接続するための複数の開口部を有することを特徴とする請求項1に記載の半導体パッケージ。 - 前記上部絶縁層は、ベンゾシクロブテン、ポリイミド及びエポキシ樹脂よりなる群から選ばれる高分子材料を含有することを特徴とする請求項2に記載の半導体パッケージ。
- 前記半導体チップのパッシベーション層と前記金属配線層の間に形成される下部絶縁層をさらに含み、
前記下部絶縁層は、前記チップパッドと前記金属配線層とを接続するための複数の開口部を有することを特徴とする請求項1に記載の半導体パッケージ。 - 前記半導体チップの裏面に形成されるチップ保護層をさらに含むことを特徴とする請求項1に記載の半導体パッケージ。
- 前記チップ保護層はポリマーを含有することを特徴とする請求項5に記載の半導体パッケージ。
- 前記チップ保護層の厚さは2μm以上50μm以下であることを特徴とする請求項5に記載の半導体パッケージ。
- 前記エッジ保護層はポリマーで形成されることを特徴とする請求項1に記載の半導体パッケージ。
- 前記補強層は、前記複数の外部端子の先端を連結する表面より下側に位置することを特徴とする請求項1に記載の半導体パッケージ。
- 前記表面から前記補強層と前記外部端子が接触している地点までの垂直距離は、87.5μm以上125μm以下であることを特徴とする請求項9に記載の半導体パッケージ。
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1998
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- 1998-12-28 US US09/222,250 patent/US6187615B1/en not_active Expired - Lifetime
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TW411536B (en) | 2000-11-11 |
KR20000015326A (ko) | 2000-03-15 |
KR100269540B1 (ko) | 2000-10-16 |
US6187615B1 (en) | 2001-02-13 |
CN1246731A (zh) | 2000-03-08 |
JP2006140508A (ja) | 2006-06-01 |
JP2000077570A (ja) | 2000-03-14 |
JP4512027B2 (ja) | 2010-07-28 |
CN100355063C (zh) | 2007-12-12 |
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