CN101924042B - 裸片堆叠密封结构的形成方法 - Google Patents
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Abstract
本发明提供一种裸片堆叠结构的形成方法。该方法包括如下步骤:多个裸片分别接合至晶片的第一表面上的多个半导体芯片之一。在多个裸片及晶片的第一表面上形成有封装结构。封装结构覆盖该晶片的中心部分的第一表面,并露出该晶片的边缘部分。保护材料则形成于晶片的第一表面的边缘部分上。本发明的形成方法使晶片中较脆弱的层状结构如低介电常数层较不会产生碎裂、剥离、或分层等现象,可大幅提升封装工艺的合格率。
Description
技术领域
本发明涉及集成电路的工艺,尤其涉及裸片堆叠密封结构的形成方法。
背景技术
集成电路已广泛应用于多种电子元件如存储芯片。目前需要缩小集成电路的尺寸,以及增加个别半导体组件的密度,以提升电子元件的功能。增加半导体组件的功能及密度的方法包括三维集成电路(3D-IC)。一般的3D-IC可允许集成电路除了具有不同的功能如处理器、逻辑电路、特用集成电路(ASIC)、及存储器外,还可降低制造成本、增加结构的机械稳定性、降低电路的RC延迟、及降低元件的电力消耗。
一般来说,3D-IC包含多个半导体裸片彼此堆叠。在一般的3D-IC工艺中,多个切割后且具有品质保证的裸片将接合至已形成于晶片上的对应裸片。上述切割后的裸片以及对应的裸片之间经由一或多个硅穿孔(TSV)电性连接。经上述工艺形成的裸片堆叠可具有多种功能或增加单一功能的密度。当物理或电性连接堆叠中的裸片后,将塑料(molding compound)置于多个裸片及晶片表面上以封装上述堆叠结构。然而公知技术无法以塑料完全覆盖晶片上表面的所有区域。如此一来,在后续晶片的处理工艺或裸片切割的过程中,晶片未被覆盖的部分易产生碎裂。上述碎裂方向一般沿着未被塑料机械支撑的部分,如晶片边缘。
综上所述,目前急需一种改良的方法以强化裸片堆叠结构,避免晶片边缘在裸片切割工艺或晶片处理工艺的过程中产生碎裂。
发明内容
为克服上述现有技术的缺陷,本发明提供一种裸片堆叠密封结构的形成方法,包括提供晶片,晶片具有第一表面及第二表面,且晶片的第一表面上包括多个半导体芯片;提供多个裸片,且每一裸片接合至第一表面上的半导体芯片之一;形成封装结构于裸片及晶片的第一表面上,其中封装结构包覆晶片的中心部分的第一表面,并露出晶片的边缘部分;以及移除晶片的边缘部分,其中晶片的保留部分的边缘与封装结构的边缘之间的距离小于0.5mm。
本发明也提供一种裸片堆叠密封结构的形成方法,且裸片堆叠结构位于晶片上,包括提供晶片,晶片具有第一表面及第二表面,且晶片的第一表面上包括多个半导体芯片;将多个裸片分别接合至第一表面上的半导体芯片之一;形成封装结构于裸片及晶片的中心部分的第一表面上,并露出晶片的第一表面的边缘部分;以及以保护材料覆盖晶片的第一表面的边缘部分。
本发明还提供一种裸片堆叠密封结构的形成方法,裸片堆叠结构为半导体组件的一部分,包括提供晶片,晶片具有第一表面及第二表面,且该晶片的第一表面上包括半导体芯片;将裸片分别接合至第一表面上的半导体芯片之一,其中裸片之一以硅穿孔电性连接至半导体芯片之一;形成封装结构于裸片及晶片的中心部分的第一表面上以形成密封结构,并露出晶片的第一表面的边缘部分;形成保护材料覆盖晶片的第一表面的边缘部分;以及将密封结构切割为独立的半导体组件。
本发明的形成方法使晶片中较脆弱的层状结构如低介电常数层较不会产生碎裂、剥离、或分层等现象,可大幅提升封装工艺的合格率。
附图说明
图1A是本发明一实施例中,晶片粘合至载体的剖视图;
图1B是本发明一实施例中,多个半导体芯片形成于晶片表面的俯视图;
图2A是本发明一实施例中,将图1A的晶片薄化后的剖视图;
图2B是本发明一实施例中,图2A的晶片及载体的部分放大图;
图3A是本发明一实施例中,将多个裸片接合至图2A的晶片的第一表面后的剖视图;
图3B是本发明一实施例中,图3A的裸片、晶片、及载体的部分放大图;
图4是本发明一实施例中,将封装结构形成于图3A中多个裸片与晶片的第一表面的中心部分后的剖视图;
图5是本发明一实施例中,将图4中晶片的边缘部分移除后的封装结构及晶片的放大图;
图6是本发明一实施例中,将图5的封装结构翻转,并将封装结构的上表面黏合至切割带后的封装结构的剖视图;
图7是本发明一实施例中,在密封结构上进行切割工艺的晶片剖视图;
图8A是本发明一实施例中,将保护材料施加于晶片边缘部分上的晶片剖视图;
图8B-I、图8B-II、及图8B-III是本发明另一实施例中,将保护材料施加于晶片的边缘部分上的剖视图及俯视图;
图9是本发明一实施例中,图8A及图8B中的封装结构与保护材料的放大图;
图10是本发明一实施例中,将封装结构翻转,并将封装结构的上表面与保护材料黏合至切割带后的封装结构的剖视图;以及
图11是本发明一实施例中,在密封结构与保护材料上进行切割工艺的晶片剖视图。
其中,附图标记说明如下:
D1~封装结构的边缘与晶片的保留部分的边缘之间的距离;D2~保护材料上表面与封装结构上表面之间的距离;D3~保护材料侧壁与晶片侧壁之间的距离;T1~保护材料厚度;T2~封装结构厚度;100~半导体芯片;101~载体;103~晶片;104~内连线层;105~焊料;107~硅穿孔;108~导线层;109~绝缘层;111~粘合剂;113~裸片;115~封装结构;117~晶片的边缘部分;119~晶片的中心部分;121~封装结构的边缘;123~晶片的保留部分的边缘;125~切割带;142~保护材料侧壁;144~晶片侧壁;168~密封结构;205~模具;207~空隙;1001、1003~晶片的第一表面;1002~晶片的第二表面;2001~保护材料上表面;2003~封装结构上表面。
具体实施方式
下述说明中,将以多个实施例说明本发明的工艺及用途。必需理解的是,下列实施例可实施于多种特定背景,且仅用以说明而非限制本发明。
图1-图7是第一实施例,用以形成裸片堆叠的方法。图1A是晶片103的剖视图,其包含多个半导体芯片粘合至载体101的上表面。晶片103的第一侧具有第一表面1001,其第二侧具有第二表面1002。“晶片”在此可为半导体基板,其上形成有多种层状结构或元件。在某些实施例中,晶片103包含包含硅或半导体化合物如砷化镓、磷化铟、硅锗合金、或碳化硅。上述层状结构包含介电层、掺杂层、及/或多晶硅层。上述元件包含晶体管、电阻、及/或电容,所述多个元件可采用内连线结构连接至其它有源电路。一般来说,载体101在后续工艺步骤中,可提供暂时的机械及结构支撑力。在一实施例中,载体101的形状及大小与晶片103类似。如此一来,可采用现有设备于载体101上进行工艺。在另一实施例中,载体101的形状及/或大小不同于载体103。在某些实施例中,载体101的主要材料为包含玻璃、硅、氧化硅、或其它材料。
在图1B中,晶片103的第二表面1002包含多个半导体芯片100形成于晶片103上。晶片103的第一表面1001及第二表面1002也为半导体芯片100的第一表面及第二表面。在一实施例中,以黏合剂将晶片103粘合于载体101上。黏合剂可为任何合适材料如紫外线硬化胶或热硬化胶。在某些实施例中,半导体芯片100一般包含多种层状结构(未图示)与元件结构(未图示)形成于晶片103的第二表面1002上。晶片103的第二表面1002可粘合至载体101的上表面。上述结构将露出位于第二表面1002相反侧的第一表面1001。
图2A是将图1A的晶片103薄化后,晶片103与载体101的剖视图。上述薄化工艺可自第一表面1001移除部分晶片103,并定义新的第一表面1003。在某些实施例中,薄化工艺可为机械研磨制、化学机械研磨工艺(CMP)、蚀刻工艺、及/或上述的组合。在上述薄化工艺中,载体101可提供暂时的机械及结构支撑力,以避免晶片103碎裂。在一实施例中,晶片103将薄化至预定厚度如25μm至250μm之间。
图2B是图2A的晶片103及载体101的放大图。在一实施例中,内连线层104形成于晶片103的第二表面1002上。内连线层104包含一或多层的导线层108与一或多层的绝缘层109。内连线层104可电性连结至其下的元件结构,或电性连结不同的元件结构,其中所述多个元件结构形成于晶片103的第二表面1002上。上述结构可采用粘合剂111将晶片103粘合至载体101上。硅穿孔(TSV)107形成于晶片103中并穿过晶片103及绝缘层109。在另一实施例中,硅穿孔107穿过晶片103但未穿过绝缘层109。在某些实施例中,薄化工艺将露出硅穿孔107。接着进行湿式或干式蚀刻工艺蚀刻晶片103以露出部分硅穿孔107,并定义新的第一表面1003。如此一来,硅穿孔107将凸出晶片103的新的第一表面1003。
接着如图3A所示,将多个裸片113接合至晶片103的半导体芯片100的新的第一表面1003上。裸片113及晶片103的半导体芯片100组成裸片堆叠。每一裸片113在接合前已测试过,只有品质保证的裸片(known good die)可接合至晶片103上的半导体芯片100。在一实施例中,每一裸片113接合至晶片103上的一半导体芯片100。此外在某些实施例中,其它裸片113置于上述已接合的裸片113的顶部。在某些实施例中,接合至晶片103的裸片113,与对应的晶片103上的半导体芯片100不需具有相同的电路设计及/或尺寸。形成内连线的接合方法包含一般常见方法如氧化物-氧化物接合、氧化物-硅接合、铜-铜接合、焊料接合、或其它类似方法。
图3B是图3A的裸片113、晶片103、及载体101的部分放大图。裸片113的位置实质上对准晶片103的硅穿孔107,两者之间填有焊料105。每一裸片113经由一或多个硅穿孔107电性连接至晶片103上的半导体芯片100之一。裸片113与晶片103上的半导体芯片100组成的裸片堆叠可提供多种功能或增加单一功能的密度。
如图4所示,封装结构(encapsulation structure)115形成于裸片113及晶片103的中心部分119的第一表面1003上,以形成密封结构(package structure)168。封装结构115也覆盖晶片103的中心部分119的半导体芯片100。晶片103未被封装结构115覆盖的部分将露出,如晶片的边缘部分117。在某些实施例中,封装结构115塑料,包含环氧树脂、硅基高分子、聚亚酰胺、聚苯并恶唑(PBO)、或其它常见材料。封装结构115较佳覆盖所有的裸片113,并流动至晶片103的第一表面1003与裸片113之间的沟槽。封装结构115的热膨胀系数(CTE)较佳与裸片113及晶片103的热膨胀系数相同。
接着移除晶片103未被封装材料115覆盖的边缘部分117。图5是图4的晶片103的边缘部分117被移除后,封装结构115与晶片103保留部分的部分放大图。上述移除方法包含一般常见方法如光刻及蚀刻工艺、或以激光切割工艺或机械切割工艺直接切割晶片的边缘部分117。经上述切割工艺后,晶片103的保留部分包含晶片103被封装结构115覆盖的中心部分119,以及晶片103未被封装结构115覆盖的边缘部分117的一部分。封装结构115的边缘121将定义第一侧壁。晶片103的保留部分的边缘123将定义第二侧壁。封装结构的边缘121与晶片的保留部分的边缘123之间的距离D1较佳小于0.5mm。换句话说,未被封装材料115覆盖的边缘区域117在切割工艺后保留的长度小于0.5mm。
在某些实施例中,晶片103未被封装材料115覆盖的边缘区域117将完全被移除。如此一来,边缘121的第一侧壁实质上对准边缘123的第二侧壁。此外,移除晶片103的边缘部分117,在晶片处理与裸片切割时可降低晶片边缘碎裂或破损的问题。此外,上述方法也可减少较脆弱的层状结构如低介电常数层产生碎裂、剥离、或分层等现象。
如图6所示,接着翻转封装结构115,并将封装结构115的上表面粘合至切割带125。接着将载体101自晶片103的保留部分的第二表面1002移除。上述移除载体101的方法包含激光剥除、化学溶解、升温离型、或任何本领域普通技术人员所熟知的合适步骤。
如图7所示,接着对密封结构168进行切割工艺。密封结构168包含晶片103的保留部分、裸片113、及封装结构115。密封结构168中的裸片113的堆叠结构与半导体芯片100将被切割为独立的半导体组件。
图8-图11是本发明另一实施例。在进行图8-图11的工艺前已先进行前述图1-图4的步骤,且图8-图11将沿用相同标记标示类似单元。
如图8A、图8B-I、图8B-II、及图8B-III所示,保护材料201施加至密封结构168。如图8A所示,在一实施例中,以高粘度喷胶形成保护材料210于晶片103的边缘部分117上。如图8B-I所示,在另一实施例中,先将晶片103置于模具205中。模具205具有容纳部分以放置晶片103,且该容纳部分的直径实质上等于或略大于晶片103的直径。接着如图8B-II所示,将保护材料201如胶体填入晶片103、模具205、及封装结构115之间的空隙207,再移除位于封装结构115的上表面上的胶体。接着如图8B-III所示,以刮板使空隙207中的胶体与封装结构115的上表面等高。在一实施例中,保护材料201包含聚亚酰胺、聚苯并恶唑(PBO)、耐热高分子如苯环丁烯(BCB)、SILKTM(购自Dow Chemical)、或其它类似物。在某些实施例中,保护材料201一般应用于半导体封装的底部填充剂。在另一实施例中,保护材料201包含塑料如环氧树脂、硅基高分子、或其它任何合适材料。
图9为图8A及图8B的详细结构,包含形成于晶片103的边缘部分117的第一表面1003上的保护材料201。在一实施例中,保护材料201的厚度T1与封装结构115的厚度T2实质上相同。保护材料201的上表面2001与封装结构115的上表面2003实质上等高。在某些实施例中,保护材料201的厚度T1小于封装结构115的厚度T2,但保护材料201的上表面2001与封装结构115的上表面2003之间的距离D2小于150μm。在另一实施例中,保护材料201的侧壁142实质上对准晶片103的侧壁144。在某些实施例中,护材料201的侧壁与晶片103的侧壁144之间的距离D3小于0.5mm。换句话说,未被保护材料201覆盖的晶片边缘区域117其长度小于0.5mm。
如图10所示,接着翻转封装结构115,并将封装结构115的上表面2003及保护材料201的上表面2001粘合至切割带125。接着将载体101自晶片103的第二表面1002移除。上述移除载体101的方法包含激光剥除、化学溶解、升温离型、或任何本领域普通技术人员所熟知的合适步骤。
如图11所示,接着对密封结构168进行切割工艺。密封结构168包含晶片103的保留部分、裸片113、封装结构115、及保护材料201。密封结构168中的裸片113的堆叠结构与半导体芯片100将被切割为独立的半导体组件。在晶片处理与裸片切割工艺中,保护层201可提供晶片103的边缘部分117较佳的支撑力。如此一来,晶片中较脆弱的层状结构如低介电常数层较不会产生碎裂、剥离、或分层等现象。上述方法将可大幅提升封装工艺的合格率。
虽然本发明已以数个优选实施例揭示如上,然而其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视随附的权利要求所界定的范围为准。
Claims (22)
1.一种裸片堆叠密封结构的形成方法,包括:
提供一晶片,该晶片具有一第一表面及一第二表面,且该晶片的第一表面上包括多个半导体芯片;
提供多个裸片,且每一裸片都分别接合至该第一表面上的所述多个半导体芯片中对应的一个;
形成一封装结构于所述多个裸片及该晶片的第一表面上,其中该封装结构包覆该晶片的中心部分的第一表面,并露出该晶片的边缘部分;以及
移除该晶片的边缘部分,其中该晶片的保留部分的边缘与该封装结构的边缘之间的距离小于0.5mm。
2.如权利要求1所述的裸片堆叠密封结构的形成方法,还包括:
黏合该晶片的第二表面至一载体;以及
薄化该晶片。
3.如权利要求1所述的裸片堆叠密封结构的形成方法,其中移除该晶片的边缘部分的步骤包括:
完全移除该晶片的边缘部分,使该封装结构的边缘对准该晶片的保留部分的边缘。
4.如权利要求1所述的裸片堆叠密封结构的形成方法,其中移除该晶片的边缘部分的步骤包括光刻工艺及蚀刻、激光切割工艺、或机械切割工艺。
5.如权利要求1所述的裸片堆叠密封结构的形成方法,其中所述多个裸片之一以硅穿孔电性连接至所述多个半导体芯片之一。
6.一种裸片堆叠密封结构的形成方法,且裸片堆叠结构位于一晶片上,包括:
提供该晶片,该晶片具有一第一表面及一第二表面,且该晶片的第一表面上包括多个半导体芯片;
将多个裸片分别接合至该第一表面上的所述多个半导体芯片之一;
形成一封装结构于所述多个裸片及该晶片的中心部分的第一表面上,并露出该晶片的第一表面的边缘部分;以及
以一保护材料覆盖该晶片的第一表面的边缘部分。
7.如权利要求6所述的裸片堆叠密封结构的形成方法,其中该保护材料的侧壁对准该晶片的侧壁。
8.如权利要求6所述的裸片堆叠密封结构的形成方法,其中该保护材料的侧壁与该晶片的侧壁之间的距离小于0.5mm。
9.如权利要求6所述的裸片堆叠密封结构的形成方法,其中该保护材料包括耐热高分子、底部填充剂、或硅基高分子。
10.如权利要求9所述的裸片堆叠密封结构的形成方法,其中该保护材料包括聚亚酰胺、聚苯并恶唑、或环氧树脂。
11.如权利要求6所述的裸片堆叠密封结构的形成方法,其中该封装结构与该保护材料的厚度相同。
12.如权利要求6所述的裸片堆叠密封结构的形成方法,其中该封装结构的上表面与该保护材料的上表面之间的距离小于150μm。
13.如权利要求6所述的裸片堆叠密封结构的形成方法,还包括:
黏合该晶片的第二表面至一载体;以及
薄化该晶片。
14.如权利要求13所述的裸片堆叠密封结构的形成方法,其中薄化该晶片的步骤露出至少一个所述多个半导体芯片的第一表面上之一硅穿孔。
15.如权利要求6所述的裸片堆叠密封结构的形成方法,其中所述多个裸片之一以硅穿孔电性连接至所述多个半导体芯片之一。
16.一种裸片堆叠密封结构的形成方法,裸片堆叠结构为半导体组件的一部分,包括:
提供一晶片,该晶片具有一第一表面及一第二表面,且该晶片的第一表面上包括多个半导体芯片;
将多个裸片分别接合至该第一表面上的所述多个半导体芯片之一,其中所述多个裸片之一以硅穿孔电性连接至所述多个半导体芯片之一;
形成一封装结构于所述多个裸片及该晶片的中心部分的第一表面上以形成一密封结构,并露出该晶片的第一表面的边缘部分;
形成一保护材料覆盖该晶片的第一表面的边缘部分;以及
将该密封结构切割为独立的半导体组件。
17.如权利要求16所述的裸片堆叠密封结构的形成方法,其中该保护材料的侧壁对准该晶片的侧壁。
18.如权利要求16所述的裸片堆叠密封结构的形成方法,其中该保护材料的侧壁与该晶片的侧壁之间的距离小于0.5mm。
19.如权利要求16所述的裸片堆叠密封结构的形成方法,其中该封装结构的上表面与该保护材料的上表面之间的距离小于150μm。
20.如权利要求16所述的裸片堆叠密封结构的形成方法,其中该保护材料包括耐热高分子、底部填充剂、或硅基高分子。
21.如权利要求20所述的裸片堆叠密封结构的形成方法,其中该保护材料包括聚亚酰胺、聚苯并恶唑、或环氧树脂。
22.如权利要求16所述的裸片堆叠密封结构的形成方法,其中形成该保护材料的步骤包括:
将该晶片置于一模具中,该模具具有一容纳部分以放置该晶片,且该容纳部分的直径大于或等于该晶片的直径;以及
将该保护材料填入该晶片、该模具、及该封装结构之间的空隙。
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