Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
  • H01L25/0657—Stacked arrangements of devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F17/00—Fixed inductances of the signal type
  • H01F17/0006—Printed inductances
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F38/00—Adaptations of transformers or inductances for specific applications or functions
  • H01F38/14—Inductive couplings
  • H01F2038/143—Inductive couplings for signals
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/321—Disposition
  • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
  • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
  • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/0239—Signal transmission by AC coupling
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making

Definitions

• the present invention relates to an electronic circuit capable of suitably performing communication between substrates such as an IC (Integrated Circuit) bare chip and a PCB (printed substrate).
• substrates such as an IC (Integrated Circuit) bare chip and a PCB (printed substrate).
• the first method is a system called system-on-chip (SoC) in which the entire system is mounted on one bare chip.
• SoC system-on-chip
• SiP system-in-package
• the first method of interconnection in SiP is a method using wire bonding as in the past.
• the number of connections between chips is less than or equal to that of a conventional package, and a problem occurs in the communication bandwidth.
• three-dimensional mounting is indispensable.In the wire bonding method, it is necessary to reduce the chips stacked on top of each other. It is difficult to form a bus because it is mainly used.
• a second method of interconnection in the SiP is a method of three-dimensionally mounting chips and connecting them with micro bumps. This method is low in cost up to two-chip mounting, but when mounting three or more chips, the chip itself or a build-up board called a through hole is It is necessary to physically manufacture a penetrating communication path, which requires dedicated process technology and high processing accuracy, and increases costs.
• a third method of interconnection in the SiP is a method in which chips are three-dimensionally mounted and the chips are electrically connected by capacitive coupling.
• this method high-speed communication is possible at low cost with face-to-face mounting of up to two chips, but with three or more chips, signal transmission efficiency deteriorates rapidly and power consumption increases.
• Patent Document 1 JP-A-11 68033
• the electric field generated by the antenna causes a large number of substances having different dielectric constants (such as a biased silicon substrate). , Doped silicon, oxide film, nitride film, etc.), reflection occurs at the interface, and transmission efficiency deteriorates.
• the present invention provides an electronic circuit that can efficiently transmit signals even when three or more substrates are three-dimensionally mounted and signals are transmitted across the substrates.
• This substrate includes IC bare chips and PCBs.
• An electronic circuit according to the present invention includes a first substrate having a first coil formed by wiring on the substrate, and an inductive connection with the first coil formed at a position corresponding to the first coil by wiring on the substrate. And a second substrate having a second coil to be combined.
• the first substrate further includes a transmission circuit that outputs a signal to the first coil when digital data for transmission changes, so that power consumption can be reduced.
• the second substrate further includes a receiving circuit that connects both ends of the second coil to a predetermined voltage source via a resistor, so that a center voltage of a voltage amplitude generated at both ends of the receiving coil when a signal is received. Can be an optimal voltage value for signal amplification.
• the first coil is inductively coupled to the second coils of the plurality of second substrates, so that a power bus can be formed again on three or more substrates.
• the second substrate further includes a receiving circuit that receives a signal only for a predetermined period in a periodic manner, so that the SN ratio can be increased.
• signals can be transmitted efficiently even when three or more substrates are three-dimensionally mounted and signals are transmitted across the substrates.
• FIG. 1 is a diagram showing a configuration of an electronic circuit according to an embodiment of the present invention.
• FIG. 2 is a diagram showing a specific configuration of a transmission circuit and a reception circuit according to the present embodiment.
• FIG. 3 is a diagram showing waveforms for explaining the operation of the present embodiment.
• FIG. 4 is a diagram showing a configuration of an electronic circuit according to another embodiment of the present invention.
• FIG. 5 is a diagram showing a configuration of an electronic circuit according to still another embodiment of the present invention.
• FIG. 6 is a diagram showing a specific configuration of a transmission circuit according to another embodiment of the present invention.
• Rxclk receive clock
• FIG. 1 is a diagram showing a configuration of an electronic circuit according to one embodiment of the present invention.
• the electronic circuit of the present embodiment includes a first LSI chip lla, a second LSI chip llb, and a third LSI chip 11c.
• This is an example in which LSI chips are stacked in three layers to form noise that spans three chips.
• the first and third LSI chips l la, l ib and 11 c are stacked vertically, and the chips are fixed to each other with an adhesive.
• first and third transmission coils 13a, 13b, and 13c used for transmission are formed by wiring, respectively, and the first and third transmission coils 13a, 13b, and 13c used for reception are respectively provided.
• the third receiving coils 15a, 15b, 15c are formed by wiring.
• the three pairs of transmitting and receiving coils 13 and 15 are arranged on the first and third LSI chips 1 la, 1 lb, and 11 c so that the centers of the openings of the coils 13 and 15 coincide with each other. Thereby, the three pairs of transmitting and receiving coils 13 and 15 form inductive coupling, and communication is possible.
• the first to third transmission coils 13a, 13b, 13c The first and third transmitting circuits 12a, 12b, and 12c are connected to the first and third receiving coils 15a, 15b, and 15c, respectively, and the first and third receiving circuits 14a, 14b, and 14c are connected to the first and third receiving coils 15a, 15b, and 15c, respectively. .
• the transmission and reception coils 13 and 15 are mounted as coils of one or more turns in three dimensions within the area allowed for communication, using multilayer wiring of process technology.
• the transmitting and receiving coils 13 and 15 have an optimal shape for communication, and it is necessary to have an optimal number of turns, an aperture, and a line width. Generally, the transmission coil 13 is smaller than the power reception coil 15 / J.
• FIG. 2 is a diagram illustrating a specific configuration of the transmission circuit and the reception circuit according to the present embodiment.
• the transmission circuit 12 of the present embodiment includes a storage element FF, a delay buffer 121, a first transmission buffer INV2, and a second transmission buffer INV3.
• L1 is the transmission coil 13.
• the transmission circuit 12 takes as input a transmission clock (synchronization signal) Txclk and transmission data Txdata synchronized with this.
• the input transmission data Txdata is held in the storage element FF and is input to the first and second transmission buffers INV2 and INV3.
• a delay buffer 121 which is a delay element, is provided before the first transmission buffer INV2, and is configured so that there is a difference between input times to the first transmission buffer INV2 and the second transmission buffer INV3.
• Outputs of the first transmission buffer INV2 and the second transmission buffer INV3 are respectively connected to both ends of the transmission coil L1.
• the receiving circuit 14 includes transistors T1 and T10, resistors R1 and R2, NAND circuits NAND1 and NAND2, and a receiving buffer INVl, and constitutes a differential amplifier with a latch as a whole.
• L2 is the receiving coil 15.
• the external power also takes the receive clock (synchronous signal) Rxclk and outputs the receive data Rxdata.
• Transistors T2 and T3 form a differential pair of a differential amplifier, and receive a signal from receive coil L2. Both ends of the receiving coil L2 connected to the transistors # 2 and # 3 are connected to the bias voltage Vbias through the resistors R1 and R2.
• the center voltage of the voltage amplitude generated across the receiving coil L2 at the time of signal reception can be set to the optimum voltage value Vbias for signal amplification.
• the source terminals of transistors T2 and ⁇ 3 are Connected to transistor Tl.
• the source terminal of the transistor T1 is grounded, and the reception clock Rxclk is input to the gate terminal.
• the transistors # 5 and # 8 and the transistors # 6 and # 9 form inverters, respectively, and the two inverters are connected in a loop.
• the wiring connecting the inverters is input to the NAND circuits NAND1 and NAND2, and the NAND circuits NAND1 and NAND2 form a latch.
• the value of the data received by the differential amplifier changes in synchronization with the receive clock Rxclk input to the transistor T1, and the received signal is converted to digital data only when the value changes by the NAND circuits NAND1 and NAND2. And keep the value as long as the input value does not change.
• Transistors T7 and T10 are connected to precharge the differential amplifier and hold the value of the latch while the receive clock Rxclk is L (low).
• Transistor T4 is connected in order to prevent the value of receive data Rxdata from being inverted even though there is no change in the receive signal from receive coil L2 due to the noise generated by transistors T7 and T10. .
• FIG. 3 is a diagram showing waveforms for explaining the operation of the present embodiment.
• the data transmission from the third transmitting circuit 12c on the third LSI chip 11c shown in FIG. 1 to the first and second receiving circuits 14a and 14b on the first and second LSI chips l la and 1 lb existing thereon is performed.
• the operation when the operation is performed will be described.
• an operation when data transmission of "...: LLHHLL"-" is performed as transmission data Txdata will be described.
• the third transmission circuit 12c on the third LSI chip 11c inputs a transmission clock Txclk and transmission data Txdata synchronized with the transmission clock Txclk when transmitting a value.
• the outputs of the first and second transmission buffers INV2 and INV3 are both in a steady state holding H (high).
• the first and second receiving circuits 14a and 14b on the first and second LSI chips lib and 11c are in a state where L is output as received data Rxdata when the L is continuously input. Has become.
• the transmission data Txdata changes to the L force H at the time of the point A.
• This signal is taken into the storage element FF at point B, and is immediately input to the second transmission buffer INV3.
• the output of the second transmission buffer INV3 becomes L.
• the output of the first transmission buffer INV2 remains H, and current flows from the first transmission buffer INV2 to the second transmission buffer INV3.
• the second transmission buffer INV3 Becomes H, the outputs of the first transmission buffer INV2 and the second transmission buffer INV3 become equipotential, and the current stops flowing.
• the driving force of the first and second transmission buffers INV2 and INV3 is set so that the current waveform becomes a triangular wave as shown at point “Transmission coil current” B.
• the receiving coil L2 disposed on the first and second LSI chips 11a and 11b receives the "first LSI chip receiving coil voltage", " The voltage shown in "2nd LSI chip receiving coil voltage” is generated.
• the center voltage of this voltage swing is Vbias. Since the first LSI chip 1 la is farther from the third LSI chip 1 lc than the second LSI chip 1 lb, the generated voltage becomes lower.
• These voltage changes are amplified by a differential amplifier with a latch, and the values are held by the latch, so that the digital data shown in the first and second LSI chips Rxdataj; is used.
• the transmission data Txdata on the third LSI chip 1lc holds H at the point B and changes! /, Na! / ⁇ .
• the input to the transmitting coil L1 at the point C does not change
• the voltage of the receiving coil L2 on the first and second LSI chips 11a and lib does not change
• the output data Rxdata is held.
• the transmission data Txdata on the third LSI chip 1lc transitions from H to L as at point C, it is fetched to the storage element FF at point D, and the input to the second transmission buffer INV3 is immediately high. From L to H, and its output changes from L to H. At this time, in the output of the first transmission buffer INV2, the change of the L level to H is delayed by the delay buffer 121, and a current flows from the second transmission buffer INV3 to the first transmission buffer INV2. Thereafter, after the delay time of the delay buffer 121, the output of the first transmission buffer INV2 becomes H, the output voltages of the first transmission buffer INV2 and the second transmission buffer INV3 become equal, and the current stops.
• the first and second transmission buffers INV2, INV3 are arranged such that the series of transmission current changes become a “transmission coil current”, ie, a triangular wave having the opposite polarity of the triangular waveform at point B, as shown at point D. Drive force is set.
• FIG. 4A is a side view of the stacked LSI including the first and third LSI chips 410 to 412.
• the contents of the transmission / reception circuit 401 are shown as a transmission / reception circuit 400.
• Arrow 403 represents inductive binding.
• FIG. 4B is a side view of the stacked LSI including the first to fourth LSI chips 420 to 423.
• the communication between the first LSI chip 420 and the third LSI chip 422 and the communication between the second LSI chip 421 and the fourth LSI chip 423 are performed at the same horizontal position. That is, a plurality of combinations of the transmission circuit and the reception circuit are independently inductively coupled using the same space. Since inductive coupling is performed at the same horizontal position, each communication is performed without crosstalk, for example, by time division.
• FIG. 5 is a view of a stacked LSI composed of the first to third LSI chips 510 to 512 as viewed laterally.
• the transmitting / receiving circuit 501 is the same as the transmitting / receiving circuit 400 shown in FIG.
• Arrow 503 represents an inductive connection, and indicates how multiple connections are established in parallel.
• a transmission / reception circuit that is not limited to the connection method can be changed. Although the power consumption of the transmission circuit increases, the configuration shown in Fig. 6 can be used if the main purpose is to reduce the circuit scale.
• the transmission circuit shown in FIG. 6 includes a storage element FF, a transmission buffer INV4, and a voltage source of a bias voltage Vbias.
• the transmission data Txdata is held in the storage element FF and is input to the transmission coil L1 via the transmission buffer INV4.
• the other end of the transmitting coil L1 is connected to the bias voltage Vbias.
• the receiving circuit receives only the signal for a predetermined period that is supposed to receive the received signal in synchronization with the receiving clock, thereby removing noises due to the clock and increasing the S / N ratio. be able to. All publications, patents, and patent applications cited herein are hereby incorporated by reference in their entirety.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Near-Field Transmission Systems (AREA)
• Semiconductor Integrated Circuits (AREA)
• Dc Digital Transmission (AREA)

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• 2004
  • 2004-02-13 JP JP2004037242A patent/JP4131544B2/ja not_active Expired - Lifetime
• 2005
  • 2005-02-14 TW TW094104197A patent/TW200532894A/zh not_active IP Right Cessation
  • 2005-02-14 US US10/588,769 patent/US7768790B2/en active Active
  • 2005-02-14 WO PCT/JP2005/002117 patent/WO2005078795A1/ja not_active Ceased
  • 2005-02-14 KR KR1020067017417A patent/KR101066128B1/ko not_active Expired - Lifetime

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