JP5600237B2 - 集積回路 - Google Patents
集積回路 Download PDFInfo
- Publication number
- JP5600237B2 JP5600237B2 JP2008023397A JP2008023397A JP5600237B2 JP 5600237 B2 JP5600237 B2 JP 5600237B2 JP 2008023397 A JP2008023397 A JP 2008023397A JP 2008023397 A JP2008023397 A JP 2008023397A JP 5600237 B2 JP5600237 B2 JP 5600237B2
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- JP
- Japan
- Prior art keywords
- transmission
- circuit
- pulse
- signal
- multiplexed signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
- H04J3/047—Distributors with transistors or integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
12 nビットカウンタ
13 リング発振器
14 送信回路
15、23 送信コイル
21 2n:1多重化器
22 送信回路
31、41 受信コイル
32 受信回路
33 位相補間器
42 受信回路
43 ダミー位相補間器
44 1:2n逆多重化器
51、52、54、55、111〜114、122〜127、211〜218、314、315、318、319、323〜336、711〜714、722〜727、 トランジスタ
53、56 電流源
57、58 抵抗
100 送信チップ
150 受信チップ
300 送信回路
311 パルス発生器
312、316、335、336 インバータ
313、317 NOR回路
320 送信コイル
321、322 抵抗
333、334 NAND回路
340 受信コイル
350 受信回路
411 制御回路
412 nビットカウンタ
413、431 リング発振器
415、515 2n:1多重化器
421、422 オンチップ配線
432、531 1:2n逆多重化器
500 送信チップ
514 1/2n-1分周期
521、522 チップ間配線
550 受信チップ
700 送信回路
715 遅延線
716 送信コイル
721 受信コイル
750 受信回路
Claims (5)
- リング発振器によって構成されていて、1つのシステムクロックからデータを送信するi個(iはi≧2の整数)のタイミングパルスを発生するパルス発生器と、
該タイミングパルスによって送信データをj:1(jは2≦j≦2iの整数)に多重化する多重化器と、
該多重化器によって多重化された多重化信号を誘導結合送信する第1送信器と、
前記タイミングパルスをi個ごとに繰り返し誘導結合送信する第2送信器と
を有する送信チップと、
前記多重化信号を誘導結合受信する第1受信器と、
前記タイミングパルスを誘導結合受信する第2受信器と、
該タイミングパルスによって前記多重化信号を1:jに逆多重化する逆多重化器と
を有し、前記送信チップに積層実装されている受信チップと
を備えることを特徴とする集積回路。 - 前記タイミングパルスから前記タイミングパルスの90度位相の補間タイミングパルスを発生する位相補間器を更に備え、
前記逆多重化器は、該補間タイミングパルスによって前記多重化信号を逆多重化することを特徴とする請求項1記載の集積回路。 - 前記第1送信器は、前記多重化信号を誘導結合送信する送信コイルを備え、該多重化信号に起因する信号を該送信コイルの一端に入力し、該多重化信号の逆極性信号に起因する信号を該送信コイルの他端に入力して、該送信コイルに該多重化信号の波形に相当する波形を入力することを特徴とする請求項1又は2記載の集積回路。
- 前記第1受信器は、前記多重化信号を誘導結合受信する受信コイルを備え、該受信コイルに誘起する電圧が第1閾値を上回ると出力を反転し、次に該受信コイルに誘起する電圧が第1閾値より小さい第2閾値を下回るとまた出力を反転し、次に該受信コイルに誘起する電圧が第1閾値を上回るとまた出力を反転することを繰り返すヒステリシス回路を構成していることを特徴とする請求項3記載の集積回路。
- 前記第1受信器は、前記受信コイルの中央を所定電位にバイアスするものであり、そのバイアス電圧を発生する回路は、前記第1受信器と同じ構成の回路の入力と出力を短絡又は抵抗短絡した構成であることを特徴とする請求項4記載の集積回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008023397A JP5600237B2 (ja) | 2008-02-02 | 2008-02-02 | 集積回路 |
US12/320,463 US8005119B2 (en) | 2008-02-02 | 2009-01-27 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008023397A JP5600237B2 (ja) | 2008-02-02 | 2008-02-02 | 集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009188468A JP2009188468A (ja) | 2009-08-20 |
JP5600237B2 true JP5600237B2 (ja) | 2014-10-01 |
Family
ID=40931650
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008023397A Active JP5600237B2 (ja) | 2008-02-02 | 2008-02-02 | 集積回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8005119B2 (ja) |
JP (1) | JP5600237B2 (ja) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5283075B2 (ja) | 2008-12-26 | 2013-09-04 | 学校法人慶應義塾 | 電子回路 |
JP5500081B2 (ja) * | 2009-02-09 | 2014-05-21 | 日本電気株式会社 | 信号伝達システム及び信号伝達方法 |
US20120002771A1 (en) * | 2009-03-05 | 2012-01-05 | Nec Corporation | Receiver, semiconductor device, and signal transmission method |
JP5504903B2 (ja) * | 2010-01-14 | 2014-05-28 | 日本電気株式会社 | 受信回路、受信方法及び信号伝達システム |
US8476953B2 (en) | 2011-08-25 | 2013-07-02 | International Business Machines Corporation | 3D integrated circuit stack-wide synchronization circuit |
US8381156B1 (en) | 2011-08-25 | 2013-02-19 | International Business Machines Corporation | 3D inter-stratum connectivity robustness |
US8525569B2 (en) | 2011-08-25 | 2013-09-03 | International Business Machines Corporation | Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network |
US8576000B2 (en) | 2011-08-25 | 2013-11-05 | International Business Machines Corporation | 3D chip stack skew reduction with resonant clock and inductive coupling |
US8519735B2 (en) | 2011-08-25 | 2013-08-27 | International Business Machines Corporation | Programming the behavior of individual chips or strata in a 3D stack of integrated circuits |
US8476771B2 (en) | 2011-08-25 | 2013-07-02 | International Business Machines Corporation | Configuration of connections in a 3D stack of integrated circuits |
US8587357B2 (en) | 2011-08-25 | 2013-11-19 | International Business Machines Corporation | AC supply noise reduction in a 3D stack with voltage sensing and clock shifting |
US8516426B2 (en) | 2011-08-25 | 2013-08-20 | International Business Machines Corporation | Vertical power budgeting and shifting for three-dimensional integration |
WO2013084517A1 (ja) * | 2011-12-05 | 2013-06-13 | 三菱電機株式会社 | 信号伝達回路 |
CN102684653B (zh) * | 2012-05-29 | 2015-07-01 | 中国电子科技集团公司第五十四研究所 | 一种数字同步脉冲无线低抖动传输方法 |
KR102048443B1 (ko) * | 2012-09-24 | 2020-01-22 | 삼성전자주식회사 | 근거리 무선 송수신 방법 및 장치 |
DE112012007198B4 (de) * | 2012-12-04 | 2021-08-26 | Mitsubishi Electric Corporation | Signalübertragungsschaltung |
US9286006B2 (en) * | 2013-04-05 | 2016-03-15 | Netapp, Inc. | Systems and methods for scheduling deduplication of a storage system |
US9509375B2 (en) | 2013-08-01 | 2016-11-29 | SK Hynix Inc. | Wireless transceiver circuit with reduced area |
EP3046302A4 (en) * | 2013-09-10 | 2017-04-05 | Sony Corporation | Communication apparatus and communication method |
JP7144696B2 (ja) * | 2018-06-14 | 2022-09-30 | 株式会社ソシオネクスト | 分周回路、通信回路、及び集積回路 |
WO2023162537A1 (ja) * | 2022-02-28 | 2023-08-31 | ローム株式会社 | パルス受信回路、信号伝達装置、電子機器、車両 |
Family Cites Families (14)
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DE2813764C3 (de) * | 1978-03-30 | 1981-09-03 | Siemens AG, 1000 Berlin und 8000 München | Elektromedizinisches Gerät zur Abnahme und Verarbeitung von elektrischen physiologischen Signalen |
JPH07288516A (ja) * | 1994-04-15 | 1995-10-31 | Fujitsu Ltd | シリアルデータ送受信回路 |
US5701037A (en) | 1994-11-15 | 1997-12-23 | Siemens Aktiengesellschaft | Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit |
US5559441A (en) * | 1995-04-19 | 1996-09-24 | Hewlett-Packard Company | Transmission line driver with self adjusting output impedance |
JP3792408B2 (ja) * | 1998-09-01 | 2006-07-05 | セイコーエプソン株式会社 | シリアルパラレル変換装置、半導体装置、電子機器及びデータ伝送システム |
US20020016917A1 (en) * | 2000-08-04 | 2002-02-07 | Tomohiko Kitamura | System integrated circuit |
JP4131544B2 (ja) * | 2004-02-13 | 2008-08-13 | 学校法人慶應義塾 | 電子回路 |
JP2005228951A (ja) * | 2004-02-13 | 2005-08-25 | Canon Inc | 光起電力素子とその製造方法 |
JP4193060B2 (ja) | 2004-06-04 | 2008-12-10 | 学校法人慶應義塾 | 電子回路 |
JP4677598B2 (ja) | 2004-08-05 | 2011-04-27 | 学校法人慶應義塾 | 電子回路 |
JP4124365B2 (ja) | 2004-08-24 | 2008-07-23 | 学校法人慶應義塾 | 電子回路 |
JP5024740B2 (ja) | 2004-09-30 | 2012-09-12 | 学校法人慶應義塾 | Lsiチップ試験装置 |
JP2006173986A (ja) | 2004-12-15 | 2006-06-29 | Keio Gijuku | 電子回路 |
JP2006173415A (ja) | 2004-12-16 | 2006-06-29 | Keio Gijuku | 電子回路 |
-
2008
- 2008-02-02 JP JP2008023397A patent/JP5600237B2/ja active Active
-
2009
- 2009-01-27 US US12/320,463 patent/US8005119B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2009188468A (ja) | 2009-08-20 |
US8005119B2 (en) | 2011-08-23 |
US20090196312A1 (en) | 2009-08-06 |
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