TWI634632B - 嵌入式半導體裝置封裝及其製造方法 - Google Patents

嵌入式半導體裝置封裝及其製造方法 Download PDF

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Publication number
TWI634632B
TWI634632B TW103131743A TW103131743A TWI634632B TW I634632 B TWI634632 B TW I634632B TW 103131743 A TW103131743 A TW 103131743A TW 103131743 A TW103131743 A TW 103131743A TW I634632 B TWI634632 B TW I634632B
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Taiwan
Prior art keywords
semiconductor device
dielectric
layer
dielectric layer
package structure
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TW103131743A
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English (en)
Chinese (zh)
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TW201523821A (zh
Inventor
Shakti Singh Chauhan
夏可堤 喬漢
Paul Alan Mcconnelee
保羅 麥可隆尼
Arun Virupaksha Gowda
艾倫 格達
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General Electric Company
通用電機股份有限公司
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Publication of TW201523821A publication Critical patent/TW201523821A/zh
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Publication of TWI634632B publication Critical patent/TWI634632B/zh

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    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
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KR101923659B1 (ko) * 2015-08-31 2019-02-22 삼성전자주식회사 반도체 패키지 구조체, 및 그 제조 방법
WO2017039275A1 (ko) 2015-08-31 2017-03-09 한양대학교 산학협력단 반도체 패키지 구조체, 및 그 제조 방법
JP6862087B2 (ja) * 2015-12-11 2021-04-21 株式会社アムコー・テクノロジー・ジャパン 配線基板、配線基板を有する半導体パッケージ、およびその製造方法
EP3443584B1 (en) * 2016-04-11 2021-11-03 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Batch manufacturing of component carriers and their related semi-finished product
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