TW201030904A - Package substrate with a cavity, semiconductor package and fabrication method thereof - Google Patents

Package substrate with a cavity, semiconductor package and fabrication method thereof Download PDF

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Publication number
TW201030904A
TW201030904A TW98103487A TW98103487A TW201030904A TW 201030904 A TW201030904 A TW 201030904A TW 98103487 A TW98103487 A TW 98103487A TW 98103487 A TW98103487 A TW 98103487A TW 201030904 A TW201030904 A TW 201030904A
Authority
TW
Taiwan
Prior art keywords
layer
metal
substrate
patterned
metal layer
Prior art date
Application number
TW98103487A
Other languages
Chinese (zh)
Other versions
TWI417993B (en
Inventor
Kuo-Ching Chen
Tsung-Yuan Chen
Cheng-Pin Chien
Original Assignee
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to TW98103487A priority Critical patent/TWI417993B/en
Publication of TW201030904A publication Critical patent/TW201030904A/en
Application granted granted Critical
Publication of TWI417993B publication Critical patent/TWI417993B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.

Description

201030904 六、發明說明： 【發明所屬之技術領域】 方法 本發明係有關於一種封裝基板、半 ㈣關於-種具，的封裝基==二 【先前技術】 近年來，三維立體(3D)構裝的快速發展 電路板上所佔的面積，同時 f大巾田縮小讀體在 將不同功能的晶片整合在的使用效率，更能201030904 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a package substrate, a semi-fourth package, and a package base == two [Prior Art] In recent years, three-dimensional (3D) structure The rapid development of the area occupied by the circuit board, while the large towel field shrinks the reading body in the use of different functions of the chip in the use efficiency, more

Pack咖SiP、w , 達到系統封裝物―η g，S!P)的以益。其中，層疊式封裝結構 體構㈣-種_，舉例纽，層疊式封 =量 ❹：及複雜的處理—，地減少 第圖繪不的疋傳統層叠式封裝結構的 1圖所示’傳統層疊式封裝結構!包含有—第二二:第 二封裝體3層疊在第—封裝 ㈣2以及第 u 2〇 ^览^ . 之上。第—封裝體2包括一第一晶 上’第一晶片2〇透過接合導線— wire)26，如金線，與第—其 土板22構成電性連接，第一晶片20與接 5 201030904 .·合導線26被一模塑材料24包覆住。第二封農體3包括一第二晶片 30設於-第二基板32上，第二晶片3〇透過接合導線兄與第二基 板32構成電性連接，第一晶片3〇與接合導線％同樣被一模塑材料 34包覆住。第二封裝體3的第二基板32藉由錫球4〇與第一封裝體 2的第-基板22構成雜連接，通f，在第—基板22與第二基板 32之間會填入底膠42 ’以免錫球4〇受到外力破壞。 ❹ 上述傳統層疊式封裝結構至少包括以下的缺點：⑴錫球4〇的 大小受限於第-基板22與第二基板32之間的距離。锡球4〇的高度 必須超過模塑材料24的高度’以確保第一基板22與第二基板32 之間的電性連接，因而無法進一步縮小踢球節距⑽ch)，導致錫球 4〇的數目以及輸出輸入接_〇)數難以提升；(2)第一基板22與第 二基板32的熱膨脹係數(CTE)不同導致錫球初可能受到*同程度的 j力’影響到封裝體的可靠度；⑶錫球4〇的共面性控制不易使 ❹付封裝製程的餘欲度(process window)較小；⑷需額外進行第一基板 22與第二基板32之間的灌膠步驟；（5)堆疊體積較大。 【發明内容】 本發明之主要目的在提供一種改良的封裝基板、層疊式封裝體 及其製作方法，以解決並克服先前技藝之不足及缺點。 根據本發明之一較佳實施例，本發明提供一種封裝基板的製作 201030904 '方法’包含有：提供-包層板’包含—第—金屬層、—第二金屬層 及-中間層，中間詹介於第一金屬層及第二金屬層之間；敍刻部分 的第-金屬層’暴露出部分的中間層並形成—金屬塊體；將包層板 與-第-銅fi基板壓合，第—銅板包含—第—絕緣層以及一第 -銅箱層；線路圖案化第一銅競’形成一第一圖案化線路·，線路 圖案化第二金屬層’形成一第二圖案化線路；移轉金屬塊體，形 成一凹穴結構；以及去除位於凹穴結構内的中間層。 ❹ 根據本發明之另一較佳實施例，本發明提供一種半導體封裝體 的製作方法，包含有：提供一包層板，包含一第一金屬層、一第二 金屬層及-中間層，介於第一金屬層及第二金屬層之間；_部分 的第-金屬層，暴露出部分的中間層並形成一金屬塊體；將包層板 與-第-銅絲板壓合’第—銅箱基板包含—第—絕緣層以及一第 -銅箱層；線路圖案化第一賴，形成一第一圖案化線路;線路 〇圖案化第二金屬層，形成一第二圖案化線路，其中第二圖案化線路 包s連接金屬塊體的複數個覆晶接墊；移除掉金屬塊體，形成一凹 穴結構；去除位於凹穴結構内的中間層；於凹穴結構内置入一覆晶 曰曰片，其主動面朝下透過錫球與相對應的覆晶接墊電連接；以及將 一填充材料填入凹穴結構内，密封住覆晶晶片。 根據本發明之較佳實細，本發贿供―種具凹穴結構 的封裝基板’包含有：-第一絕緣層；一凹穴結構，位於第一絕緣 層中；-第-圖案化線路，位於第一絕緣層的一面上；一第二圖案 201030904 中第二圖荦化綠 位於第-絕緣層的另-面上，其 第-圖案化線路包含有複數個覆晶接塾，位 以及複數個第-導電通孔，位、-構的底心 索哲 。邑緣層中，用來電連接第一圖 _。。州：咖線路為—雙層金屬結 魯 一為^使貴審查委員能更進一步了解本發明之特徵及技術内 町械本剌之詳細與關。細所關式僅供 參考與輔助說日·，並非用來對本發明加以限制者。 【實施方式】 凊參閱第2圖至帛η圖，其為依據本發明較佳實施例所緣示的 層疊式封裝結構的製作方法。首先，如第2圖所示，提供一包層板 例如銅-錦-銅(Cu-Ni-Cu)複合金屬基材、銅_紹_銅(cu_Ai_〇j) ❹複σ金屬基材或者銅镇基板(copper clad laminate，CCL)。包層板1 〇〇 包括一中間層1G2、-第-金屬層1〇4,設於中間層1G2的第一面上， 以及一第二金屬層106，設於中間層1〇2的相反於第一面的第二面 上，其中，第一金屬層104較佳為銅金屬，其厚度例如，約為3〇 微米至150微米之間，且大於第二金屬層1〇6的厚度，第二金屬層 1〇6較佳為銅金屬，其厚度約為1微米至5〇微米之間。若包層板· 為銅箔基板，則其中間層102可以為玻纖布、環氧樹脂或熱固性樹 脂等。 8 201030904 如第3圖所示，進行一微影製程及蝕刻製程，蝕刻掉部分的第 一金屬層104，以形成一金屬塊體l〇4a。前述之微影製程及触刻製 程包括在第一金屬層104形成一光阻圖案(圖未示），定義出欲形成 金屬塊體的範圍及形狀’然後再以濕姓刻法或乾触刻法餘刻掉未被 光阻圖案覆蓋住的第一金屬層104,直到暴露出中間層102。根據本 發明之較佳實施例’金屬塊體104a的長X寬尺寸大小約介於 ❹ 0.5mmx〇.5mm至lOmmxlOmm之間。此外，根據本發明之另一較 佳實施例，也可以將中間層102蝕刻掉，僅留下位於金屬塊體1〇4a 正下方的部分中間層102。 如第4圖所示’在形成金屬塊體i〇4a之後，將包層板1〇〇與一 單面銅的第一銅箔基板110壓合成一基板2〇〇，其中，第一銅羯基 板110包括一第一絕緣層112 ’例如，prepreg，以及一第一銅箔層 114。此時’基板200的第一面2〇〇a有第一銅箔層114,第二面200b © 有第二金屬層106。 如第5圖所示，接著進行導電通孔製程，在基板2〇〇中形成複 數個第一導電通孔120 ’其電連接基板2〇〇第一面200a上的第一銅 箔層114以及第二面200b上的第二金屬層106。前述的導電通孔製 程乃公知技藝，其大致上包括鑽孔、化學銅電鍍及電鍍銅等步驟。 如第6圖所示’接著進行微影製程及蝕刻製程，在基板2〇〇的 201030904 第一面200a上蝕刻掉部分的第一銅箔層114及在第二面200b上蝕 刻掉部分的第二金屬層1〇6以及中間層102，如此分別在基板200 的第一面200a及第二面200b上形成第一圖案化線路114a及第二圖 案化線路106a。值得注意的是，此時第二圖案化線路106&包含有 部分的第二金屬層1〇6以及部分的中間層1〇2。且，第二圖案化線 路l〇6a更包含有複數個與金屬塊體i〇4a連接的覆晶接墊(flip_chip bond pad) 106b。 e 如第7圖所示，接著進行一增層壓合流程，在基板2〇〇的第一 面200a及第二面200b上分別壓合一單面銅的第二銅箔基板13〇以 及一單面銅的第三銅箔基板14〇，形成一四層基板3〇〇，其中，第二 銅箔基板130包括一預留的開孔135，位於金屬塊體l〇4a的正上 方’以暴露出金屬塊體l〇4a。第二銅箔基板130包括一第二絕緣層 132 ’例如介電層以及一第二銅箔層134，而第三銅箔基板14〇包括 一第三絕緣層142以及一第三銅箔層144。 ❿ 如第8圖所示，接著依序進行一雷射成孔製程、導電通孔製程 以及外部線路圖案化製程，在四層基板3〇〇的第一面3〇〇a上形成第 二圖案化線路134a，在四層基板3〇〇的第二面3〇〇b上形成第四圖 案化線路144a ’其中，第三圖案化線路134a經由形成在第二絕緣 層132中的第二導電通孔138與第一圖案化線路114&電性連接，而 第四圖案化線路144a經由形成在第三絕緣層142中的第三導電通孔 148與第二圖案化線路l〇6a電性連接。 201030904 如第9圖所示，隨後進行—防焊層步驟，在四層基板的第 -面施錢第二面雇上分卿翁焊層⑼及防焊層⑽: 防焊層15〇及防知層100可以由感紐材料所構成者。接著，利用 微影製程，在防焊層150及防焊層⑽中形成開孔挪及職， 分別暴露出部分的第三圖案化線路⑽以及第四圖案化線路144a。 β ^第10圖所示，接著在暴露出來的銅表面上形成銻金層170或 其它抗氧化金屬表面處理。需注意的是，此時在金屬塊體馳的表 =上不形成齡層。例如，可以在形成齡層17G或其它抗氧化金 私面處理時，將金屬塊體1(Ha的表面以光阻先覆蓋住，舰待鑛 疋錦金層後，再將光阻剝除。 如第11圖所示’接著進行一驗性钮刻步驟，將未覆錄金層的金 ❹ 鬼體104a以及位於金屬塊體1〇如正下方的中間層⑽完全触除 ^再以-酸性溶液微細穴，暴露出覆晶接塾祕，如此即形成 —具凹穴結構18G的四層基板。需注意的是，第2圖至第u圖 2的製作流程是針對四層板結構所設計，本發明亦可以應用在雙層 二層板、六層減八層板等其它*同封裝基板結構。 如第12圖所示，在完成具凹穴結構18〇的四層基板之後， ^著在凹穴結構180内置入一覆晶晶片400，其主動面偷朝下透 k锡球402與相對應的覆晶接塾l〇6b電性連接。隨後，將一填充材 11 201030904 料41〇，例如，環氧樹脂基體材料，填入凹穴結構180内，密封住 覆晶晶片400，如此即形成一將覆晶晶片400嵌入四層基板300中 的封裝體5〇0。根據本發明之較佳實施例，此時填充材料的表 面約略與防焊層150的表面共平面。 如第13圖所示，在完成封裝體500之後，接著於封裝體5〇〇上 層疊- ic封裝體600，IC封裝體_包括晶片7〇〇,設於一基板⑽ ❹的第一面上’模封材料710包覆住晶片7〇〇,複數個錫球6〇2，設於 基板㈣的第二面上’透過錄/金層17〇對應電性連接到第三圖案化 以上所述僅為本發明之較佳實施例，凡依本發咐請專利範圍 斤做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1_示的是傳統層疊式封裝結構的剖面結構示意圖。 瞻縣翻崎__爾柄裝結構 【主要元件符號說明】 層疊式封裝結構 201030904 2第一封裝體 3第二封裝體 20第一晶片 22第一基板 24、34模塑材料 26、36接合導線 30第二晶片 H 32第二基板 40、402、602 錫球 42底膠 100包層板 102中間層 104第一金屬層 104a金屬塊體 106第二金屬層 106a第二圖案化線路 106b覆晶接墊 110第一銅猪基板 112第一絕緣層 114第一銅箱層 114a第一圖案化線路 120第一導電通孔 130第二銅箔基板 201030904 132第二絕緣層 134第二銅箔層 134a第三圖案化線路 135、150a、160a 開孔 138第二導電通孔 140第三銅羯基板 142第三絕緣層 0 144第三銅箔層 144a第四圖案化線路 148第三導電通孔 150、160防焊層 170鎳金層 180凹穴結構 200、610 基板 200a、300a 第一面 200b、300b 第二面 300四層基板 400覆晶晶片 400a主動面 410填充材料 500封裝體 600 1C封裝體 700晶片 201030904 710模封材料Pack coffee SiP, w, to achieve the benefits of the system package - η g, S! P). Among them, the stacked package structure (4) - species _, for example, cascading seal = amount ❹: and complex processing - to reduce the number of the traditional cascading package structure shown in Figure 1 'traditional cascading The package structure includes: the second two: the second package 3 is stacked on the first package (four) 2 and the second layer. The first package 20 includes a first on-chip 'first wafer 2' through the bonding wire-wire 26, such as a gold wire, and is electrically connected to the first earth plate 22, and the first wafer 20 is connected to 5 201030904. The bonding wire 26 is covered by a molding material 24. The second agricultural body 3 includes a second wafer 30 disposed on the second substrate 32. The second wafer 3 is electrically connected to the second substrate 32 through the bonding wire brother. The first wafer 3 is the same as the bonding wire %. It is covered by a molding material 34. The second substrate 32 of the second package 3 is connected to the first substrate 22 of the first package 2 by the solder balls 4, and is connected to the first substrate 22 and the second substrate 32. Glue 42 'to avoid damage to the solder ball 4 外. The above conventional stacked package structure includes at least the following disadvantages: (1) The size of the solder balls 4 is limited by the distance between the first substrate 22 and the second substrate 32. The height of the solder ball 4 must exceed the height ' of the molding material 24 to ensure an electrical connection between the first substrate 22 and the second substrate 32, so that the kick pitch (10) ch) cannot be further reduced, resulting in a solder ball. The number and the number of output inputs are difficult to increase; (2) the difference in thermal expansion coefficient (CTE) between the first substrate 22 and the second substrate 32 causes the solder ball to be affected by the same degree of j force to the package. (3) The coplanarity control of the solder ball 4〇 is not easy to make the process window of the package processing process small; (4) the additional step of filling the first substrate 22 and the second substrate 32 is required; 5) The stacking volume is large. SUMMARY OF THE INVENTION A primary object of the present invention is to provide an improved package substrate, stacked package, and method of fabricating the same that solves and overcomes the deficiencies and shortcomings of the prior art. According to a preferred embodiment of the present invention, the present invention provides a fabrication of a package substrate. 201030904 'Method' includes: providing a cladding layer comprising - a metal layer, a second metal layer and an intermediate layer, Between the first metal layer and the second metal layer; the first metal layer of the engraved portion exposes a portion of the intermediate layer and forms a metal block; the cladding plate is pressed against the --copper fi substrate, The first copper plate comprises a first insulating layer and a first copper box layer; the line patterned first copper competes to form a first patterned line, and the line patterned second metal layer ' forms a second patterned line; The metal block is transferred to form a recessed structure; and the intermediate layer located within the recessed structure is removed. According to another preferred embodiment of the present invention, the present invention provides a method of fabricating a semiconductor package, comprising: providing a cladding board comprising a first metal layer, a second metal layer, and an intermediate layer; Between the first metal layer and the second metal layer; the first metal layer of the portion, exposing a portion of the intermediate layer and forming a metal block; pressing the cladding plate with the --copper wire plate 'first The copper box substrate comprises a first insulating layer and a first copper layer; the circuit pattern is first patterned to form a first patterned line; and the second layer is patterned to form a second patterned line, wherein the second patterned layer is formed The second patterned circuit package s is connected to the plurality of flip-chip pads of the metal block; the metal block is removed to form a recess structure; the intermediate layer located in the recess structure is removed; and a recess is built in the recess structure The wafer is electrically connected downwardly through the solder ball to the corresponding flip chip; and a filling material is filled into the recess structure to seal the flip chip. According to a preferred embodiment of the present invention, the present invention provides a package substrate of a recessed structure comprising: a first insulating layer; a recessed structure in the first insulating layer; - a first patterned line The second pattern 201030904 is located on the other side of the first insulating layer, and the first patterned line includes a plurality of flip-chip contacts, and A plurality of first-conducting through-holes, and the bottom of the structure. In the edge layer, it is used to electrically connect the first figure _. . State: The coffee line is a double-layer metal knot. Lu Yiwei ^ enables the review committee to further understand the characteristics and technology of the present invention. The details are for reference and assistance only, and are not intended to limit the invention. [Embodiment] Referring to Figures 2 to 2, there is shown a method of fabricating a stacked package structure according to a preferred embodiment of the present invention. First, as shown in FIG. 2, a clad plate such as a copper-gold-copper (Cu-Ni-Cu) composite metal substrate, a copper-copper (cu_Ai_〇j) ❹ complex σ metal substrate or Copper clad laminate (CCL). The cladding board 1 includes an intermediate layer 1G2, a -metal layer 1〇4, a first surface of the intermediate layer 1G2, and a second metal layer 106 disposed opposite to the intermediate layer 1〇2. The second surface of the first surface, wherein the first metal layer 104 is preferably copper metal, and the thickness thereof is, for example, between about 3 Å and 150 μm, and is greater than the thickness of the second metal layer 〇6, The two metal layers 1〇6 are preferably copper metal having a thickness of between about 1 micrometer and 5 micrometers. If the clad plate is a copper foil substrate, the intermediate layer 102 may be a fiberglass cloth, an epoxy resin or a thermosetting resin. 8 201030904 As shown in FIG. 3, a lithography process and an etching process are performed to partially etch away the first metal layer 104 to form a metal block 10a. The lithography process and the etch process include forming a photoresist pattern (not shown) on the first metal layer 104, defining a range and shape of the metal block to be formed, and then engraving or dry etching The first metal layer 104 not covered by the photoresist pattern is engraved until the intermediate layer 102 is exposed. According to a preferred embodiment of the present invention, the metal block body 104a has a length X width dimension of between about 0.5 mm x 〇 5 mm to 10 mm x 10 mm. Moreover, in accordance with another preferred embodiment of the present invention, the intermediate layer 102 can also be etched away leaving only a portion of the intermediate layer 102 directly below the metal block 1〇4a. As shown in FIG. 4, after forming the metal block i〇4a, the clad plate 1〇〇 and a single-sided copper first copper foil substrate 110 are pressed into a substrate 2〇〇, wherein the first copper crucible The substrate 110 includes a first insulating layer 112', such as a prepreg, and a first copper foil layer 114. At this time, the first surface 2A of the substrate 200 has the first copper foil layer 114, and the second surface 200b has the second metal layer 106. As shown in FIG. 5, a conductive via process is then performed to form a plurality of first conductive vias 120' in the substrate 2'' to electrically connect the first copper foil layer 114 on the first surface 200a of the substrate 2'' and The second metal layer 106 on the second side 200b. The foregoing conductive via process is well known in the art and generally includes the steps of drilling, chemical copper plating, and electroplating copper. As shown in FIG. 6 'subsequent to the lithography process and the etching process, a portion of the first copper foil layer 114 is etched away on the first surface 200a of the substrate 30 2010 201030904 and a portion etched away on the second surface 200b The second metal layer 1〇6 and the intermediate layer 102 form a first patterned line 114a and a second patterned line 106a on the first surface 200a and the second surface 200b of the substrate 200, respectively. It should be noted that at this time, the second patterned wiring 106& includes a portion of the second metal layer 1〇6 and a portion of the intermediate layer 1〇2. Further, the second patterning line 106a further includes a plurality of flip-chip bond pads 106b connected to the metal block i〇4a. e, as shown in FIG. 7, a lamination process is further performed, and a second copper foil substrate 13 and a single-sided copper are respectively laminated on the first surface 200a and the second surface 200b of the substrate 2A. The third copper foil substrate 14〇 of the single-sided copper forms a four-layer substrate 3〇〇, wherein the second copper foil substrate 130 includes a reserved opening 135 located directly above the metal block 104a The metal block l〇4a is exposed. The second copper foil substrate 130 includes a second insulating layer 132 ′ such as a dielectric layer and a second copper foil layer 134 , and the third copper foil substrate 14 〇 includes a third insulating layer 142 and a third copper foil layer 144 . . ❿ As shown in FIG. 8 , a laser hole forming process, a conductive via process, and an external line patterning process are sequentially performed to form a second pattern on the first surface 3〇〇a of the four-layer substrate 3〇〇. The wiring 134a forms a fourth patterned wiring 144a on the second surface 3b of the four-layer substrate 3', wherein the third patterned wiring 134a passes through the second conductive via formed in the second insulating layer 132. The hole 138 is electrically connected to the first patterned line 114& and the fourth patterned line 144a is electrically connected to the second patterned line 106a via the third conductive via 148 formed in the third insulating layer 142. 201030904 As shown in Figure 9, the subsequent solder mask step is applied to the second side of the four-layer substrate. The second side of the four-layer substrate is coated with a separate layer of the weld layer (9) and the solder resist layer (10): the solder resist layer 15 and the anti-solder layer The layer 100 can be composed of a material of the sense. Next, by the lithography process, openings are formed in the solder resist layer 150 and the solder resist layer (10), and a portion of the third patterned line (10) and the fourth patterned line 144a are exposed, respectively. As shown in Fig. 10, a gold layer 170 or other anti-oxidation metal surface treatment is then formed on the exposed copper surface. It should be noted that at this time, the age layer is not formed on the surface of the metal block. For example, the metal block 1 (the surface of Ha may be covered with photoresist first) after forming the age layer 17G or other anti-oxidation gold private surface, and the photoresist is stripped after the ship is subjected to the gold layer. As shown in Fig. 11, 'A subsequent inductive buttoning step is performed to completely remove the gold layer ghost body 104a which is not covered with the gold layer and the intermediate layer (10) which is located directly below the metal block body 1 and then -acid The micro-cavity of the solution exposes the crystal-clearing junction, thus forming a four-layer substrate with a recessed structure of 18G. It should be noted that the fabrication process of the second to the second embodiment is designed for the four-layer structure. The present invention can also be applied to other double-layered boards, six-layered and eight-layer boards, and the like. As shown in Fig. 12, after completing the four-layer substrate with the recessed structure 18〇, A flip-chip wafer 400 is embedded in the recess structure 180, and the active surface is sneaked downward through the k-tin ball 402 to be electrically connected to the corresponding flip-chip interface 〇6b. Subsequently, a filler material 11 201030904 is 41 〇 For example, an epoxy resin base material is filled into the recess structure 180 to seal the flip chip 400, thus forming The package 50 〇 0 is embedded in the four-layer substrate 300. According to a preferred embodiment of the present invention, the surface of the filling material is approximately coplanar with the surface of the solder resist layer 150. After the package 500 is completed, an ic package 600 is further stacked on the package 5, and the IC package _ includes a wafer 7 〇〇 disposed on the first surface of the substrate (10) 模 a molding material 710 Covering the wafer 7 〇〇, a plurality of solder balls 6 〇 2, disposed on the second surface of the substrate (4) 'transmission recording/gold layer 17 〇 correspondingly electrically connected to the third patterning. In the preferred embodiment, the equivalent variation and modification of the patent scope of the present invention should be within the scope of the present invention. [Simplified Schematic] The first section shows the cross-sectional structure of the conventional stacked package structure. Schematic. Zhanxian Razaki __ handle structure [main component symbol description] Cascaded package structure 201030904 2 first package 3 second package 20 first wafer 22 first substrate 24, 34 molding materials 26, 36 Bonding wire 30 second wafer H 32 second substrate 40, 402, 602 solder ball 4 2 primer 100 cladding board 102 intermediate layer 104 first metal layer 104a metal block 106 second metal layer 106a second patterned line 106b flip chip 110 first copper pig substrate 112 first insulating layer 114 first copper Box layer 114a first patterned line 120 first conductive via 130 second copper foil substrate 201030904 132 second insulating layer 134 second copper foil layer 134a third patterned line 135, 150a, 160a opening 138 second conductive Hole 140 third copper germanium substrate 142 third insulating layer 0 144 third copper foil layer 144a fourth patterned line 148 third conductive via 150, 160 solder resist layer 170 nickel gold layer 180 recess structure 200, 610 substrate 200a 300a first side 200b, 300b second side 300 four-layer substrate 400 flip chip 400a active surface 410 filling material 500 package 600 1C package 700 wafer 201030904 710 molding material

Claims (1)

201030904 七 、申請專利範圍 1. 一種封裝基板的製作方法，包八 提供-包層板，包含__第—上含有： 該中間層介於該第—賴層及!^層、1二金朗及-t間層， 蝕刻部分的該第—金屬層，^ —金屬層之間； 塊體； 、露出部分的該中間層並形成-金屬 將該包層板與一第—鋼箔基被 絕緣層以及一第一銅萡層，· 合’該第—鋼箔基板包含一第一 線路圖案化該第-鋼箱層， 線路圖案化該第二金屬層，，第一圖案化線路； 移除掉該金屬塊體，形成二，—第二圖案化線路； *除位於該凹穴結構内的二:構;以及 如申請專利範圍第！項所述 金屬層的厚度大於鄉二金初作枝，其中該第一 H申料機轉2項㈣之縣 金屬層的厚度介於30微米至15Q微米之間。製作方去，財該第- 二如:：=r述之封裝基板_ I、微核5G微米之間。 16 201030904 5.如申請專利範圍第1 金屬層包含銅。 項所述之封錄板的製作 方法，其中該第 6.如申請專利範圍第1 金屬層包含銅。 項所述之封裝基板的製作方法，其中該第二 7.如申請專利範圍第〗 層包含鋅、^基板的製作絲，其中該中間 ❹ 玻纖布、環氣 8如申請專利範圍第！項所述之 圖案化線路包含位於該 板職作方U該第一 、、°構底部的複數個覆晶接墊。 剩第^娜罐作方法， 於該第-絕緣層中形成複數個第 其中另包含 導電通孔 其中另包含 ⑽娜娜作方法， 有以下步驟： 於該第一圖案化線路上壓人一 板包含H緣料及H第:;細基板，其找第二鋪基 相對應於該金屬塊體之開孔杯;6層’且二碱基板具有一 t該第二絕緣層中形成複數個第二導電通孔；以及 表路圖案化該第二銅荡層’形成—第三圖案化線路。 201030904 11· -種半導體封裝體的製作方法，包含有. 提供一包層板’包含—第—合屬 ^ ^ 、屬層、一第二金屬層及一中間層， 該中間層，,於該第一金屬層及該第二金屬層之間. 金屬 關部分的該第—金屬層，暴露出部分的該中間層並形成-塊體； 第一 ❹ 將該包層板與-第-銅·板壓合，該第一編基板包含 絕緣層以及一第一銅箔層； 線路圖案化該第-銅箱層，形成一第一圖案化線路； 線路圖案化該第二金屬層，形成—第二圖案化線路，其中 圖案化線路包含連麟金屬塊體的複數個覆晶接塾； 一 移除掉該金屬塊體，形成一凹穴結構· 去除位於該凹穴結構内的該中間層； 、亥凹八、、構内置入一覆晶晶片，其主動面朝下透過錫 應的該覆晶接墊電連接；以及 、相對 將一填充材料填入該凹穴結構内，密封住該覆晶晶片。 12.如申請專利翻第n項所述之半導體封裝體的製作方法 該第一金屬層的厚度大於該第二金屬層的厚度。 、 13·如申請專利範圍第12項所述之半導體封裝體的製作方法1 該第-金屬層的厚度介於30微来至15〇微米之間。 ’其中 18 201030904 14·如申請專利範圍第12項所述之料 該第二金屬層的厚度介於】微米至5〇微米之的製作方法，其令 ❹ 15.如申請專利範圍第η 該第一金屬層包含銅。 16·如申請專利範圍第11 5亥第一金屬層包含銅。 項所述之轉_裝_製作方法， 項所述之轉_物㈣作方法， 其中 其中 專利細第U項所狀轉_㈣㈣作 另包含有以下步驟： 其中 於該第一絕緣層中形成複數個第一導電通孔。201030904 VII. Patent application scope 1. A method for fabricating a package substrate, the package 8 provides a cladding plate, including __第-: contains: the intermediate layer is between the first layer and the layer, and the second layer And the inter-t layer, the first metal layer of the etched portion, between the metal layers; the bulk; the exposed portion of the intermediate layer and the metal-inserting the cladding plate and the first steel foil substrate a layer and a first copper layer, the 'the first steel foil substrate comprises a first line patterned the first steel box layer, the line patterned the second metal layer, the first patterned line; The metal block is removed to form a second, second patterned line; * except for the two structures located within the recess structure; and as claimed in the patent scope! The thickness of the metal layer is greater than that of the township, and the thickness of the metal layer of the county (2) is between 30 micrometers and 15 micrometers. The producer goes, the financial one - two such as: : = r described package substrate _ I, micronuclear 5G micron. 16 201030904 5. The first metal layer contains copper as claimed in the patent application. The method for producing a seal plate according to the invention, wherein the sixth metal layer of the patent application scope comprises copper. The method for fabricating a package substrate according to the invention, wherein the second layer, as in the scope of the patent application, comprises a wire made of zinc and a substrate, wherein the intermediate fiberglass cloth and the ring gas 8 are as claimed in the patent scope! The patterned circuit of the item includes a plurality of flip chip pads at the bottom of the first and lower structures of the board U. a method for forming a plurality of cans in the first insulating layer, wherein the plurality of conductive vias are further included in the first insulating layer, and the method further comprises: (10) Nana, the following steps: pressing a board on the first patterned circuit Comprising a H-edge material and a H-th:; a fine substrate, wherein the second substrate is corresponding to the open-cell cup of the metal block; the 6-layer' and the di-alkali substrate have a t-the second insulating layer forms a plurality of a second conductive via; and a surface patterning the second copper layer to form a third patterned line. 201030904 11 - A method for fabricating a semiconductor package, comprising: providing a cladding board comprising: a first-part, a genus layer, a second metal layer and an intermediate layer, the intermediate layer Between the first metal layer and the second metal layer. The first metal layer of the metal off portion exposes a portion of the intermediate layer and forms a block; the first layer of the cladding plate and the -th-copper layer Pressing the board, the first braided substrate comprises an insulating layer and a first copper foil layer; the circuit patterning the first copper box layer to form a first patterned line; and the circuit patterning the second metal layer to form a first a patterned circuit, wherein the patterned circuit comprises a plurality of flip-chip contacts of a lining metal block; a metal block is removed to form a recess structure; and the intermediate layer is disposed within the recess structure; , the recessed eight, the built-in into a flip chip, the active face down through the tin should be electrically connected to the flip chip; and a relatively filling material into the recess structure, sealing the cover Crystal wafer. 12. The method of fabricating the semiconductor package of claim n, wherein the thickness of the first metal layer is greater than the thickness of the second metal layer. 13. The method of fabricating a semiconductor package according to claim 12, wherein the thickness of the first metal layer is between 30 micrometers and 15 micrometers. '18 201030904 14 · The material of the second metal layer as described in claim 12, the thickness of the second metal layer is between 5 micrometers and 5 micrometers, and the method is as follows: A metal layer contains copper. 16. The first metal layer of the 11th hexa if the patent application scope contains copper. The method of manufacturing the method described in the item, wherein the method of converting the fourth item of the patent, the method of the fourth item of the patent, further comprises the following steps: wherein the first insulating layer is formed A plurality of first conductive vias. 19 201030904 作方法，其中 2〇.如申請專利範圍第W項所述之半導體封裝體的製 另包含有以下步驟： 於該第三圖案化線路上層疊—Ic封裝體。 21. —種具凹穴結構的封裝基板，包含有： 一第一絕緣層； ❹ 一凹穴結構，位於該第一絕緣層中； :第一圖案化線路，位於該第—絕緣層的—面上. 層的m線=對=第一圖案化線路而位於該第一絕緣 於該—底 槿，雔思人显 刀该第一圖案化線路為-雙層金屬結 複數t 包含―網以及一中間金屬層；以及 -圖宰化魏2電舰細^第―絕騎巾，絲雜連接該第 ❿ 圖案化線路與該第二圖案化線路。 接/弟 ====12 _^_物臟，其中該 2::=:=:娜基 Η 線路，位於該第二絕緣層上。第瞧線路ϋ三圈索化 20 201030904 24.如申請專利範圍第23項所述之具凹穴結構的封裝基板，其中另 包含有複數個第二導電通孔，位於該第二絕緣層中，用來電性連接 該第一圖案化線路與該第三圖案化線路。 八、圖式：19 201030904. The method of claim 2, wherein the semiconductor package of claim W further comprises the step of: laminating an Ic package on the third patterned line. 21. A package substrate having a recessed structure, comprising: a first insulating layer; a recessed structure in the first insulating layer; a first patterned line on the first insulating layer - The m line of the layer = the pair = the first patterned line and the first insulation is located at the bottom - the bottom line, the first patterned line is - the double layer metal junction complex t contains - net and An intermediate metal layer; and - the slain Wei 2 electric ship fine ^ first - absolutely riding towel, the wire is connected to the second patterned circuit and the second patterned circuit. The younger brother ====12 _^_ is dirty, where the 2::=:=: Naji Η line is located on the second insulating layer. The second substrate is provided with a plurality of second conductive vias, and is disposed in the second insulating layer, wherein the package substrate has a recessed structure as described in claim 23, further comprising a plurality of second conductive vias. The first patterned line and the third patterned line are electrically connected. Eight, the pattern: 21twenty one
TW98103487A 2009-02-04 2009-02-04 Package substrate with a cavity, semiconductor package and fabrication method thereof TWI417993B (en)

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TWI602270B (en) * 2012-12-11 2017-10-11 三星電機股份有限公司 Chip-embedded printed circuit board and semiconductor package using the pcb, and manufacturing method of the pcb
TWI611523B (en) * 2014-09-05 2018-01-11 矽品精密工業股份有限公司 Method for fabricating semiconductor package
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TWI634632B (en) * 2013-09-26 2018-09-01 通用電機股份有限公司 Embedded semiconductor device package and method of manufacturing thereof

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CN104979219A (en) * 2014-04-08 2015-10-14 矽品精密工业股份有限公司 Method for manufacturing package structure
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