TWI482278B - 以閘流體為基礎之記憶體單元、包含其之裝置及系統及用於形成其之方法 - Google Patents
以閘流體為基礎之記憶體單元、包含其之裝置及系統及用於形成其之方法 Download PDFInfo
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- TWI482278B TWI482278B TW100106775A TW100106775A TWI482278B TW I482278 B TWI482278 B TW I482278B TW 100106775 A TW100106775 A TW 100106775A TW 100106775 A TW100106775 A TW 100106775A TW I482278 B TWI482278 B TW I482278B
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Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1027—Thyristors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42308—Gate electrodes for thyristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
- H10B99/20—Subject matter not provided for in other groups of this subclass comprising memory cells having thyristors
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
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Description
本發明之實施例係關於以閘流體為基礎之記憶體單元,包含一個或多個閘流體之半導體裝置及用於形成此等記憶體單元及半導體裝置之方法。
本申請案係關於與其在2010年3月2日提出申請之序列號為12/715,704且題目為「SEMICONDUCTOR-METAL-ON-INSULATOR STRUCTURES,METHODS OF FORMING SUCH STRUCTURES,AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES」之共同待決美國專利申請案;與其在2010年3月2日提出申請之序列號為12/715,843且題目為「FLOTING BODY CELL STRUCTURES,DEVICES INCLUDING SAME,AND METHODS FOR FORMING SAME」之共同待決美國專利申請案;與其在2010年3月2日提出申請之序列號為12/715,743且題目為「SEMICONDUCTOR DEVICES INCLUDING A DIODE STRUCTURE OVER A CONDUCTIVE STRAP,AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES」之共同待決美國專利申請案;及與其在2010年3月2日提出申請之序列號為12/715,922且題目為「SEMICONDUCTOR CELLS,ARRAYS,DEVICES AND SYSTEMS HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME」之共同待決美國專利申請案,該等共同待決美國專利申請案所揭示之內容皆以引用之方式併入本文中。
傳統上,積體電路(IC)記憶體裝置包含靜態隨機存取記憶體(SRAM)。習用SRAM係基於與以低電壓位準運作且以相對高速度執行之習用記憶體元件(諸如互補金屬氧化物半導體(CMOS)裝置)相容之四-電晶體記憶體單元(4T SRAM單元)或六-電晶體記憶體單元(6T SRAM單元)。然而,習用SRAM耗佔一大的單元面積,這限制SRAM之高密度設計。
為了試圖減小IC記憶體裝置之面積,已製造了包含四個交替n型及p型矽材料層之高密度低電壓SRAM單元,其通常稱作一「薄電容性耦合閘流體(TCCT)」。如本文所使用,術語「閘流體」意指且包含雙穩態三端子裝置,該雙穩態三端裝置包含包含以一p-n-p-n組態配置之一p型陽極區、一n型基極、一p型基極及一n型陰極區之四層結構。該閘流體可包含兩個主端子、一陽極及一陰極及可附著至最靠近陰極之p型材料之控制端子(通常稱作「閘極」)。與習用SRAM單元相比,以閘流體為基礎之隨機存取記憶體(T-RAM)單元表現出較快切換速度及較低操作電壓。
可藉由施偏壓於該閘極而使一記憶體裝置中之一閘流體接通以使一p-n-p-n通道傳導一電流。一旦該裝置接通(通常稱作「鎖存」),該閘流體就不需要施偏壓於該閘極以維持電流在陰極與陽極之間傳導。反而其將繼續傳導直到一最小吸持電流不再維持於該陽極與陰極之間為止或直到該陽極與陰極之間的電壓反轉為止。因此,該閘流體可用作能夠在一「接通」狀態與一「關斷」狀態之間切換之一
開關或二極體。
參照圖1A,一習用T-RAM單元10包含具有作為雙穩態元件之一垂直環繞閘極14之一垂直閘流體12及形成於矽基板11上之一存取電晶體16。閘流體12包含一陽極區18、一n基極區20、一p基極區22及一陰極區24。T-RAM單元10係由兩個字線存取:用以控制存取電晶體16之一存取閘極之一第一字線26及在寫入操作期間用作第二字線且用以控制垂直閘流體12之切換之閘極14。垂直閘流體12連接至一參考電壓28。閘極14可改良垂直閘流體12之切換速度。一位元線30將T-RAM單元10連接至一感測放大器(未展示)以用於自T-RAM單元10讀取資料或將資料寫入至T-RAM單元10。T-RAM單元10展現在範圍10pA中之一極低的維持電流。
然而,存在與T-RAM單元10相關聯之若干個缺點,包含對可擴展性、控制及整合性之限制。舉例而言,T-RAM單元10受限於難以控制每一閘流體12之尺寸以及難以複製一陣列中之每一閘流體12之尺寸。由於難以按比例調整垂直閘流體12與閘極14,因此難以將T-RAM單元10按比例調整至小於8F2
之面積,其中F係最小特徵大小。此外,形成閘流體12之經摻雜區受可在閘流體12中導致不期望之摻雜劑濃度或分佈之植入製程妨礙。另外,須與任何其他裝置(諸如邏輯裝置)分離地製造T-RAM單元10,這需要額外的製造動作。最後,T-RAM單元10藉助字線26及閘極14之連接可導致串聯(亦即,單元至單元)電阻及裝置故障。
因此,在該技術中所需要的係以閘流體為基礎之記憶體單元以用於形成具有經改良之可擴展性、密度及整合能力之裝置及用於形成以閘流體為基礎之記憶體單元之方法。
本文揭示記憶體單元、包含此等記憶體單元之一半導體裝置及用於形成此等記憶體單元及裝置之方法。此等記憶體單元包含(例如)至少一個閘流體及與該閘流體相關聯之一控制閘極,該至少一個閘流體包含安置於一導電條帶上之垂直疊加之交替經摻雜區。如本文所使用,術語「垂直疊加」意指且包含以其周邊或外表面通常重合之此一方式安置於頂部或位於彼此之上的一(若干種)材料。該導電條帶可提供用於該閘流體之一電連接。該等記憶體單元可具有4F2
之一單元大小(其中F係一最小特徵大小)以提供具有經改良之可擴展性、減小之面積及增加之記憶體單元密度之半導體裝置。根據本發明之各種實施例而形成之該等記憶體單元及裝置可與一個或多個邏輯裝置(諸如一CMOS裝置)整合在一起,且可用於諸如,例如一中央處理單元(CPU)、一晶片上系統(SOC)、感測器、成像器、微機電系統(MEMS)及奈米機電系統(NEMS)之一系統中。提供形成此等記憶體單元及裝置之方法。該等方法可包含能夠控制經摻雜區之形成及該等記憶體單元與裝置之簡化整合之一材料轉移製程。
以下說明提供具體細節(諸如材料類型及處理條件),以提供對本發明之實施例及其實施方案之透徹說明。然而,熟習此項技術者將理解,可在不採用此等具體細節之情形下且結合習用製造技術來實踐本發明之實施例。另外,本文所提供之說明不形成用於製造一半導體裝置或系統之一完整製程流程。本文僅詳細闡述理解本發明之實施例所必需之彼等製程動作及結構。用以根據本發明之實施例形成包含記憶體裝置之一完整系統或積體電路裝置之額外動作可藉由習用技術來執行。
本文所闡述之材料可藉由任一適合技術形成,包含但不限於旋塗、毯覆式塗佈、化學氣相沈積(「CVD」)、電漿增強型化學氣相沈積(「PECVD」)、原子層沈積(「ALD」)、電漿增強型ALD或物理氣相沈積(「PVD」)。另一選擇為,材料可係原位生長。熟習此項技術者可選擇適於沈積或生長一特定材料之一技術。儘管本文中所闡述及圖解說明之材料可作為層而形成,但該等材料並不限於此且可以其他三維組態而形成。
如本文所使用,術語「水平」及「垂直」不管該晶圓或基板之定向如何而界定元件或結構相對於一晶圓或基板之一主平面或表面之相對位置,且係相對於正闡述之結構之定向所闡釋之正交維度,如正參照之圖式中所圖解說明。如本文所使用,術語「垂直」意指且包含與所圖解說明之一基板或晶圓之主表面大致垂直之一維度,且術語「水平」意指與所圖解說明之基板或晶圓之主表面大致平行且在該圖式之左側與右側之間延伸之一維度。如本文所使用,諸如「在...上」、「在...上方」、「在...之上」及「在...下面」之介詞係對應於相對於正闡述之結構之垂直方向之相對術語。
在以下實施方式中,將參照構成本文之一部分之隨附圖式,在該等隨附圖式中以圖解說明方式展示其中可實踐本發明之具體實施例。充分詳細地闡述此等實施例以使熟習此項技術者能夠實踐本發明。然而,可在不背離本發明之範疇的情形下利用其他實施例且可作出結構、邏輯及電方面之改變。本文中所呈現之圖解說明並非意欲作為任一特定系統、邏輯裝置、半導體裝置或記憶體單元之實際視圖,而僅係用以闡述本發明之實施例之理想化表示形式。本文中所呈現之該等圖式未必按比例繪製。另外,圖式之間共同的元件可保留相同數字標記。
圖2A係對一半導體裝置100之一圖解說明,該半導體裝置包含複數個記憶體單元102,每一記憶體單元包含一閘流體104及一相關聯之控制閘極106。半導體裝置100之複數個記憶體單元102可安置於上覆於一電絕緣材料150上之一導電條帶108上,該電絕緣材料亦可表徵為一介電材料。為簡單起見,電絕緣材料150在下文中稱作一絕緣材料150。閘流體104中之每一者可具有一圓柱或柱之一般形狀且可包含一半導體材料,諸如一結晶矽材料、鍺化矽(Si1-x
Gex
)材料、砷化鎵(GaAs)材料或氮化鎵(GaN)材料。閘流體104可各自包含複數個垂直疊加之交替經摻雜區,諸如陰極區116、p基極區114、n基極區112及陽極區110。如本文所使用,術語「交替經摻雜區」及「交替經摻雜半導體區」意指且包含一個接一個連續安置之相反地經摻雜之半導體材料之部分。陽極區110可包含一高摻雜p型矽材料(亦即,一p+材料)。n基極區112可包括一n型矽材料。P基極區114可包含一p型矽材料。陰極區116可包含一高摻雜半導體材料(亦即,一n+材料),諸如一高摻雜鍺化矽材料、一高摻雜砷化鎵材料或一高摻雜氮化鎵材料。如本文所使用,本文所使用之術語「經高度摻雜」意指且包含具有比未高摻雜彼等材料高之一摻雜物濃度之一材料。因此,與p基極區114及n基極區112相比,陽極區110及陰極區116可分別具有一增加的摻雜劑濃度。與習用之水平對準之閘流體相比,閘流體104具有一大致減小之面積。因此,與習用T-RAM單元相比,半導體裝置100之一佔用面積可大致減小。
作為一非限定性實例,記憶體單元102可配置成一陣列,其包含在一第一方向X上延伸之複數個列及在一第二方向Y上延伸之複數個行。圖2A中所展示之半導體裝置100包含三(3)列及四(4)行閘流體104。然而實際上且如所組態,半導體裝置100可包含任一數目個列及行。另外,在第一方向X上對準之閘流體104之列可大致垂直於在第二方向Y上對準之閘流體104之行。半導體裝置100可安置於上覆於一晶圓(未展示)上之絕緣材料150上,該晶圓可包含一習用邏輯裝置,如將詳細闡述。
控制閘極106(亦即,存取線)可各自包含一導電材料且可各自安置於一閘流體104之至少一個側壁上方。一閘極電介質124可安置於控制閘極106與相關聯之閘流體104中之每一者之間。舉例而言,記憶體單元102中之每一者可包含安置於閘流體104之一單個側壁上之閘極電介質124上之一控制閘極106或可包含安置於閘流體104之對置側壁上之控制閘極106。作為一非限定性實例,控制閘極106可在第二方向Y上延伸且可安置於對準成在第二方向Y上延伸之行之閘流體104之側壁中之至少一者上方。控制閘極106或閘極電介質124在存在之情形下可直接接觸閘流體104之p基極區114而不接觸與p基極區114側接之n基極區112或陰極區116。控制閘極106中之每一者可操作性地連接至一電壓源(未展示)以用於施偏壓於半導體裝置100之閘流體104。
導電條帶108中之每一者可包含非晶矽128及一導電材料130且可安置於介電材料150與複數個閘流體104之間。導電條帶108可用作至半導體裝置100之一個或多個閘流體104之陰極區116的一電互連件。如圖2A中所展示,在一些實施例中,導電條帶108可各自在方向X上延伸,從而下伏於該等列中之至少一者上。該列中之閘流體104中之每一者之陰極區116可與導電條帶108中之一下伏導電條帶電耦合。因此,導電條帶108可與控制閘極106大致垂直地對準。導電條帶108中之每一者可包含一互連區132,該互連區可保持曝露以使半導體裝置100能夠與另一裝置(未展示)(諸如一下伏之習用邏輯裝置)電耦合。導電條帶108之垂直表面可與該等列中之一者中之閘流體104之側壁對準。
導電線134可安置於半導體裝置100之複數個記憶體單元102上方。舉例而言,導電線134中之每一者可安置於配置成該等列中之一者之記憶體單元102中之每一者之陽極區110上方且與該陽極區接觸,且可因此用作至陽極區110中之每一者之一電互連件。導電線134中之每一者可(例如)安置於控制閘極106中之一者之上且與其大致垂直。
在半導體裝置100之操作期間,可使用電壓源施偏壓於控制閘極106以便形成一損耗基極區,從而提供自閘流體104中之每一者之陰極區116流動至陽極區110之電流。導電線134可各自用作一資料/感測線(亦即,位元線)且在半導體裝置100之操作期間可形成電耦合半導體裝置100之記憶體單元102之一正向偏壓。導電條帶108可用作至記憶體單元102中之每一者之陰極區116的電接觸件。
圖2B係圖2A中所展示之半導體裝置100之一部分之一電圖。記憶體單元102安置成複數個列118及行120且各自包含一閘流體104及一控制閘極106。控制閘極106中之每一者電耦合至列118中之一者中之閘流體104且導電條帶108及導電線134中之每一者電耦合至行120中之一者中之閘流體104。
圖3A係對除了閘流體104之垂直疊加之經摻雜區之次序之外與圖2A中所展示之半導體裝置100具有大致相同組態之一半導體裝置200之一圖解說明。舉例而言,可相對於圖2A中所展示之彼等閘流體而反轉閘流體104中之每一者以使陽極區110安置於導電條帶108中之一者上,n基極區112安置於陽極區110上方,p基極區114安置於n基極區112與陰極區116之間。記憶體單元102可配置成包含在一第一方向X上延伸之複數個列及在一第二方向Y上延伸之複數個行之一陣列,如相對於圖2A所闡述。半導體裝置200之控制閘極106可沿閘流體104之p基極區114而安置。
控制閘極106中之每一者可操作性地連接至一電壓源(未展示)以用於施偏壓於半導體裝置200之記憶體單元102。在半導體裝置200之操作期間,可將一電壓施加至可用作陰極之導電線134同時導電條帶108可各自用作一資料/感測線(亦即,位元線)且可形成電耦合半導體裝置200之記憶體單元102之一正向偏壓。
圖3B係圖3A中所展示之半導體裝置200之一部分之一電圖。記憶體單元102安置成複數個列118及行120且各自包含一閘流體104及一控制閘極106。控制閘極106中之每一者電耦合至列118中之一者中之閘流體104且導電條帶108及導電線134中之每一者電耦合至行120中之一者中之閘流體104。
圖4係圖2A到3B中所展示之半導體裝置100及200之一部分之一不完整自上而下視圖。控制閘極106在列中橫向延伸且導電線134在行中於其上方垂直延伸。在圖2A及2B中所展示之半導體裝置100中,導電線134上覆於包括一p型結晶矽材料之一經摻雜區(未展示)上。在圖3A及3B中所展示之半導體裝置200中,導電線134上覆於包括一n型結晶矽材料之一經摻雜區(未展示)上。記憶體單元102中之每一者具有4F2
之一單元大小。4F2
單元大小係藉由在半導體裝置100之操作期間將導電條帶108提供為一陰極或位元線而達成。
參照圖5至圖15,現在將闡述形成包含複數個記憶體單元102之半導體裝置100及200之一方法,每一記憶體單元包含一閘流體104(諸如圖2A到圖4中所展示之彼等閘流體),其中相同元件係由相同編號標記。可形成包含一基板138之一施體晶圓136,該基板上形成有一經摻雜材料140、導電材料130及非晶矽128。基板138可包含一製造基板,諸如半導體材料(例如矽、鍺化矽、砷化鎵、磷化銦等)之一全或部分晶圓、一全或部分絕緣體上矽(SOI)型基板(諸如玻璃上矽(SOG)、陶瓷上矽(SOC)或藍寶石上矽(SOS)基板)或任一其他已知適合的製造基板。如本文中所使用,術語「晶圓」包含習用晶圓以及其他塊狀半導體基板。在一項實施例中,基板138可包含一結晶矽材料。基板138可經摻雜或未經摻雜。在一項實施例中,可用p型雜質摻雜基板138以形成可用以形成圖2A中所展示之半導體裝置100之一p型矽材料。在另一實施例中,可用一n型雜質摻雜基板138以形成可用以形成圖3A中所展示之半導體裝置200之一n型矽材料。
如相對於圖2A及3A所闡述,經摻雜材料140(圖5)可包含可用以形成圖2A中所展示之半導體裝置100之陰極區116之一高摻雜n型材料或可用以形成圖3A中所展示之半導體裝置200之陽極區110之一高摻雜p型材料,如將進一步詳細闡述。可藉由在基板138上執行一習用離子植入來形成經摻雜材料140。在一項實施例中,可藉由將一n型雜質(諸如砷(As)、磷(P)或銻(Sb))之離子植入至基板138中而使經摻雜材料140經形成以包含一高摻雜n型矽材料(亦即,n+材料)。包含n+材料之經摻雜材料140可用以形成圖2A中所展示之半導體裝置100之陰極區116,如將進一步詳細闡述。在另一實施例中,可藉由將一p型雜質(諸如硼(B))之離子植入至基板138中而使經摻雜材料140經形成以包含一高摻雜p型矽材料(亦即,p+材料)。包含p+材料之經摻雜材料140可用以形成圖3A中所展示之半導體裝置200之陽極區110,如將進一步詳細闡述。可在導電材料130及非晶矽128已形成於施體晶圓136上之前或之後形成經摻雜材料140。在另一實施例中,可藉由在基板138上磊晶生長或沈積經摻雜之鍺化矽、經摻雜之砷化鎵或經摻雜之氮化鎵而形成經摻雜材料140以改良行動性且提供對摻雜劑在經摻雜材料140中擴散之較佳控制。
導電材料130可係一低電阻率材料,其包含但不限於一相變材料、鈦、矽化鈦、氧化鈦、氮化鈦、坦、矽化坦、氧化坦、氮化坦、鎢、矽化鎢、氧化鎢、氮化鎢、其他金屬、金屬矽化物、金屬氧化物或金屬氮化物材料或其組合,包含多個不同的導電材料。在一項實施例中,導電材料130可係由氮化鈦形成,此乃因氮化鈦對許多材料(諸如用作基板138之材料)具有良好黏附或黏附性。氮化鈦亦具有使其不受高處理溫度影響之一高熔點(約3000℃)。氮化鈦亦與其他導電材料有極佳的歐姆接觸。氮化鈦亦通用於半導體製造中,且因此可輕易併入至習用製造製程中。在一項實施例中,導電材料130係一富含鈦之氮化鈦,諸如氮化鈦金屬模式(MMTiN)。導電材料130亦可係由多種導電材料形成。在另一實施例中,導電材料130可係由一金屬(諸如,鈦、鎢或鋁)形成,其中其上形成氮化鈦材料層。可端視於該材料來最佳化導電材料130之厚度以提供一低歐姆接觸。舉例而言,若導電材料130係氮化鈦(諸如MMTiN),則導電材料130可具有自約10 nm至約50 nm之一厚度。可藉助此項技術中習知之一沈積技術(諸如,例如原子層沈積(ALD)、化學氣相沈積(CVD)或電漿氣相沈積(PVD))來形成導電材料130。
可藉助此項技術中習知之一沈積技術(諸如,例如ALD、CVD或PVD)在導電材料130上方形成非晶矽128。在一項實施例中,可藉助PVD後跟化學-機械平坦化(CMP)在導電材料130上形成非晶矽128。非晶矽128之厚度可係自約10 nm至約80 nm。
施體晶圓136亦可包含藉由使一原子物質植入至基板138中而形成之一轉移區146。原子物質可係氫離子、稀有氣體離子(亦稱作惰性或不活躍氣體)或氟離子。原子物質可植入至施體晶圓136之基板138中以形成一經植入地帶148(在圖5中由虛線表示)。原子物質可在導電材料130或非晶矽128形成於基板138上之前或之後植入至基板138中。經植入地帶148可於一期望深度處形成於基板138中,這相依於此項技術中習知之諸如原子物質之植入劑量及能量之參數。可基於圖2A及3A中所展示之閘流體104之一期望厚度來控制經植入地帶148之深度。經植入地帶148可包含包含經植入原子物質之微泡或微腔,這在基板138內提供一弱化區。可在植入受影響之一溫度之上但在導電材料130之融化溫度之下的一溫度時對施體晶圓136進行熱處理以影響施體晶圓136中之結晶重排及微泡或微腔之聚結。如下文所闡述,施體晶圓136可在經植入地帶148處裂開以形成圖6中所展示之一半導體結構172'。
如圖6中所展示,施體晶圓136可疊加至上覆於一受體晶圓152上之絕緣材料150上以使施體晶圓136之非晶矽128與絕緣材料150接觸。為了形成受體晶圓152,可使用此項技術中習知之一習用沈積技術(諸如,例如ALD、CVD或PVD)使絕緣材料150形成於一塊狀基板154上方。舉例而言,塊狀基板154可包含矽基板。一至少經部分製造之習用邏輯裝置(諸如一互補金屬氧化物半導體(CMOS)裝置156)可視需要形成於塊狀基板154上且可藉助習用技術形成。舉例而言,CMOS裝置156可包含安置於塊狀基板154中之源極區160與汲極基極區162之間的一場效應電晶體(FET)陣列。FET 158中之每一者可包含安置於間隔件166之間的一閘極電介質163及一閘極電極164。一介電材料168可視需要形成於塊狀基板154與FET 158中之每一者之閘極電極164之間。CMOS裝置156可進一步包含互連FET 158之複數個線互連件170。
然後施體晶圓136之非晶矽128可藉由曝露至熱而接合至受體晶圓152之絕緣材料150。在施體晶圓136接合至受體晶圓152之前,可視需要對非晶矽128之一表面及絕緣材料150之一表面中之至少一者進行處理以改良其間之接合強度。此等處理技術在此項技術中習知且可包含(例如)化學活化、電漿活化或植入活化。舉例而言,可用一稀釋的氫氧化氨溶液或氟化氫溶液來處理絕緣材料150之表面。非晶矽128之表面亦可曝露至(例如)氬電漿以形成一電漿活性表面。非晶矽128之表面及絕緣材料150之表面中之至少一者活化可由於形成於非晶矽128之表面及絕緣材料150之表面上之離子物質(例如,氫)之行動性增加而使其間之後續接合之動力增加。
仍參照圖6,施體晶圓136之非晶矽128可與受體晶圓152之絕緣材料150接觸且接合以形成一半導體結構172'。舉例而言,可藉由將半導體結構172'加熱至小於約600℃(諸如自約300℃至約400℃)之一溫度而使非晶矽128接合至絕緣材料150。若絕緣材料150係由二氧化矽形成,則可在非晶矽128與絕緣材料150之間形成氧化矽接合。由於導電材料130可係由一金屬或且他熱敏材料形成,因此半導體結構172'
曝露至的溫度可小於導電材料130之熔點。非晶矽128與絕緣材料150亦可在沒有熱之情形下(諸如在室溫時(自約20℃至約25℃))接合。亦可對施體晶圓136及受體晶圓152施加壓力以使非晶矽128接合至絕緣材料150。一旦施體晶圓136接合至受體晶圓152,來自施體晶圓136之導電材料130就可形成安置於絕緣材料150與基板138之間的一掩埋式導電材料。
然後可自基板138移除轉移區146以形成圖7中所展示之半導體結構172。可藉助此項技術中習知之技術來移除轉移區146,諸如藉由對經植入地帶148(圖6)施加一剪切力或藉由在經植入地帶148處施加熱或一噴氣流。植入於經植入地帶148中之氫或其他離子在基板138中生成易受裂開影響之一弱化區。基板138'之剩餘部分可具有(例如)自約50nm至約30nm(自約500Å至約3000Å)之一厚度。在使轉移區146與基板138'之剩餘部分分離之後,基板138'之一曝露表面176可不期望地粗糙。可使基板138'之曝露表面176平滑以促進根據此項技術中習知之技術所闡述之進一步處理(諸如,例如研磨、濕式蝕刻及化學機械拋光(CMP)中之一者或多者)。
可藉助SMART-CUT®
層轉移技術之修改形式來形成半導體結構172。SMART-CUT®
層轉移技術詳細闡述於(例如)頒予Bruel之美國專利第RE 39,484號、頒予Aspar等人之美國專利第6,303,468號、頒予Aspar等人之美國專利第6,335,258號、頒予Moriceau等人之美國專利第6,756,286號、頒予Aspar等人之美國專利第6,809,044號、頒予Aspar等人之美國專利第6,946,365號及頒予Dupont之美國專利申請公開案第2006/0099776號。然而,若維持足夠低的製程溫度,則亦可使用適用於製造具有一掩埋式導電材料之一
半導體結構之其他製程。在SMART-CUT®
層轉移技術之習用實施方案中,使用一高溫退火而將施體晶圓與受體晶圓接合在一起。用以接合施體晶圓與受體晶圓之溫度係自約1000℃至約1300℃。然而,由於在本文中所闡述之半導體結構中存在導電材料130,因此本發明之半導體結構將不能承受曝露至此等溫度下而不受到熱損壞。因此,如上文所闡述,可使用較低溫度來接合一受體晶圓152與施體晶圓136。用於形成半導體結構172之實例性方法詳細闡述於在2010年3月2日提出申請且標題為「SILICON-METAL-ON-INSULATOR STRUCTURES,METHODS OF FORMING SUCH STRUCTURES,AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES」之美國專利申請案第12/715,704號。儘管圖6及圖7圖解說明形成半導體結構172之一方法之一項實施例,但可利用美國專利申請案第12/715,704號中所闡述之方法中之任一者或其他習知方法來形成半導體結構172。
參照圖8,可移除基板138'
、經摻雜材料140、導電材料130及非晶矽128之部分以形成導電條帶108,該等導電條帶中之每一者可用作圖2A中所展示之半導體裝置100中之一陰極互連件或圖3A中所展示之半導體裝置200中之一位元線。藉助相對於圖5到圖7所闡述之接合及材料轉移製程形成包含掩埋式導電材料130之半導體結構172使得能夠形成導電條帶108,使用一習用矽晶圓或一習用絕緣體上矽(SOI)結構不可達成此結果。為簡化起見,自剩餘圖中已省略了圖6及圖7中下伏於絕緣材料150上之受體晶圓152。可藉由在基板138'上方沈積一遮罩材料(未展示)且圖案化該遮罩材料以形成基板138'之表面透過其曝露之開孔來形成導電條帶108。該遮罩材料可包含(例如)一光阻劑材料、一氧化物材料、透明碳或非晶碳。此項技術中已知形成且圖案化該遮罩材料之方法,因此本文未詳細闡述該等方法。可移除基板138'、經摻雜材料140、導電材料130及非晶矽128之透過遮罩材料中之開孔而曝露之部分以形成基板138'、經摻雜材料140、導電材料130及非晶矽128中之每一者之剩餘部分之間的溝渠178。然後可移除該遮罩材料之剩餘部分。
藉助非限定性實例,溝渠178可經形成以在第一方向X上透過基板138'、經摻雜材料140、導電材料130及非晶矽128中之每一者延伸。可使用(例如)一各向異性反應離子(亦即,電漿)蝕刻製程來移除基板138'、經摻雜材料140、導電材料130及非晶矽128之部分以曝露下伏絕緣材料150。舉例而言,若基板138'及經摻雜材料140各自係由一經摻雜結晶矽材料形成,則可執行使用氧(O2
)氣、四氟化碳(CF4
)氣及溴化氫(HBr)氣之一反應離子蝕刻(RIE)製程來選擇性地移除對遮罩材料及絕緣材料150具有選擇性的經摻雜矽材料之部分。若導電材料130係由氮化鈦或矽化鎢形成,則可使用一含溴氣體與一含氟氣體或一含氟氣體與一含氯氣體之一混合物來移除對該遮罩材料及絕緣材料150具有選擇性之氮化鈦及非晶矽材料。
如圖9中所展示,可在半導體結構172上方形成一填充材料180。藉助非限定性實例,填充材料180可包含諸如氧化物材料、氮化物材料或一玻璃上旋塗(SOG)材料之一介電材料且可使用一化學氣相沈積製程使其沈積。在形成填充材料180之後,可使用一化學-機械拋光(CMP)製程來移除其部分以使半導體結構172之一上表面174大致平坦。
圖10展示在已移除基板138'及經摻雜材料140(圖9)之部分以形成複數個柱182且曝露導電條帶108之互連區132之後的半導體結構172。在剩餘圖中,為簡化及澄清圖解說明起見已省略了填充材料180。該等柱中之每一者包含基板138"及經摻雜材料140'之一剩餘部分。在一項實施例中(圖10中所展示),柱182可各自包含一陰極區116及一p基極區114以形成圖2A中所展示之半導體裝置100之閘流體104中之一者。在另一實施例中(未展示),柱182中之每一者可包含陽極區110及n基極區112以形成圖3A中所展示之半導體裝置200之閘流體104。可藉由在半導體結構172上方沈積一遮罩材料(未展示)且圖案化該遮罩材料以形成基板138'之表面透過其曝露之開孔來形成柱182。視需要,填充材料180(圖9)之表面可透過該遮罩材料而曝露。該遮罩材料可包含(例如)一光阻劑材料、氧化物材料、透明碳或非晶碳。此項技術中已知形成且圖案化該遮罩材料之方法,因此本文中未詳細闡述該等方法。可移除基板138'及經摻雜材料140之透過該遮罩材料中之開孔而曝露之部分以形成柱182且曝露導電條帶108之互連區132。舉例而言,若基板138'
及經摻雜材料140各自係由一經摻雜結晶矽形成,則可執行一反應離子蝕刻(RIE)製程以選擇性地移除該經摻雜結晶矽之部分而不自導電條帶108移除導電材料130。柱182中之每一者可經形成以具有自約2:1至約20:1且更特定而言自約3:1至約10:1之一縱橫比。藉由完全移除經摻雜材料140(圖9)以曝露其間導電材料130之表面來形成圖10中所展示之柱182。如所組態,可藉由僅移除基板138'(圖9)或其一部分而形成柱182以使經摻雜材料140之至少一部分保留於導電條帶108上方,如虛線所展示。
在形成垂直閘流體12之習用方法(諸如圖1A中所展示之方法)中,藉由習用摻雜製程來形成陰極區24,其中將摻雜劑自垂直閘流體12之上表面植入至陰極區24。此等摻雜製程通常造成摻雜劑或雜質之一不期望之濃度或分佈,且因此不利於將摻雜劑或雜質引入至材料之實質深度(諸如圖1A中所展示之垂直閘流體12之陰極區24)。相反,相對於圖5到圖7所闡述之接合及材料轉移製程在材料轉移之前達成基板138、138'及經摻雜材料140之摻雜。因此,實質性地改良基板138、138'及經摻雜材料140之品質,諸如摻雜劑濃度或分佈之均勻性。由於可在形成柱182之前摻雜基板138、138'及經摻雜材料140,因此本發明之方法達成對圖2A中所展示之半導體裝置100之陰極區116及p基極區114以及圖3A中所展示之半導體裝置200之陽極區110及n基極區112之摻雜濃度之控制及最佳化。
柱182可形成一陣列,該陣列包含其中柱182在第一方向
X上對準之複數個列及其中柱182在第二方向Y上對準之複數個行。可移除基板138'及經摻雜材料140以使互連區132具有可有利於導電條帶108與下伏或上覆半導體結構(未展示)電互連之一交錯組態。
圖11A到圖11C圖解說明在柱182上形成控制閘極106之一方法之一實施例且其係圖10中所展示之半導體結構172在一閘極介電材料184及一導電材料186已沈積於半導體裝置172上方之後的透視圖。圖11A圖解說明具有沈積於柱182之間的填充材料180之半導體裝置172。如圖11B中所展示,可在半導體結構172上方保形形成一閘極介電材料184及一導電材料186。藉助非限定性實例,閘極介電材料184可係使用(例如)一化學氣相沈積製程、一熱氧化製程或其一組合而形成之氧化物材料或氮化物材料。然後可在閘極介電材料184上方形成導電材料186。作為一非限定性實例,導電材料186可係由氮化鈦、氮化鉈、鎢或鋁形成且可使用一化學氣相沈積製程使其沈積。可在導電材料186上方沈積具有約50Å與100Å之間的一厚度之一襯墊材料(未展示)(諸如多晶矽材料)。參照圖11C,可執行各向異性幹性蝕刻製程以移除該襯墊及導電材料186之部分以形成上覆於導電材料186之剩餘部分上之襯墊材料之間隔件(未展示)。將該等間隔件用作一硬遮罩,可執行使用(例如)氫氧化氨(NH4
OH)、過氧化氫(H2
O2
)及去離子水之一濕式蝕刻製程來底切導電材料186以形成圖12中所展示之控制閘極106。然後可移除該等間隔件。舉例而言,若該等間隔件包括多晶矽,則可使用使用四甲基氫氧化氨(TMAH)之一濕式蝕刻製程來移除對控制閘極106及閘極電介質124具有選擇性之多晶矽材料。可使用此項技術中習知之任一其他技術來形成控制閘極106及閘極電介質124。
在圖11A到圖11C中所展示之實施例中,在柱182之兩(2)個表面上形成控制閘極106。然而,亦可在柱182之一單個側上形成控制閘極106。舉例而言,在形成控制閘極106之後,可在半導體結構172上方沈積一遮罩材料(未展示)且將其圖案化以形成柱182之一個側上之控制閘極106之表面透過其曝露之複數個開孔。可執行一習用蝕刻製程來移除控制閘極106中之每一者之曝露部分以使控制閘極106保留在柱182之一單個側上。
如圖12中所展示,可視需要對控制閘極106具有選擇性地移除閘極電介質124。可使一摻雜劑或雜質植入柱182中之每一者之一上部區以形成圖2A中所展示之半導體裝置100之n基極區112,或圖3A中所展示之半導體裝置200之p基極區114。可使用習用方法(諸如一離子植入製程或一高溫擴散製程)來摻雜柱182之曝露部分。在一項實施例中,可藉由使半導體裝置172曝露至一n型摻雜劑(諸如含磷或含砷)來形成圖2A中所展示之半導體裝置100之閘流體104之n基極區112以便形成一n型材料。在另一實施例中,可藉由使半導體裝置172曝露至一p型摻雜劑(諸如含硼或含鋁)來形成圖3A中所展示之半導體裝置200之閘流體104之p基極區114以便形成一p型材料。作為另一實例,可在柱182之曝露表面上方沈積一高摻雜p型材料或一高摻雜n型材料之一薄膜(未展示)且可執行一熱退火,期間摻雜劑自高摻雜p型材料或高摻雜n型材料移至柱182中從而生成期望之經摻雜材料(亦即,圖2A中所展示之n基極區112或圖3A中所展示之p基極區114)。
如圖13中所展示,可使一摻雜劑或雜質植入柱182中之每一者之一上部區以形成圖2A中所展示之半導體裝置100之陽極區110,或圖3A中所展示之半導體裝置200之陰極區116。如相對於圖12所闡述,可使用習用方法來摻雜柱182之曝露部分。在一項實施例中,可藉由使半導體裝置172曝露至一p型摻雜劑或藉由在柱182之曝露表面上沈積一高摻雜p型材料且執行一熱退火來形成圖2A中所展示之半導體裝置100之陽極區110以便形成高摻雜p型材料。在另一實施例中,在一項實施例中,可藉由使半導體裝置172曝露至一n型摻雜劑或藉由在柱182之曝露表面上沈積一高摻雜n型材料且執行一熱退火來形成圖3A中所展示之半導體裝置200之陰極區116以便形成高摻雜p型材料。
儘管上文圖解說在圖5中所展示之動作之後執行圖2A中所展示之半導體裝置100之陽極區110及n基極區112或圖3A中所展示之半導體裝置200之陰極區116及p基極區114之形成,但亦可在藉由相對於圖5到圖7所闡述之接合及材料轉移製程形成半導體結構172之前形成此等區。如圖14中所展示,可形成具有類似於圖5中所展示之施體晶圓136之一結構之一施體晶圓136',且該施體晶圓可額外包含一第一材料142及一第二材料144。可藉助一習用摻雜製程形成第一材料142及一第二材料144,可藉由使施體晶圓136'之一第一主表面188或一第二主表面190曝露至一摻雜劑或雜質來執行該習用摻雜製程。在一項實施例中,基板138可包含一高摻雜n型材料,第一材料142可包含一p型材料,第二材料144可包含一n型材料且經摻雜材料140可包含一高摻雜p型材料以便在如相對於圖10所闡述形成柱182時形成圖2A中所展示之半導體裝置100之閘流體104。在另一實施例中,基板138可包含一高摻雜p型材料,第一材料142可包含一n型材料,第二材料144可包含一p型材料且經摻雜材料140可包含一高摻雜n型材料以便在如相對於圖10所闡述形成柱182時形成圖3A中所展示之半導體裝置200之閘流體104。因此在相對於圖5到圖7所闡述之接合及材料轉移製程之前摻雜基板138使得其中之摻雜劑之濃度及分佈能夠得以控制並最佳化。
在使用及操作期間,可將一電壓施加至控制閘極106,從而致使一電流自圖2A到圖3B中所展示之閘流體104之陰極區116流動至陽極區110。在形成控制閘極106期間,可發生控制閘極106與閘流體104之相關聯之p基極區114之間的重疊。此重疊可在完整裝置之操作期間形成電容且增加洩露電流從而限制該陣列之密度。因此,可形成p基極區114及相關聯之控制閘極106以最小化控制閘極106與陰極區116之重疊以及n基極區112側接p基極區114。舉例而言,可使用(例如)一習用電漿蝕刻製程來移除在p基極區114之上延伸之控制閘極106之部分以使控制閘極106不延伸超過p基極區114與陰極區116及n基極區112中之每一者之間的介面。
重新參照圖2A及圖3A,可在閘流體104上方並以與該閘流體接觸地形成導電線134以形成半導體裝置100及200。可藉由沈積一導電材料且圖案化該導電材料來形成導電線134以形成在第一方向X上延伸之大致垂直於控制閘極106之導電線。在一項實施例中,可使用一習用鑲嵌或減性製程來形成導電線134。舉例而言,可在半導體結構172(圖12)上方形成一導電材料(未展示)且可透過一光阻劑材料中之開孔移除其部分以界定導電線134。在另一實施例中,可使用一習用微影製程來形成導電線134。舉例而言,可在半導體結構172上方沈積一犧牲介電材料(未展示)且可使用一習用微影製程在其中形成一溝渠圖案(未展示)。該等溝渠中之每一者可形成於導電線134欲形成之位置中。可在半導體結構172上方沈積一導電材料以填充該等溝渠且可使用一化學-機械拋光製程來移除上覆於介電材料上之導電材料之一部分以形成導電線134。
此外,在形成分別在圖2A及圖3A中所展示之半導體裝置100及200中之一者之後,可重複圖5至圖13中所展示之方法以形成包含複數個垂直堆疊之半導體裝置、記憶體或邏輯且具有增加之記憶體密度之一多層級半導體裝置。
如先前所闡述,導電線134在圖2A及圖2B中所展示之半導體裝置100之操作期間用作資料線(亦即,位元線)且在圖3A及圖3B中所展示之半導體裝置200之操作期間用作陰極。
圖15圖解說明根據本文所闡述之一個或多項實施例所實施之一電子系統300之一簡化方塊圖。電子系統300包含至少一個輸入裝置302、至少一個輸出裝置304、一記憶體存取裝置(諸如一個或多個處理器306)及一個或多個記憶體裝置308。記憶體裝置308包含併入本文所闡述之裝置或方法之至少一項實施例之至少一個半導體記憶體310。電子系統300可係若干個計算、處理及消費產品之部分。作為非限定性實例,此等產品中之一些可包含個人電腦、手持式裝置、相機、電話、無線裝置、顯示器、晶片組、機頂盒、遊戲及車輛。
在一些實施例中,本發明包含記憶體單元,其包含安置於一基板上方之一導電條帶、安置於該導電條帶上且包含複數個交替經摻雜之垂直疊加半導體區之一閘流體及安置於該閘流體之該複數個交替經摻雜之垂直疊加半導體區中之一者上之一控制閘極。安置於一基板上方之導電條帶可包含上覆於非晶矽上之一導電材料。該導電條帶之至少兩個側壁可與該閘流體之側壁對準。該閘流體可包含垂直疊加於彼此上方之一陰極區、一p基極區、一n基極區及一陽極區。該控制閘極可安置於該n型矽之曝露側壁上。該控制閘極可操作性地耦合至一電壓源。該記憶體單元可具有4F2
之一單元大小。
在額外實施例中,本發明包含半導體裝置,其包含至少一個導電條帶、安置於該至少一個導電條帶上之複數個記憶體單元及與該複數個記憶體單元之至少一部分電耦合之一資料線。該複數個記憶體單元中之每一者可包含包括複數個交替經摻雜之垂直疊加半導體區之一閘流體及與該閘流體相關聯之一控制閘極。該複數個記憶體單元中之每一者可具有4F2
之一單元大小。該至少一個導電條帶可安置於一電絕緣材料上,該電絕緣材料上覆於形成於一晶圓上之一邏輯裝置上。該閘流體包含形成三個半導體結之交替摻雜劑型之四個經摻雜區。該複數個記憶體單元可對準成在一第一方向上延伸之複數個列且對準成在垂直於該第一方向之一第二方向上延伸之複數個行以形成一陣列。該複數個記憶體單元中之每一者之該閘流體包括安置於該至少一個導電條帶上之一高摻雜n型區、安置於該高摻雜n型區上之一p型區、安置於該p型區上之一n型區及安置於該n型區上之一高摻雜p型區。
在另外之實施例中,本發明包含一記憶體陣列,其包含一記憶體單元陣列,該記憶體單元陣列包含大致對準成一第一方向上之複數個列及垂直於該第一方向之一第二方向上之複數個行之複數個閘流體,該複數個閘流體中之每一者包括複數個垂直疊加之交替地經摻雜半導體區及與該複數個行中之至少一者中之該複數個閘流體中之每一者之該複數個垂直疊加之交替地經摻雜半導體區中之一者電耦合之至少一個控制閘極。該記憶體單元進一步包含複數個導電條帶,每一者與對準成該複數個列中之一者之該複數個閘流體中之每一者電耦合。該至少一個控制閘極可安置於對準成複數個行中之一者之該複數個閘流體中之每一者之至少一個側壁上。該記憶體單元陣列之該複數個列中之一者中之該複數個閘流體中之每一者可安置於該複數個導電條帶中之一者上。另外,該複數個導電線可安置於對準成該複數個列中之一者之該等閘流體上方並與該等閘流體對準。該記憶體陣列可進一步包含電耦合至該複數個導電條帶中之至少一者之至少一個邏輯裝置。
在又另外之實施例中,本發明包含形成一半導體裝置之一方法。該方法包含形成包括上覆於一電絕緣材料上之非晶矽、上覆於該非晶矽上之一導電材料、上覆於該導電材料上之一經摻雜材料及上覆於該經摻雜材料上之一經摻雜結晶矽之一半導體結構,移除該經摻雜結晶矽、該經摻雜材料、該導電材料及該非晶矽中之每一者之部分以形成曝露該電絕緣材料之複數個通道、移除該經摻雜結晶矽及該經摻雜材料之部分以形成各自包含一第一經摻雜區及相對於該第一經摻雜區相反地經摻雜之一第二經摻雜區之複數個柱,在該複數個柱中之每一者之至少一個表面上形成一控制閘極,將該複數個柱曝露至一第一摻雜劑以形成相對於該第二經摻雜區相反地經摻雜之一第三經摻雜區且將該複數個柱曝露至一第二摻雜劑以形成一第四經摻雜區。該等方法可進一步包含在該複數個柱中之每一者之該第四經摻雜區上方且以與該第四經摻雜區接觸地形成一導電線。可藉由形成包括上覆於該導電材料上之該非晶矽之一施體晶圓(該導電材料上覆於安置於一結晶矽晶圓上之該經摻雜材料上)、將離子植入至該結晶矽晶圓中一預定深度、將該施體晶圓之非晶矽附著至一受體晶圓上之電絕緣材料且分離該施體晶圓之一部分以留下該結晶矽晶圓、該經摻雜材料、該導電材料及該非晶矽之一部分上覆於該受體晶圓之電絕緣材料之一表面上來形成該半導體結構。該半導體結構可包含形成於上覆於該電絕緣材料上之一晶圓上之一邏輯裝置。
在又另外之實施例中,本發明包含一系統,該系統包含至少記憶體存取裝置及操作性地耦合至該至少一個記憶體存取裝置之至少一個半導體裝置。該至少一個半導體裝置可包含至少一個導電條帶、安置於該至少一個導電條帶上之複數個記憶體單元及與該複數個記憶體單元之至少一部分電耦合之一資料線。該複數個記憶體單元中之每一者可包含一閘流體及與該閘流體相關聯之一控制閘極。該等閘流體可各自包含複數個垂直疊加之交替地經摻雜半導體區。該系統之該複數個記憶體單元中之每一者可具有4F2
之一單元大小。
儘管已根據某些所圖解說明之實施例及其變化形式闡述了本發明,但熟習此項技術者將理解及瞭解本發明並非具有限制性。而是,可在不背離如以下申請專利範圍所界定之本發明範疇及其法定等效範圍之情形下實行對所圖解說明之實施例的添加、刪除及修改。
10‧‧‧以閘流體為基礎之隨機存取記憶體單元
11‧‧‧矽基板
12‧‧‧垂直閘流體
14‧‧‧垂直環繞閘極
16‧‧‧存取電晶體
18‧‧‧陽極區
20‧‧‧n基極區
22‧‧‧p基極區
24‧‧‧陰極區
26‧‧‧第一字線
28‧‧‧參考電壓
30‧‧‧位元線
100‧‧‧半導體裝置
102‧‧‧記憶體單元
104‧‧‧閘流體
106‧‧‧控制閘極
108‧‧‧導電條帶
110‧‧‧陽極區
112‧‧‧n基極區
114‧‧‧p基極區
116‧‧‧陰極區
118‧‧‧列
120‧‧‧行
124‧‧‧閘極電介質
128‧‧‧非晶矽
130‧‧‧導電材料
132‧‧‧互連區
134‧‧‧導電線
136‧‧‧施體晶圓
136'‧‧‧施體晶圓
138...基板
138'...基板
138"...基板
140...經摻雜材料
140'...經摻雜材料
142...第一材料
144...第二材料
146...轉移區
148...經植入地帶
150...電絕緣材料
152...受體晶圓
154...塊狀基板
156...互補金屬氧化物半導體(CMOS)裝置
158...場效應電晶體
160...源極區
162...汲極基極區
163...閘極電介質
164...閘極電極
166...間隔件
168...介電材料
170...線互連件
172...半導體結構
172'...半導體結構
176...曝露表面
178...溝渠
180...填充材料
182...柱
184...閘極介電材料
186...導電材料
188...第一主表面
190...第二主表面
200...半導體裝置
300...電子系統
302...輸入裝置
304...輸出裝置
306...處理器
308...記憶體裝置
310...半導體記憶體
圖1A圖解說明根據先前技術之一T-RAM單元之一剖面視圖;圖2A圖解說明根據本發明之一實施例之一半導體裝置之一部分之一透視圖;圖2B圖解說明表示圖2A中所圖解說明之半導體裝置之部分之一電路圖;圖3A圖解說明根據本發明之一實施例之另一半導體裝置之一部分之一透視圖;圖3B圖解說明表示圖3A中所圖解說明之另一半導體裝置之部分之一電路圖;圖4圖解說明圖2A及2B中所圖解說明之根據本發明之實施例之一半導體裝置之部分之一自上而下平面視圖;圖5到圖14圖解說明根據本發明之實施例在各個製造階段期間一半導體結構之一部分之透視圖及剖視圖;及圖15圖解說明根據本發明之本文所闡述之一個或多項實施例而實施之一系統之一簡化方塊圖。
100‧‧‧半導體裝置
102‧‧‧記憶體單元
104‧‧‧閘流體
106‧‧‧控制閘極
108‧‧‧導電條帶
110‧‧‧陽極區
112‧‧‧n基極區
114‧‧‧p基極區
116‧‧‧陰極區
124‧‧‧閘極電介質
128‧‧‧非晶矽
130‧‧‧導電材料
132‧‧‧互連區
134‧‧‧導電線
150‧‧‧電絕緣材料
Claims (33)
- 一種記憶體單元,其包括:一導電條帶,其安置於一基板上方,該導電條帶包括上覆於非晶矽上之一導電材料,該非晶矽安置於上覆於該基板上之一電絕緣材料上;一閘流體,其安置於該導電條帶上方且包括複數個交替經摻雜之垂直疊加半導體區;及一控制閘極,其安置於該閘流體之該複數個交替經摻雜之垂直疊加半導體區中之一者上。
- 如請求項1之記憶體單元,其中該導電材料包含一導電含金屬材料或一導電含金屬化合物材料。
- 如請求項1之記憶體單元,其中該導電條帶之至少兩個垂直表面與該閘流體之側壁對準。
- 如請求項1之記憶體單元,其中該閘流體包括垂直地疊加於彼此上方之一陰極區、一p基極區、一n基極區及一陽極區。
- 如請求項4之記憶體單元,其中該控制閘極安置於該n基極區之曝露側壁上。
- 如請求項1之記憶體單元,其中該控制閘極可操作地耦合至一電壓源。
- 如請求項1之記憶體單元,其中該記憶體單元之一單元大小係4F2 。
- 一種半導體裝置,其包括:在一基板之上之至少一個導電條帶,該導電條帶包括 上覆於非晶矽上之一導電材料,該非晶矽安置於上覆於該基板上之一電絕緣材料上;安置於該至少一個導電條帶上之複數個記憶體單元,該複數個記憶體單元中之每一者包括:一閘流體,其包括複數個交替經摻雜之垂直疊加半導體區;及一控制閘極,其與該閘流體相關聯;及一資料線,其與該複數個記憶體單元之至少一部分電耦合。
- 如請求項8之半導體裝置,其中該複數個記憶體單元中之每一者具有4F2 之一單元大小。
- 如請求項8之半導體裝置,其中該至少一個導電條帶上覆於一邏輯裝置上。
- 如請求項8之半導體裝置,其中該複數個記憶體單元包括對準成在一第一方向上延伸之複數個列及對準成在垂直於該第一方向之一第二方向上延伸之複數個行的一記憶體單元陣列。
- 如請求項11之半導體裝置,其中對準成該複數個列中之每一者之該複數個記憶體單元安置於一單個導電條帶上。
- 如請求項8之半導體裝置,其中該複數個記憶體單元中之每一者之該閘流體包括安置於該導電條帶上之一高摻雜n型區、安置於該高摻雜n型區上之一p型區、安置於該p型區上之一n型區及安置於該n型區上之一高摻雜p型 區。
- 如請求項13之半導體裝置,其中該控制閘極安置於該p型區之至少一個表面上方且與該至少一個表面接觸。
- 如請求項8之半導體裝置,其進一步包括與其整合在一起之至少一個邏輯裝置。
- 如請求項8之半導體裝置,其中該導電材料包含一導電含金屬材料或一導電含金屬化合物材料。
- 一種記憶體陣列,其包括:一記憶體單元陣列,其包括:複數個閘流體,其等大致對準成在一第一方向上之複數個列及在垂直於該第一方向之一第二方向上之複數個行,該複數個閘流體中之每一者包括複數個垂直疊加之交替經摻雜半導體區;及至少一個控制閘極,該至少一個控制閘極與該複數個行中之至少一者中的該複數個閘流體中之每一閘流體之該複數個垂直疊加之交替經摻雜半導體區中之一者電耦合;及複數個導電條帶,每一者與該複數個列中之至少一者中的該複數個閘流體中之每一閘流體電耦合,該等導電條帶個別包括上覆於非晶矽上之一導電材料,該非晶矽安置於上覆於一基板上之一電絕緣材料上。
- 如請求項17之記憶體陣列,其中該至少一個控制閘極安置於對準成該複數個行中之一者的該複數個閘流體中之每一閘流體之至少一個側壁上。
- 如請求項17之記憶體陣列,其中該記憶體單元陣列之該複數個列中之一個列中的該複數個閘流體中之每一閘流體安置於該複數個導電條帶中之一個導電條帶上。
- 如請求項17之記憶體陣列,其進一步包括安置於對準成該複數個列中之一個列的該複數個閘流體上方且與該複數個閘流體對準之複數個導電線。
- 如請求項17之記憶體陣列,其進一步包括電耦合至該複數個導電條帶中之至少一者之至少一個邏輯裝置。
- 如請求項17之記憶體陣列,其中該導電材料包含一導電含金屬材料或一導電含金屬化合物材料。
- 一種形成一半導體裝置之方法,其包括:形成一半導體結構,該半導體結構包括上覆於一電絕緣材料上之非晶矽、上覆於該非晶矽上之一導電材料、上覆於該導電材料上之一經摻雜材料及上覆於該經摻雜材料上之一經摻雜結晶矽;移除該經摻雜結晶矽、該經摻雜材料、該導電材料及該非晶矽中之每一者之部分以形成曝露該電絕緣材料之複數個通道;移除該經摻雜結晶矽及該經摻雜材料之部分以形成複數個柱,該複數個柱中之每一柱包含一第一經摻雜區及相對於該第一經摻雜區相反摻雜之一第二經摻雜區;在該複數個柱中之每一柱之至少一個表面上形成至少一個控制閘極;將該複數個柱曝露至一第一摻雜劑以形成相對於該第 二經摻雜區相反摻雜之一第三經摻雜區;將該複數個柱曝露至一第二摻雜劑以形成一第四經摻雜區。
- 如請求項23之方法,其進一步包括在該複數個柱中之每一柱之該第四經摻雜區上方且與該第四經摻雜區接觸地形成至少一個導電線。
- 如請求項23之方法,其中在該複數個柱中之每一柱之至少一個表面上形成至少一個控制閘極包括在該第二及第三經摻雜區中之一者之一表面上方形成該控制閘極。
- 如請求項23之方法,其中形成包括上覆於一電絕緣材料上之非晶矽、上覆於該非晶矽上之一導電材料、上覆於該導電材料上之一經摻雜材料及上覆於該經摻雜材料上之一經摻雜結晶矽的一半導體結構包括:形成包括上覆於該導電材料上之該非晶矽之一施體晶圓,該導電材料上覆於安置於一結晶矽晶圓上之該經摻雜材料上;將離子植入至該結晶矽晶圓中至一預定深度;將該施體晶圓之該非晶矽附著至一受體晶圓上之該電絕緣材料;及分離該施體晶圓之一部分以留下該結晶矽晶圓、該經摻雜材料、該導電材料及該非晶矽之一部分上覆於該受體晶圓之該電絕緣材料之一表面上。
- 如請求項23之方法,其中形成一半導體結構進一步包括形成包括形成於下伏於該電絕緣材料上之一晶圓上之一 邏輯裝置的一半導體結構。
- 如請求項23之方法,其中移除該經摻雜結晶矽、該經摻雜材料、該導電材料及該非晶矽中之每一者之部分以形成曝露該電絕緣材料之複數個通道包括形成在一第一方向上延伸之該複數個通道。
- 如請求項28之方法,其中移除該經摻雜結晶矽及該經摻雜材料之部分以形成複數個柱包括移除在大致垂直於該第一方向之一第二方向上之材料。
- 一種系統,其包括:至少記憶體存取裝置;及至少一個半導體裝置,該至少一個半導體裝置可操作地耦合至該至少一個記憶體存取裝置且包括:至少一個導電條帶,該導電條帶包括上覆於非晶矽上之一導電材料,該非晶矽安置於上覆於一基板上之一電絕緣材料上;及安置於該至少一個導電條帶上之複數個記憶體單元,該複數個記憶體單元中之每一者包括:一閘流體;及一控制閘極,其與該閘流體相關聯;及一資料線,其與該複數個記憶體單元之至少一部分電耦合。
- 如請求項30之系統,其中該複數個記憶體單元中之每一者之該閘流體包括複數個交替經摻雜之垂直疊加區,該複數個交替經摻雜之垂直疊加區中之至少一者安置於該 至少一個導電條帶上方且與該至少一個導電條帶接觸。
- 如請求項30之系統,其中該複數個記憶體單元中之每一者具有4F2 之一單元大小。
- 如請求項30之系統,其中該導電材料包含一導電含金屬材料或一導電含金屬化合物材料。
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JP5578454B2 (ja) | 2014-08-27 |
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US20130323887A1 (en) | 2013-12-05 |
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