JP2013521649A - サイリスタベースメモリセル、デバイス及びそれらを含むシステム、そしてそれらを形成する方法 - Google Patents
サイリスタベースメモリセル、デバイス及びそれらを含むシステム、そしてそれらを形成する方法 Download PDFInfo
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- JP2013521649A JP2013521649A JP2012556082A JP2012556082A JP2013521649A JP 2013521649 A JP2013521649 A JP 2013521649A JP 2012556082 A JP2012556082 A JP 2012556082A JP 2012556082 A JP2012556082 A JP 2012556082A JP 2013521649 A JP2013521649 A JP 2013521649A
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- doped
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- thyristor
- memory cells
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
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- General Physics & Mathematics (AREA)
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- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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- Composite Materials (AREA)
- Semiconductor Memories (AREA)
- Thyristors (AREA)
Abstract
Description
この出願は、本件と同日に出願された“SEMICONDUCTOR−METAL−ON−INSULATOR STRUCTURES,METHODS OF FORMING SUCH STRUCTURES,AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES”という題名の同時係属米国特許出願12/XXX,XXX号(代理人整理番号2269−9742US)、本件と同日に出願された“FLOATING BODY CELL STRUCTURES,DEVICES INCLUDING THE SAME,AND METHODS FOR FORMING THE SAME”という題名の同時係属米国特許出願12/XXX,XXX号(代理人整理番号2269−9743US)、本件と同日に出願された“SEMICONDUCTOR DEVICES INCLUDING A DIODE STRUCTURE OVER A CONDUCTIVE STRAP,AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES”という題名の同時係属米国特許出願12/XXX,XXX号(代理人整理番号2269−9803US)、及び本件と同日に出願された“SEMICONDUCTOR CELLS,ARRAYS,DEVICES,AND SYSTEMS HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME”という題名の同時係属米国特許出願12/XXX,XXX号(代理人整理番号2269−9819US)と関連し、これらの各々の開示は、ここでの言及によって本明細書に組み入れられたものとする。
幾つかの実施形態において、本発明は、基板上に堆積された伝導ストラップと、前記伝導ストラップに堆積され、複数の代替ドープされた垂直に重なる半導体領域を含むサイリスタと、前記サイリスタの前記複数の代替ドープされる垂直に重なる半導体領域の1つ上に堆積される制御ゲートとを含むメモリセルを含む。基板上に堆積される前記伝導ストラップは、アモルファスシリコンの上の伝導材料を含んでもよい。前記伝導ストラップの少なくとも2つの側壁は、前記サイリスタの側壁に整列されてもよい。前記サイリスタは、お互いの上に垂直に重なるカソード領域、pベース領域、nベース領域とアノード領域を含んでもよい。前記制御ゲートは、前記n−型シリコンの露出される側壁上に堆積されてもよい。前記制御ゲートは、電圧源に実施可能な接続がなされてもよい。メモリセルは、4F2のセルサイズを有してもよい。
この出願は、2010年3月2日に出願された“SEMICONDUCTOR−METAL−ON−INSULATOR STRUCTURES,METHOD OF FORMING SUCH STRUCTURES,AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES”という題名の同時係属米国特許出願12/715,704号、2010年3月2日に出願された“FLOATING BODY CELL STRUCTURES,DEVICES INCLUDING THE SAME,AND METHODS FOR FORMING THE SAME”という題名の同時係属米国特許出願12/715,843号、2010年3月2日に出願された“SEMICONDUCTOR DEVICES INCLUDING A DIODE STRUCTURE OVER A CONDUCTIVE STRAP,AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES”という題名の同時係属米国特許出願12/715,743号、及び2010年3月2日に出願された“SEMICONDUCTOR CELLS,ARRAYS,DEVICES,AND SYSTEM HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME”という題名の同時係属米国特許出願12/715,922号と関連し、これらの開示は、ここでの言及によって本明細書に組み入れられたものとする。
Claims (30)
- 基板上に堆積される伝導ストラップと、
前記伝導ストラップ上に堆積され、複数の代替ドープされた垂直に重なる半導体領域を含むサイリスタと、
前記サイリスタの複数の代替ドープされた垂直に重なる半導体領域の1つ上に堆積される制御ゲートとを含む
ことを特徴とするメモリセル。 - 前記伝導ストラップは、前記基板の上の電気的絶縁材料上に堆積されるアモルファスシリコンの上の伝導材料を含む
ことを特徴とする請求項1記載のメモリセル。 - 前記伝導ストラップの少なくとも2つの垂直表面は、前記サイリスタの側壁に整列される
ことを特徴とする請求項1記載のメモリセル。 - 前記サイリスタは、お互いの上に垂直に重ねるカソード領域、pペース領域、nベース領域、とアノード領域を含む
ことを特徴とする請求項1記載のメモリセル。 - 前記制御ゲートは、n−型シリコンの露出される側壁上に堆積される
ことを特徴とする請求項1記載のメモリセル。 - 前記制御ゲートは、電圧源に動作的に接続されている
ことを特徴とする請求項1記載のメモリセル。 - 前記メモリセルのセルサイズは4F2である
ことを特徴とする請求項1記載のメモリセル。 - 少なくとも1つの伝導ストラップと、
前記少なくとも1つの伝導ストラップ上に堆積される複数のメモリセルと、
前記複数のメモリセルの各々は、複数の代替ドープされた垂直に重なる半導体領域を含むサイリスタと、前記サイリスタに関連する制御ゲートとを含み、
前記複数のメモリセルの少なくともある部分と電気的に結合するデータ線とを含む
ことを特徴とする半導体デバイス。 - 前記複数のメモリセルの各々は、4F2のセルサイズを有する
ことを特徴とする請求項8記載の半導体デバイス。 - 前記少なくとも1つの伝導ストラップは、ウェファー上に形成される論理デバイスの上の電気的絶縁材料上に堆積される
ことを特徴とする請求項8記載の半導体デバイス。 - 前記複数のメモリセルは、第一方向に拡張する複数の行に整列され、そして第一方向と垂直する第二方向に拡張する複数の列に整列されるメモリセルのアレイを含む
ことを特徴とする請求項8記載の半導体デバイス。 - 前記複数の行の各々内に整列される複数のメモリセルは、単一の伝導ストラップ上に堆積される
ことを特徴とする請求項8記載の半導体デバイス。 - 前記複数のメモリセルの各々のサイリスタは、少なくとも1つの伝導ストラップ上に堆積された高ドープされたn−型領域、高ドープされたn−型領域上に堆積されたp−型領域、p−型領域上に堆積されたn−型領域、そしてn−型領域上に堆積された高ドープされたp−型領域を含む
ことを特徴とする請求項8記載の半導体デバイス。 - 前記制御ゲートは、前記p−型領域の少なくとも1つの表面上に堆積され、接続されている
ことを特徴とする請求項8記載の半導体デバイス。 - 少なくとも1つの論理デバイスが集積されていることを更に含む
ことを特徴とする請求項8記載の半導体デバイス。 - メモリセルのアレイを含むメモリアレイであって、前記メモリセルのアレイは
実質的に第一方向の複数の行と前記第一方向と垂直する第二方向の複数の列に整列される複数のサイリスタ、前記複数のサイリスタの各々は、複数の垂直に重なる代替ドープされた領域を含み、
前記複数の列の内少なくとも1つの前記複数のサイリスタの各々の前記複数の垂直に重ねられる代替ドープされた領域の1つと電気的に接続する少なくとも1つの制御ゲートを含み、
複数の伝導ストラップ、各々は、複数の行の内1つに整列された前記複数のサイリスタの各々と電気的に結合される
ことを特徴する前記メモリアレイ。 - 前記少なくとも1つの制御ゲートは、前記複数の列の内1つに整列された前記複数のサイリスタの各々の少なくとも1つの側壁上に堆積される
ことを特徴とする請求項16記載のメモリアレイ。 - 前記メモリセルのアレイの前記複数の行の内1つの行の前記複数のサイリスタの各々は、前記複数の伝導ストラップの1つ上に堆積される
ことを特徴とする請求項16記載のメモリアレイ。 - 複数の伝導ストラップを更に含み、前記複数の行の内1つの行で整列される前記複数のサイリスタに上に堆積されそして整列される
ことを特徴とする請求項16記載のメモリアレイ。 - 前記複数の伝導ストラップの少なくとも1つと電気的に結合する少なくとも1つの論理デバイスを更に含む
ことを特徴とする請求項16記載のメモリアレイ。 - 電気的絶縁材料の上のアモルファスシリコンと、前記アモルファスシリコンの上の伝導材料と、前記伝導材料の上のドープされた材料と、前記ドープされた材料の上のドープされた結晶シリコンとを含む半導体構造を形成し、
電気的絶縁材料を露出する複数のチャネルを形成するために前記ドープされた結晶シリコン、前記ドープされた材料、前記伝導材料と前記アモルファスシリコンの各々の部分を除去し、
複数の柱を形成するために前記ドープされた結晶シリコンと前記ドープされた材料を除去し、各々の柱は第一ドープされた領域と前記第一ドープされた領域に対して反対にドープされる第二ドープされた領域を含み、
前記複数の柱の各々の少なくとも1つの表面上に制御ゲートを形成し、
前記第二ドープされた領域に対して反対にドープされる第三ドープされた領域を形成するために前記複数の柱を第一ドーパントに露出し、
前記第四ドープ領域を形成するために前記複数の柱を第二ドーパントに露出する
ことを特徴とする半導体デバイスの形成方法。 - 前記複数の柱の各々の前記第四ドープされた領域上に伝導線を形成し、接続されることを更に含む
ことを特徴とする請求項21記載の方法。 - 前記複数の柱の各々の少なくとも1つの表面上に前記制御ゲートの形成は、前記第二と前記第三ドープされた領域の表面上に少なくとも1つの伝導線を形成することを更に含む
ことを特徴とする請求項21記載の方法。 - 電気的絶縁材料の上のアモルファスシリコンと、前記アモルファスシリコンの上の伝導材料と、前記伝導材料の上のドープされた材料と、前記ドープされた材料の上のドープされた結晶シリコンとを含む半導体構造の形成は、
前記伝導材料の上の前記アモルファスシリコンを含むドナーウェファーを形成し、前記伝導材料は前記結晶シリコンウェファー上に堆積されるドープされた材料の上であり、
前記結晶シリコンウェファー内に予め決められた深さまでイオンを注入し、
前記ドナーウェファーの前記アモルファスシリコンをアセプタウェファー上の前記電気的絶縁材料に取り付け、
前記結晶シリコンウェファー、前記ドープされた材料、前記伝導材料と、前記アセプタウェファーの前記電気的絶縁材料の表面の上の前記アモルファスシリコンを捨てるために前記ドナーウェファーの部分を切り離すことを更に含む
ことを特徴とする請求項21記載の方法。 - 半導体構造の形成は、前記電気的絶縁材料の下にあるウェファー上に形成される論理デバイスを含む半導体構造の形成を更に含む
ことを特徴とする請求項21記載の方法。 - 電気的絶縁材料を露出する複数のチャネルを形成するために前記ドープされた結晶シリコン、前記ドープされた材料、前記伝導材料と前記アモルファスシリコンの各々の部分の除去は、第一方向に拡張する前記複数のチャネルを形成することを含むこと
ことを特徴とする請求項21記載の方法。 - 複数の柱を形成するために前記ドープされた結晶シリコンと前記ドープされた材料の除去は、実質的に前記第一方向と垂直する第二方向内の材料を除去することを含む
ことを特徴とする請求項21記載の方法。 - 少なくともメモリアクセスデバイスと、
前記少なくとも1つのメモリアクセスデバイスとの結合可能な少なくとも1つの半導体デバイスとを含み、
前記少なくとも1つの半導体デバイスは、
少なくとも1つの伝導ストラップと、
前記少なくとも1つの伝導ストラップ上に堆積される複数のメモリセルと、前記複数のメモリセルの各々は、サイリスタと、前記サイリスタに関連する制御ゲートとを含み、
前記複数のメモリセルの少なくともある部分と電気的に結合するデータ線とを含む
ことを特徴とするシステム。 - 前記複数のメモリセルの各々の前記サイリスタは、複数の垂直に重なる代替ドープされた半導体領域を含み、これらの少なくとも1つは、前記少なくとも1つの伝導ストラップ上に堆積されそしてそれに接続する
ことを特徴とする請求項28記載のシステム。 - 前記複数のメモリセルの各々は、4F2のセルサイズを有する
ことを特徴とする請求項28記載のシステム。
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KR20220046283A (ko) | 2020-10-07 | 2022-04-14 | 삼성전자주식회사 | 반도체 메모리 소자 |
KR20220055513A (ko) | 2020-10-26 | 2022-05-04 | 삼성전자주식회사 | 반도체 메모리 장치 |
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US8288795B2 (en) | 2012-10-16 |
SG183451A1 (en) | 2012-09-27 |
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TWI482278B (zh) | 2015-04-21 |
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US8524543B2 (en) | 2013-09-03 |
US20110215371A1 (en) | 2011-09-08 |
US20130323887A1 (en) | 2013-12-05 |
CN102782848A (zh) | 2012-11-14 |
CN102782848B (zh) | 2015-10-14 |
JP5578454B2 (ja) | 2014-08-27 |
TW201203539A (en) | 2012-01-16 |
US20150179649A1 (en) | 2015-06-25 |
WO2011109147A3 (en) | 2011-11-24 |
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US20130011974A1 (en) | 2013-01-10 |
US8980699B2 (en) | 2015-03-17 |
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