US20040017721A1 - Magnetic storage device - Google Patents

Magnetic storage device Download PDF

Info

Publication number
US20040017721A1
US20040017721A1 US10364655 US36465503A US2004017721A1 US 20040017721 A1 US20040017721 A1 US 20040017721A1 US 10364655 US10364655 US 10364655 US 36465503 A US36465503 A US 36465503A US 2004017721 A1 US2004017721 A1 US 2004017721A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
device
magnetic
voltage
stack
orientation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10364655
Inventor
Nikolai Franz Schwabe
Carsten Heide
Roger Elliott
Original Assignee
Schwabe Nikolai Franz Gregoe
Carsten Heide
Elliott Roger James
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Abstract

A magnetic storage device comprises an array of magnetic memory cells (50). Each cell (50) has, in electrical series connection, a magnetic tunnel junction (MTJ) (30) and a Zener diode (40). The MTJ (30) comprises, in sequence, a fixed ferromagnetic layer (FMF) (32), a non-magnetic spacer layer (33), a tunnel barrier layer (34), a further spacer layer (35), and a soft ferromagnetic layer (FMS) (36) that can change the orientation of its magnetic moment. The material type and thickness of each layer in the MTJ (30) is selected so that the cell (50) can be written by applying a voltage across the cell, which sets the orientation of the magnetic moments of the FMF (32) and FMS (36) relative to one another. The switching is effected by means of an induced exchange interaction between the FMS and FMF mediated by the tunneling of spin-polarised electrons in the MTJ (30). The cell (50) therefore has low power consumption during write operations allowing for fast writing and dense integration of cells (50) in an array. The mechanism used to control the array to write and sense the information stored in the cells (50) is simplified.

Description

    DESCRIPTION
  • 1. Field of the Invention [0001]
  • The present invention relates to non-volatile magnetic random access memory (MRAM) storage elements. [0002]
  • 2. Background of the Invention [0003]
  • Important characteristics of mass information storage devices of the future should be high speed, low power consumption, low cost and small size. To achieve this aim, magnetic random access memories (MRAMs) have been proposed due to their non-volatile nature. Unlike dynamic random access memory (DRAM) cells, non-volatile memory cells such as MRAM cells do not require a complex circuitry for perpetual electronic refreshing of the information stored, and thus can in principle outperform DRAM cells in all above mentioned characteristics. [0004]
  • The first of such MRAMs were based on magnetic multi-layer structures, deposited on a substrate. U.S. Pat. No. 5,343,422, for example, discloses a structure in which two layers of ferromagnetic material are separated by a layer of non-magnetic metallic conducting material. One of the magnetic materials, called the ferromagnetic fixed layer (FMF), has a fixed direction of magnetic moment, e.g. by having a particularly high coercive field or strong uni-axial anisotropy. The magnetisation of the other magnetic layer, called the ferromagnetic soft layer (FMS), is free to change direction between parallel and anti-parallel alignment relative to the direction of the magnetic moment of FMF. [0005]
  • The state of the storage element represents a logical “1” or “2” depending on whether the directions of the magnetic moments of the magnetic layers are aligned parallel or anti-parallel, respectively. Because the resistance levels are different for different mutual orientations of the magnetic layers, the structure acts as a spin valve. It thus allows the sensing of the state of the storage element by measuring the differential resistance ΔR/R with a current, where ΔR is the difference in resistance of the storage element for two different states of orientation, and R is its total resistance. Due to the high conductance of the device, strong currents are needed to obtain a high enough output voltage signal level for the sensing operation. A switching between these orientations can be achieved by passing write currents in the vicinity of the FMS, usually by using write lines which run past the layered structure on either side. These write currents, which do not pass through the layered structure itself, induce a magnetic field at the location of the FMS which alters the orientation of the FMS, if it is stronger than the coercive field H[0006] c of the FMS.
  • The main disadvantage of this set-up is the relatively high power consumption during both write and sense operations due to the high conductance of the structure. For example, conducting thin films have low sheet resistivities of about 10 Ω/μm[0007] 2 leading to cell resistances of about 10 Ω for currently realisable devices. Such devices require high sense currents of the order of a 0.1 mA in order to get voltage signals in the region of 1 mV. Therefore MRAM storage devices with higher resistance have been sought for.
  • An alternative was proposed by J. M. Doughton, [0008] J. Appl. Phys., 81, pp. 3758-3763 (1997). There, the conducting non-magnetic spacer layer between the two magnetic layers is replaced by an insulator. The device therefore forms a magnetic tunnel junction (MTJ), where spin polarised electrons tunnel through the insulator. It has a high impedance with resistivity values of 104-10 9 Ω/μm2, allowing for high speed MRAMs. Further, when put into a two dimensional array such an MRAM cell can be controlled by just using two lines per cell, the minimum needed to locate the cell in such an array. Such an array, shown in FIG. 1A is proposed in U.S. Pat. No. 5,640,343, the disclosure of which is incorporated herein by reference.
  • With reference to FIG. 1A, the memory cell elements are arranged vertically between parallel electrically conductive word lines [0009] 1, 2, 3 and bit lines 4, 5, 6. This makes the device topologically simple and allows in principle for a denser array than is achievable with a similar line-width process for DRAMs. The MRAM array shown in FIG. 1A uses memory cells 9, shown in FIG. 1B, that comprise each a MTJ 8 and a p-n diode 7 in electrical series connection. The diode 7 is formed as a silicon junction with an n-type layer 10 and a p-type layer 11. It is connected by an intermediate layer 12 to the MTJ 8, which is formed as a series of stacked layers comprising a template layer 15, a first ferromagnetic layer 16, a anti-ferromagnetic layer 18 a FMF 20, a tunnelling barrier layer 22, a FMS 24 and contact layer 25.
  • The presence of the diode [0010] 7 in the memory cell 9 allows the use of only two lines per cell. The device can be operated such that during a sense operation only one memory cell in the MRAM will be forward biased whereas the remaining cells will either not be biased or reverse biased. Since the reverse bias is always kept below the breakdown voltage of the diode 7, no current flows through these cells.
  • A cell is written by sending simultaneously a current through the word and bit line crossing at the location of the cell. Although these currents do not pass through the cell itself, the magnetic field induced by the current at the location of the FMS is strong enough to switch the orientation of the magnetic moment between its two preferred states along the easy axis of the FMS. The FMF, however, has a coercivity that is high enough such that its magnetic moment is left unchanged in this process. Similarly, in the other memory cells which lie along either the bit or word line used in the switching, the magnetic field induced by the current passing only in one line is not strong enough to switch the FMS. This set-up however still suffers from high power consumption during write operations. [0011]
  • As a consequence of the magnetic fields of the switching currents the density of planar integration of MJT cells in an array is also limited. Further, the supporting electric circuitry has to be designed such that both write and sense currents can be effected to flow along different paths which makes such circuitry quite complex. [0012]
  • SUMMARY OF THE INVENTION
  • In its first aspect, the present invention comprises a magnetic tunnel junction device comprising first and second stacks of layers of magnetic material, each stack comprising at least one layer, the stacks being separated by a third stack of layers of non-magnetic material, the third stack comprising at least one layer of electrically insulating material, with contacts being made to the first and second stack to apply a voltage across the device, the magnetic materials and insulating material(s) each being of a type and the said layers each having a thickness such that the orientation of the magnetic moments of said first and second stack relative to one another are changeable by applying a voltage across the device, characterised in that said orientation can be switched to a first state by applying a first voltage across the device and that said orientation can be switched to a second state applying a second voltage across the device, whereby after either switching the said orientation is maintained when a third voltage is applied to the device the said third voltage being in between the first and second voltage. [0013]
  • Preferably, the magnetic tunnel junction device comprises a layer of nonmagnetic conductive material between at least one of the layers of magnetic material in the first or second stack and the at least one layer of insulating material in the third stack. [0014]
  • Preferably, a single layer of insulating material is provided to form a single tunnel barrier between the first and second stack. Alternatively, two layers of insulating material separated by a layer of non-magnetic conductive material may be provided to form a double tunnel barrier, which can be advantageous due to its special transmission characteristics. [0015]
  • In its second aspect the present invention comprises an array of magnetic memory cell devices, said array comprising a first plurality of conducting leads, a second plurality of conducting leads, each lead in the said second plurality crossing over each lead in the said first plurality, a plurality of magnetic memory cell devices, each magnetic memory cell device comprising in electrical series connection a diode and a magnetic tunnel junction device according to the first aspect of the present invention, each magnetic memory cell device being located at an intersection region between one of the first plurality of leads and one of the second plurality of leads, the array having means to apply a voltage to the leads in the first and second plurality such that a voltage drop across a specific memory cell device can be effected the voltage drop causing the said memory cell device to be written. [0016]
  • In its third aspect the present invention comprises a method of providing a magnetic tunnel junction device comprising providing a magnetic tunnel junction comprising first and second stacks of layers of magnetic material, each stack comprising at least one layer, the stacks being separated by a third stack of layers of non-magnetic material, the third stack comprising at least one layer of electrically insulating material, with contacts being made to said first and second stack to apply a voltage across the magnetic tunnel junction the type and thickness of said magnetic and insulating materials being selected such that the orientation of the magnetic moments of said first and second stack relative to one another can be changed by applying a voltage across the device, characterised in that said orientation can be switched to a first state by applying a first voltage across the device and that said orientation can be switched to a second state applying a second voltage across the device, whereby after either switching the said orientation is maintained when a third voltage is applied to the device the said third voltage being in between the first and second voltage. [0017]
  • In its fourth aspect the present invention comprises a method of providing an array of magnetic memory cell devices comprising providing a first plurality of conducting leads, a second plurality of conducting leads, each lead in the said second plurality crossing over each lead in the said first plurality, a plurality of magnetic memory cell devices, each magnetic memory cell device comprising in electrical series connection a diode and a magnetic tunnel junction device according to the third aspect of the present invention, each magnetic memory cell device being located at an intersection region between one of the first plurality of leads and one of the second plurality of leads, and providing means to apply a voltage to the leads in the first and second plurality such that a voltage drop across a specific memory cell device can be effected, the voltage drop causing a magnetic field in the device through tunnelling of spin-polarised electrons which effects the device to be written by setting the orientation of the said magnetic moments relative to one another. [0018]
  • In this second and fourth aspect the present invention is therefore an MRAM using MTJ elements as memory cells in implementations where both write and sense currents are passing through the cell perpendicularly. The invention utilises the combined effect of the non-linear current-voltage characteristics of the tunnel process and the non-equilibrium exchange coupling between the two magnetic layers (N. F. Schwabe et al., [0019] Physical Review B 54, pp. 12953-12968 (1996) and R. J. Elliott et al., Journal of Magnetism and Magnetic Materials 177-181, pp. 769-770 (1998)).
  • It has been shown that when a MTJ, and preferably a MTJ comprising a non-magnetic spacer layer (NMS) between the FMS and the barrier layer and between the FMF and the barrier layer, is significantly biased out of equilibrium a strong spin polarised tunnelling current flows through the MTJ. At the same time, due to the difference in Fermi-wavevectors on either side of the MTJ, the exchange interaction changes its characteristic periodicity, and becomes a superposition of periodic functions with several wavelengths. Further, when the MTJ is biased, a strong spin-current induced exchange interaction (SCE) occurs between the magnetic layers on either side of the MTJ, which has terms that scale with the voltage and the thickness of the FMF and the FMS. This allows changing both the sign and the strength of the exchange interaction by applying voltage across the device that is higher than a typical voltage used to sense the device. [0020]
  • Switching occurs when the voltage across the device is strong enough to induce a spin current across the junction which carries a magnetic field H[0021] E across the junction that is higher than the coercive field HC of the FMS and that has opposite sign of the alignment of the magnetic moment of the FMS. When the voltage across the MTJ is lowered again after such switching has been effected the spin-current induced magnetic field HE sinks below the coercive field HC of the FMS, and the FMS remains in the switched state.
  • In order to switch the device in the opposite direction, the MTJ has to be designed such that, when the junction is biased reverse the first time the SCE exceeds H[0022] C of the FMS, the sign of the interaction is opposite that of the SCE when used to switch the FMS using a forward voltage. For this purpose, the MTJ has to be designed to have an asymmetric voltage-interaction response. For example the thickness of the FMS and the FMH have to be controlled such that the voltage-interaction response curve scales in relation to HC approximately as shown in FIG. 3, where for forward voltage the first switching always occurs towards parallel alignment between the FMS and the FMF and for reverse voltage to anti-parallel alignment. FIG. 3 will be described in more detail later.
  • To sense the orientation of the FMS and FMF relative to one another, a weak sense voltage, that does not affect the orientation of the FMS, is applied across the device, and the resistance differential of the MTJ ΔR/R is measured with respect to a given reference orientation similar to that in devices of the prior art. [0023]
  • Being able to switch the FMS by applying a voltage across the memory cell according to the present invention, rather than running strong currents past the memory cell which do not flow across the cell, substantially reduces the power consumption of the device and impedance effects in the MRAM array. Further, only having to control voltages across a memory cell according to the invention, compared with having to control both voltages across cells and currents flowing past cells, reduces the complexity of the electrical circuit driving the MRAM array. [0024]
  • SPECIFIC EMBODIMENTS
  • Further embodiments of the present invention shall now be described with reference to the accompanying drawings in which: [0025]
  • FIG. 1A shows a perspective view of a MRAM array with magnetic memory cells located vertically between bit and word lines, [0026]
  • FIG. 1B shows an enlarged view of one of the memory cells shown in FIG. 1A, [0027]
  • FIG. 2 shows a perspective view of a memory cell according to the present invention, [0028]
  • FIG. 3 shows the exchange field—voltage response of an MTJ memory cell in relation to the coercive field H[0029] C of the FMS according to the invention,
  • FIG. 4 shows schematically the diagram of the electric circuit formed by the MRAM array, and [0030]
  • FIG. 5 illustrates the voltage levels on the leads in the MRAM array according to the invention. [0031]
  • FIG. 1A and FIG. 1B have already been described.[0032]
  • CONSTRUCTION AND OPERATION OF THE MEMORY CELL
  • The memory cell [0033] 50 in FIG. 2 is formed as a series of layers similar to the one disclosed in U.S. Pat. No. 5,640,343, but different in detail. In one of its preferred embodiments the cell comprises an MTJ 30 in series with a PN junction diode 40. The MTJ comprises a first contact layer 31, which can be Cu or Pt, a FMF 32 such as Co—Pt—Cr, a first NMS 33 such as Cu or Pt, a tunnelling barrier layer 34 such as MgO, a second NMS 35 such as Cu or Pt, a FMS 36 such as Ni—Fe, and a second contact layer 37 such as Cu or Pt.
  • The diode [0034] 40 is formed on a semiconductor substrate such as Si and contains layers of p- and n-doped Si 41 and 42, respectively. The p-doped region 41 is in contact with the second contact layer 39, and the n-doped region 42 is in contact with a word line (not shown). The initial contact layer 31 is in contact with the bit line (not shown). Preferably, the diode is formed as a Zener-diode, i.e. it can be operated through a reverse breakdown voltage in the avalanche breakdown region.
  • The FMF [0035] 32 and the FMS 36 are fabricated to have easy axes of magnetisation that align with one another. By using for the FMF 32 a material with particularly high anisotropy such as Co—Pt—Cr the direction of magnetisation of the easy axis of the FMF 32 is fixed against the one of the FMS 36. Alternatively, the direction of magnetisation of the FMF 32 can be set by an unidirectional anisotropy as given, for example, in U.S. Pat. No. 5,465,185. For the FMS 36 there are two possible directions along its easy axis, which define the two states of the memory cell. In addition the FMS may be fabricated to have a low coercivity by giving it an elliptical shape or forming tapers at the corners, giving it a hexagonal or octagonal shape, in order to suppress the effects of edge domains.
  • There are several differences between this embodiment and the prior art. The properties of the FMF [0036] 32 and the FMS 36 are not chosen with regard to their response to writing fields produced by external writing currents, but with regard to an optimal current-voltage characteristics facilitating both read and write operations by passing a current perpendicularly through the cell 40. The thickness and magnetic properties of the FMF 32 and the FMS 36 are chosen to achieve an asymmetric SCE which has a voltage response function such as the one shown in FIG. 3.
  • The construction of the tunnel barrier [0037] 34 is not only determined by the desired values for ΔR/R to sense the state of the FMS 36, but also to accommodate switching. Due to its effect on the write performance of the device MgO is preferred as a material for the tunnel barrier 36. Alternatively, two layers of insulating material separated by a layer of non-magnetic conductive material may be provided to form a double tunnel barrier.
  • The presence of the NMSs [0038] 33 and 35 on one or both sides of the tunnel barrier between the FMF 32 and the tunnel barrier 34 as well as the FMS 36 and the tunnel barrier 34 is advantageous for the SCE effect as it allows the phase of the exchange interaction across the MTJ to be tuned. This is desirable to ensure that the sign of the SCE can be changed at a reasonable voltage level across the MTJ 30. The disadvantage of a very large spacer layer is, however, that the SCE decays over distance. Therefore, the right trade-off has to be achieved between appropriate phase and sufficient interaction amplitude in the optimal design of the thickness of both NMSs 33, 35.
  • Further advantages of the NMSs [0039] 33, 35 is that they help to reduce lattice mismatch, thus enlarging the range of possible magnetic materials, and also reduce the number of magnetic impurities in the tunnel barrier 34 which could impair the properties of the MTJ.
  • Further, the diode [0040] 40, formed as a Zener device, accommodates two operational regimes. One regime for the sense operation similar to the prior art, and the other one during write operations where for writing at least one of the two possible logical states a reverse voltage has to be applied to the diode 40 that is greater than its breakdown voltage.
  • It should be noted that although the presence of the NMSs facilitates the achievement of the desired characteristics of the MTJ their use is not strictly necessary and devices are conceivable without their use, but including the same form of operation. [0041]
  • FIG. 3 shows the strength of the exchange interaction, represented by the exchange field H[0042] E versus the voltage drop V across the MTJ 30. When the voltage across the MTJ is increased from the vicinity of zero beyond the forward bias VP, such that HE>HC, and lowered back again to the inception point the FMS 36 will be left in parallel alignment with the FMF 32. Similarly, when V is increased beyond VAP, such that HE<−HC, and subsequently lowered again to close to zero, the FMS 36 and FMF 32 will be left in anti-parallel alignment. A sensing of the cell can be achieved by applying a small sensing voltage VS across the MTJ and measuring the resistance differential ΔR/R with respect to a given reference value. VS is thereby substantially smaller in absolute magnitude than both VP and VAP.
  • It should be noted that the invention is not limited to the use of single layer FMF [0043] 32 and FMS 36, which can be replaced by stacks of magnetic layers, respectively, in order to tune the magnetic moment, anisotropy, and coercivity of these layers. Similarly the transmission characteristics of the tunnel barrier 34 can be tuned by replacing it with a double barrier structure that contains a conductive layer between two insulating layers.
  • Operation of the MRAM Array
  • An MRAM array according to the present invention has the same topographic design as the prior art MRAM array of FIG. 1A with the difference that it contains a memory cell according to the invention at each node in the array. A circuit diagram of the MRAM array according to the present invention is shown in FIG. 4, which is also similar to the prior art. As shown FIG. 4 the memory cells [0044] 70 to 78 lie at the intersections of the word lines 1, 2, 3 with the bit lines 4, 5, 6, which in turn are connected to the control circuits 51 and 53. Different from the operation of the prior art MRAM, however, a memory cell 70 is written by applying a strong voltage to the cell either as a forward or reverse voltage, depending on which way the cell should be switched. A voltage level diagram of the MRAM array of FIG. 4 in operation is shown in FIG. 5.
  • In FIG. 5 the cell [0045] 70 is first switched to a parallel alignment representing a logical “1”, then the state of cell 70 is sensed. Subsequently, the cell is switched to an anti-parallel alignment representing a logical “0” after which the state of the cell is sensed again.
  • During the switching to state “1” a voltage V[0046] F is applied to bit line 4, using circuit 51. At the same time the voltage on bit lines 5 and 6 as well as word line 1 are set to zero, while the word lines 2 and 3 are also biased to the voltage VF using both circuits 51 and 53. The voltage VF across memory cell 70 induces a voltage drop VP across the MTJ which, as shown in FIG. 3, is strong enough to switch the orientation of its FMS in the MTJ to a parallel alignment. While the cell 70 is now biased forward at VF, cells 71, 72, 73, and 76 are unbiased and cells 74, 75, 77, 78 are reverse biased at −VF, which is still less than the breakdown voltage of the Zener-diode and therefore does not lead to a substantial voltage drop across the MTJ.
  • A sensing operation is carried out by applying a voltage V[0047] S to bit line 4, while setting the voltage on word line 1 to zero. At the same time bit lines 5, 6 are kept at zero voltage whereas word lines 2, 3 are biased to VS. This way it can be seen that there will be a positive voltage drop VS across cell 70, whereas all the other cells either have no voltage drop across them or a small reverse voltage −VS which is smaller than the breakdown voltage of the Zener-diode.
  • Finally, an operation to write a logical “0” into cell [0048] 70 is achieved by setting the voltage on bit line 4 to −VR while setting the voltage on word line 1 to VR. The total voltage drop across cell 70 of −2VR is now such that it is greater than the reverse breakdown voltage of the Zener-diode and such that it induces a voltage drop VAP across the MTJ which is strong enough to switch the FMS to “0”, as indicated in FIG. 3. At the same time the voltage on bit lines 5, 6 are left at zero, while the voltage on word lines 2, 3 are kept at VS. Neither of the voltage drops of −VR and −VR+VS across cells 71, 72 and 73, 76, respectively are high enough to cause a reverse breakdown of the Zener-diode, thus avoiding a notable voltage drop across the relevant MTJs.
  • In the embodiment of the MRAM array described above, voltages are applied using the control circuits [0049] 51, 53, such that during either a read or write operation only one cell will be addressed at any one time and the power consumption of the device is kept to a minimum. The method of applying voltages described here is merely an example to which the invention is not limited, and other combinations of applying voltages for operating a memory cell and the MRAM array are conceivable.

Claims (36)

  1. 1. A magnetic tunnel junction device comprising first and second stacks of layers of magnetic material, each stack comprising at least one layer, the stacks being separated by a third stack of layers of non-magnetic material, the third stack comprising at least one layer of electrically insulating material, with contacts being made to the first and second stack to apply a voltage across the device, the magnetic materials and insulating material(s) each being of a type and the said layers each having a thickness such that the orientation of the magnetic moments of said first and second stack relative to one another are changeable by applying a voltage across the device, characterised in that said orientation can be switched to a first state by applying a first voltage across the device and that said orientation can be switched to a second state applying a second voltage across the device, whereby after either switching the said orientation is maintained when a third voltage is applied to the device the said third voltage being in between the first and second voltage.
  2. 2. A device as claimed in claim 1 in which at least one of the said first and second stacks is separated from the third stack by a further layer of non-magnetic conducting material.
  3. 3. A device as claimed in claim 1 or claim 2 in which the third stack comprises two layers of insulating material separated from one another by a layer of nonmagnetic conductive material.
  4. 4. A device as claimed in any preceding claim in which at least one of the layers of magnetic material in the said first or second stack has a substantially elliptical shape.
  5. 5. A device as claimed in claims 1, 2 or 3 in which at least one of the layers of magnetic material in the said first or second stack has a substantially hexagonal or octagonal shape.
  6. 6. A device as claimed in any preceding claim in which the easy axes of the magnetisation of the said first and second stack are aligned with one another such that the orientation of the magnetic moments of said first and second stack relative to one another are changeable between substantially parallel and substantially anti-parallel states.
  7. 7. A device as claimed in claim 6 with the magnetic materials and insulating material(s) each being of a type and the said layers each having a thickness thus causing an asymmetric current response such that the changing from substantially parallel to substantially anti-parallel state is allowed to be effected by applying a forward or backward voltage to the device, wherein the change effected by applying a forward voltage is opposite to the change effected by applying a backward voltage.
  8. 8. A device as claimed in any preceding claim comprising sensing means connected to the said contacts which allows the orientation of the magnetic moments of said first and second stack relative to one another to be sensed by applying a fourth voltage across the device and measuring the resistance of the device.
  9. 9. A device as claimed in claim 8 in which the fourth voltage applied to the device in order to sense the state of the device is smaller in absolute terms than a voltage applied to the device in order to change the state of the device.
  10. 10. A device as claimed in any preceding claim in which the said third stack comprises at least one layer of manganese oxide (MgO).
  11. 11. A device as claimed in claim 10 in which the easy axes of the magnetisation of the said first and second stack are aligned with one another such that the device can be switched between two states in which the orientation of the magnetic moments of said first and second stack can be changed from a substantially parallel alignment to substantially anti-parallel alignment by applying one of the said first and second voltages to the device and said magnetic moments can be switched from a substantially anti-parallel alignment to a substantially parallel alignment by applying the other of the said first and second voltages to the device.
  12. 12. A magnetic memory cell device comprising a magnetic tunnel junction device as claimed in any preceding claim which comprises a diode in electrical series connection with the magnetic tunnel junction device.
  13. 13. A magnetic memory cell device as in claim 12 wherein the diode is a Zener diode.
  14. 14. A device as claimed in claim 12 or claim 13 having means allowing to effect one of the said voltages required to switch the relative orientation of the magnetic moments of the said first and second stacks in the magnetic tunnel junction device by allowing to apply a further voltage across the magnetic memory cell device said further voltage effecting a voltage across the diode which is a reverse voltage on the diode, said reverse voltage being greater than the breakdown voltage of the diode.
  15. 15. An array of magnetic memory cell devices comprising a first plurality of conducting leads, a second plurality of conducting leads, each lead in the said second plurality crossing over each lead in the said first plurality, a plurality of magnetic memory cell devices as claimed in claim 12 to claim 14, each magnetic memory cell device being located at an intersection region between one of the first plurality of leads and one of the second plurality of leads, the array having means to apply a voltage to the leads in the first and second plurality such that a voltage drop across a specific memory cell device can be effected, the voltage drop causing the said memory cell device to be written by setting the orientation of said magnetic moments relative to one another.
  16. 16. A method of providing a magnetic tunnel junction device comprising providing a magnetic tunnel junction comprising first and second stacks of layers of magnetic material, each stack comprising at least one layer, the stacks being separated by a third stack of layers of non-magnetic material, the third stack comprising at least one layer of electrically insulating material, with contacts being made to said first and second stack to apply a voltage across the magnetic tunnel junction the type and thickness of said magnetic and insulating materials being selected such that the orientation of the magnetic moments of said first and second stack relative to one another can be changed by applying a voltage across the device, characterised in that said orientation can be switched to a first state by applying a first voltage across the device and that said orientation can be switched to a second state applying a second voltage across the device, whereby after either switching the said orientation is maintained when a third voltage is applied to the device the said third voltage being in between the first and second voltage.
  17. 17. A method as claimed in claim 16 comprising providing two layers of insulating material in the said third stack, which two layers of insulating material are separated from one another by a layer of non-magnetic conductive material.
  18. 18. A method as claimed in claim 16 or claim 17 in which at least one of the layers of magnetic material in the said first or second stack is provided having a substantially elliptical shape.
  19. 19. A method as claimed in claims 16 to 17 in which at least one of the layers of magnetic material in the said first or second stack is provided having a substantially hexagonal or octagonal shape.
  20. 20. A method as claimed in claims 16 to 19 comprising providing a layer of nonmagnetic conductive material between the said third stack and at least one of the said first and second stacks.
  21. 21. A method as claimed in claim 16 to claim 20 in which the orientation of the magnetic moments of said first and second stack relative to one another can be changed between substantially parallel and substantially anti-parallel states.
  22. 22. A method as claimed in claim 21 in which changing from substantially parallel to substantially anti-parallel state is effected by applying a forward or backward voltage to the device, wherein the change effected by applying a forward voltage is opposite the change effected by applying a backward voltage.
  23. 23. A method as claimed in claims 16 to 22 in which the orientation of the magnetic moments of said first and second stack relative to one another can be sensed by applying a fourth voltage across the magnetic tunnel junction device and measuring the resistance of the device.
  24. 24. A method as claimed in claim 23 in which the fourth voltage applied to the device in order to sense the orientation of the magnetic moments of the said first and second stack relative to one another is smaller in absolute terms than the voltage applied to the device in order to change the relative alignment of said magnetic moments.
  25. 25. A method as claimed in any preceding claim in which the said third stack is provided with at least one layer of manganese oxide (MgO).
  26. 26. A method as claimed in claim 25 in which the device can be switched between two states in which the orientation of the magnetic moments of said first and second stack can be changed from a substantially parallel alignment to substantially anti-parallel alignment by applying on of the said first and second voltages to the device and said magnetic moments can be switched from a substantially anti-parallel alignment to a substantially parallel alignment by applying the other of the said first and second voltages to the device.
  27. 27. A method of providing magnetic memory cell device comprising providing a magnetic tunnel junction device as claimed in any of claims 16 to 25 which comprises providing a diode in electrical series connection with the magnetic tunnel junction device.
  28. 28. A method as claimed in claim 27 wherein the diode is a Zener diode.
  29. 29. A method as claimed in claim 27 or claim 28 in which one of the said voltages required to switch the relative orientation of the magnetic moments of said first and second stack in the magnetic tunnel junction device is effected by applying a further voltage across the magnetic memory cell device said further voltage effecting a voltage across the diode which is a reverse voltage on the diode, said reverse voltage being greater than the breakdown voltage of the diode.
  30. 30. A method of providing an array of magnetic memory cell devices comprising providing a first plurality of conducting leads, a second plurality of conducting leads, each lead in the said second plurality crossing over each lead in the said first plurality, a plurality of magnetic memory cell devices provided as claimed in claim 27 to claim 29, each magnetic memory cell device being located at an intersection region between one of the first plurality of leads and one of the second plurality of leads, and providing means to apply a voltage to the leads in the first and second plurality such that a voltage drop across a specific memory cell device can be effected, the voltage drop causing a magnetic field in the device through tunnelling of spin-polarised electrons which effects the device to be written by setting the orientation of the said magnetic moments relative to one another.
  31. 31. A magnetic tunnel junction device substantially as herein before described with reference to FIG. 2 to FIG. 5 of the accompanying drawings.
  32. 32. A magnetic memory cell device substantially as herein before described with reference to FIG. 2 to FIG. 5 of the accompanying drawings.
  33. 33. A magnetic memory cell array substantially as herein before described with reference to FIG. 2 to FIG. 5 of the accompanying drawings.
  34. 34. A method of providing a magnetic tunnel junction device substantially as herein before described with reference to FIG. 2 to FIG. 5 of the accompanying drawings.
  35. 35. A method of providing a magnetic memory cell device substantially as herein before described with reference to FIG. 2 to FIG. 5 of the accompanying drawings.
  36. 36. A method of providing a magnetic memory cell array substantially as herein before described with reference to FIG. 2 to FIG. 5 of the accompanying drawings.
US10364655 1998-10-30 2003-02-12 Magnetic storage device Abandoned US20040017721A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB9823694.6 1998-10-30
GB9823694A GB2343308B (en) 1998-10-30 1998-10-30 Magnetic storage device
US83041201 true 2001-04-27 2001-04-27
US10364655 US20040017721A1 (en) 1998-10-30 2003-02-12 Magnetic storage device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10364655 US20040017721A1 (en) 1998-10-30 2003-02-12 Magnetic storage device
US10874205 US7218550B2 (en) 1998-10-30 2004-06-24 Magnetic storage device
US11692160 US7616478B2 (en) 1998-10-30 2007-03-27 Magnetic storage device

Related Parent Applications (3)

Application Number Title Priority Date Filing Date
US09830412 Continuation
PCT/EP1999/008368 Continuation WO2000026918A1 (en) 1998-10-30 1999-11-02 Magnetic storage device
US83041201 Continuation 2001-04-27 2001-04-27

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10874205 Continuation US7218550B2 (en) 1998-10-30 2004-06-24 Magnetic storage device

Publications (1)

Publication Number Publication Date
US20040017721A1 true true US20040017721A1 (en) 2004-01-29

Family

ID=30772061

Family Applications (3)

Application Number Title Priority Date Filing Date
US10364655 Abandoned US20040017721A1 (en) 1998-10-30 2003-02-12 Magnetic storage device
US10874205 Active 2019-12-17 US7218550B2 (en) 1998-10-30 2004-06-24 Magnetic storage device
US11692160 Active US7616478B2 (en) 1998-10-30 2007-03-27 Magnetic storage device

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10874205 Active 2019-12-17 US7218550B2 (en) 1998-10-30 2004-06-24 Magnetic storage device
US11692160 Active US7616478B2 (en) 1998-10-30 2007-03-27 Magnetic storage device

Country Status (1)

Country Link
US (3) US20040017721A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080186759A1 (en) * 2007-02-06 2008-08-07 Yuui Shimizu Magnetic random access memory and write method of the same
US20090046501A1 (en) * 2006-04-27 2009-02-19 Yadav Technology, Inc. Low-cost non-volatile flash-ram memory
US20150070983A1 (en) * 2013-09-09 2015-03-12 Yoshinori Kumura Magnetic memory device
US9378797B2 (en) 2014-07-31 2016-06-28 Samsung Electronics Co., Ltd. Provide a memory device capable of increasing performance by performing a write operation using stable multi voltages that are applied to a word line
US9768229B2 (en) 2015-10-22 2017-09-19 Western Digital Technologies, Inc. Bottom pinned SOT-MRAM bit structure and method of fabrication

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7660181B2 (en) * 2002-12-19 2010-02-09 Sandisk 3D Llc Method of making non-volatile memory cell with embedded antifuse
US8008700B2 (en) * 2002-12-19 2011-08-30 Sandisk 3D Llc Non-volatile memory cell with embedded antifuse
KR100647319B1 (en) * 2005-02-05 2006-11-23 삼성전자주식회사 Multi-bit magnetic memory device using spin-polarized current and methods of manufacturing and operating the same
US7230265B2 (en) * 2005-05-16 2007-06-12 International Business Machines Corporation Spin-polarization devices using rare earth-transition metal alloys
US7366011B2 (en) * 2005-07-12 2008-04-29 The Regents Of The University Of California Power consumption minimization in magnetic random access memory by using the effect of hole-mediated ferromagnetism
US7800932B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Memory cell comprising switchable semiconductor memory element with trimmable resistance
US7800934B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Programming methods to increase window for reverse write 3D cell
US8089110B1 (en) * 2006-02-09 2012-01-03 Spansion Llc Switchable memory diodes based on ferroelectric/conjugated polymer heterostructures and/or their composites
US7450414B2 (en) * 2006-07-31 2008-11-11 Sandisk 3D Llc Method for using a mixed-use memory array
US20080023790A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array
US7486537B2 (en) * 2006-07-31 2009-02-03 Sandisk 3D Llc Method for using a mixed-use memory array with different data states
US20080025069A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array with different data states
US7760542B2 (en) 2008-04-21 2010-07-20 Seagate Technology Llc Spin-torque memory with unidirectional write scheme
US7974119B2 (en) 2008-07-10 2011-07-05 Seagate Technology Llc Transmission gate-based spin-transfer torque memory unit
US8233319B2 (en) 2008-07-18 2012-07-31 Seagate Technology Llc Unipolar spin-transfer switching memory unit
US7933146B2 (en) * 2008-10-08 2011-04-26 Seagate Technology Llc Electronic devices utilizing spin torque transfer to flip magnetic orientation
US7933137B2 (en) * 2008-10-08 2011-04-26 Seagate Teachnology Llc Magnetic random access memory (MRAM) utilizing magnetic flip-flop structures
US20100091546A1 (en) * 2008-10-15 2010-04-15 Seagate Technology Llc High density reconfigurable spin torque non-volatile memory
US9030867B2 (en) * 2008-10-20 2015-05-12 Seagate Technology Llc Bipolar CMOS select device for resistive sense memory
US7936580B2 (en) * 2008-10-20 2011-05-03 Seagate Technology Llc MRAM diode array and access method
US7936583B2 (en) * 2008-10-30 2011-05-03 Seagate Technology Llc Variable resistive memory punchthrough access method
US7825478B2 (en) * 2008-11-07 2010-11-02 Seagate Technology Llc Polarity dependent switch for resistive sense memory
US8178864B2 (en) 2008-11-18 2012-05-15 Seagate Technology Llc Asymmetric barrier diode
US8203869B2 (en) 2008-12-02 2012-06-19 Seagate Technology Llc Bit line charge accumulation sensing for resistive changing memory
US8159856B2 (en) 2009-07-07 2012-04-17 Seagate Technology Llc Bipolar select device for resistive sense memory
US8158964B2 (en) 2009-07-13 2012-04-17 Seagate Technology Llc Schottky diode switch and memory units containing the same
US9646869B2 (en) * 2010-03-02 2017-05-09 Micron Technology, Inc. Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices
US9608119B2 (en) 2010-03-02 2017-03-28 Micron Technology, Inc. Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
US8288795B2 (en) 2010-03-02 2012-10-16 Micron Technology, Inc. Thyristor based memory cells, devices and systems including the same and methods for forming the same
US8648426B2 (en) 2010-12-17 2014-02-11 Seagate Technology Llc Tunneling transistors
US8519431B2 (en) 2011-03-08 2013-08-27 Micron Technology, Inc. Thyristors
US8772848B2 (en) 2011-07-26 2014-07-08 Micron Technology, Inc. Circuit structures, memory circuitry, and methods
KR20150065446A (en) 2013-12-05 2015-06-15 삼성전자주식회사 Method of operating semiconductor memory devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640343A (en) * 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US5650958A (en) * 1996-03-18 1997-07-22 International Business Machines Corporation Magnetic tunnel junctions with controlled magnetic response
US5764567A (en) * 1996-11-27 1998-06-09 International Business Machines Corporation Magnetic tunnel junction device with nonferromagnetic interface layer for improved magnetic field response

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL273920A (en) 1961-01-25
GB1124340A (en) 1964-11-20 1968-08-21 Tokyo Shibaura Electric Co Magnetic film memory device
US3480926A (en) 1967-06-16 1969-11-25 Sperry Rand Corp Synthetic bulk element having thin-ferromagnetic-film switching characteristics
US4780848A (en) 1986-06-03 1988-10-25 Honeywell Inc. Magnetoresistive memory with multi-layer storage cells having layers of limited thickness
US4731757A (en) 1986-06-27 1988-03-15 Honeywell Inc. Magnetoresistive memory including thin film storage cells having tapered ends
US5173873A (en) 1990-06-28 1992-12-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration High speed magneto-resistive random access memory
JPH08510095A (en) 1994-02-21 1996-10-22 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ METHOD AND APPARATUS changing the magnetization direction of the magnetic partially
DE69513630D1 (en) 1994-10-05 2000-01-05 Koninkl Philips Electronics Nv Magnetic more management arrangement that includes a double-barrier structure resonant tunnel effect
US5541868A (en) 1995-02-21 1996-07-30 The United States Of America As Represented By The Secretary Of The Navy Annular GMR-based memory element
JP3293437B2 (en) 1995-12-19 2002-06-17 松下電器産業株式会社 The magnetoresistive element, a magnetoresistive head and memory element
US5835314A (en) 1996-04-17 1998-11-10 Massachusetts Institute Of Technology Tunnel junction device for storage and switching of signals
US5734605A (en) 1996-09-10 1998-03-31 Motorola, Inc. Multi-layer magnetic tunneling junction memory cells
US5801984A (en) * 1996-11-27 1998-09-01 International Business Machines Corporation Magnetic tunnel junction device with ferromagnetic multilayer having fixed magnetic moment
US5991193A (en) 1997-12-02 1999-11-23 International Business Machines Corporation Voltage biasing for magnetic ram with magnetic tunnel memory cells
US6130835A (en) 1997-12-02 2000-10-10 International Business Machines Corporation Voltage biasing for magnetic RAM with magnetic tunnel memory cells
US6072718A (en) 1998-02-10 2000-06-06 International Business Machines Corporation Magnetic memory devices having multiple magnetic tunnel junctions therein
US6114719A (en) 1998-05-29 2000-09-05 International Business Machines Corporation Magnetic tunnel junction memory cell with in-stack biasing of the free ferromagnetic layer and memory array using the cell
US6331944B1 (en) 2000-04-13 2001-12-18 International Business Machines Corporation Magnetic random access memory using a series tunnel element select mechanism
US6269018B1 (en) 2000-04-13 2001-07-31 International Business Machines Corporation Magnetic random access memory using current through MTJ write mechanism
US6316965B1 (en) * 2000-06-15 2001-11-13 The United States Of America As Represented By The Secretary Of The Navy Non-volatile reprogrammable logic circuits by combining negative differential resistance devices and magnetic devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640343A (en) * 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US5650958A (en) * 1996-03-18 1997-07-22 International Business Machines Corporation Magnetic tunnel junctions with controlled magnetic response
US5841692A (en) * 1996-03-18 1998-11-24 International Business Machines Corporation Magnetic tunnel junction device with antiferromagnetically coupled pinned layer
US5764567A (en) * 1996-11-27 1998-06-09 International Business Machines Corporation Magnetic tunnel junction device with nonferromagnetic interface layer for improved magnetic field response

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090046501A1 (en) * 2006-04-27 2009-02-19 Yadav Technology, Inc. Low-cost non-volatile flash-ram memory
US8120949B2 (en) * 2006-04-27 2012-02-21 Avalanche Technology, Inc. Low-cost non-volatile flash-RAM memory
US20080186759A1 (en) * 2007-02-06 2008-08-07 Yuui Shimizu Magnetic random access memory and write method of the same
US7869265B2 (en) 2007-02-06 2011-01-11 Kabushiki Kaisha Toshiba Magnetic random access memory and write method of the same
US20150070983A1 (en) * 2013-09-09 2015-03-12 Yoshinori Kumura Magnetic memory device
US9378797B2 (en) 2014-07-31 2016-06-28 Samsung Electronics Co., Ltd. Provide a memory device capable of increasing performance by performing a write operation using stable multi voltages that are applied to a word line
US9768229B2 (en) 2015-10-22 2017-09-19 Western Digital Technologies, Inc. Bottom pinned SOT-MRAM bit structure and method of fabrication

Also Published As

Publication number Publication date Type
US20080007996A1 (en) 2008-01-10 application
US20040233761A1 (en) 2004-11-25 application
US7616478B2 (en) 2009-11-10 grant
US7218550B2 (en) 2007-05-15 grant

Similar Documents

Publication Publication Date Title
Tehrani et al. Recent developments in magnetic tunnel junction MRAM
Engel et al. The science and technology of magnetoresistive tunneling memory
Daughton Magnetic tunneling applied to memory
US6111784A (en) Magnetic thin film memory element utilizing GMR effect, and recording/reproduction method using such memory element
US7282755B2 (en) Stress assisted current driven switching for magnetic memory applications
US6778421B2 (en) Memory device array having a pair of magnetic bits sharing a common conductor line
US6104633A (en) Intentional asymmetry imposed during fabrication and/or access of magnetic tunnel junction devices
US6777730B2 (en) Antiparallel magnetoresistive memory cells
US7660153B2 (en) Memory device and memory
US6114719A (en) Magnetic tunnel junction memory cell with in-stack biasing of the free ferromagnetic layer and memory array using the cell
US5969978A (en) Read/write memory architecture employing closed ring elements
US6172904B1 (en) Magnetic memory cell with symmetric switching characteristics
US6130835A (en) Voltage biasing for magnetic RAM with magnetic tunnel memory cells
US5841692A (en) Magnetic tunnel junction device with antiferromagnetically coupled pinned layer
US7009874B2 (en) Low remanence flux concentrator for MRAM devices
US7230845B1 (en) Magnetic devices having a hard bias field and magnetic memory devices using the magnetic devices
US6285581B1 (en) MRAM having semiconductor device integrated therein
US6055179A (en) Memory device utilizing giant magnetoresistance effect
Tehrani et al. Magnetoresistive random access memory using magnetic tunnel junctions
US5629549A (en) Magnetic spin transistor device, logic gate &amp; method of operation
US5946228A (en) Limiting magnetic writing fields to a preferred portion of a changeable magnetic region in magnetic devices
US5991193A (en) Voltage biasing for magnetic ram with magnetic tunnel memory cells
US6925000B2 (en) Method and apparatus for a high density magnetic random access memory (MRAM) with stackable architecture
US7345911B2 (en) Multi-state thermally assisted storage
US5923583A (en) Ferromagnetic memory based on torroidal elements