TWI401781B - 藉由嵌入跡線界定之導電墊 - Google Patents

藉由嵌入跡線界定之導電墊 Download PDF

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Publication number
TWI401781B
TWI401781B TW100113585A TW100113585A TWI401781B TW I401781 B TWI401781 B TW I401781B TW 100113585 A TW100113585 A TW 100113585A TW 100113585 A TW100113585 A TW 100113585A TW I401781 B TWI401781 B TW I401781B
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TW
Taiwan
Prior art keywords
component
conductive
conductive element
dielectric region
pad
Prior art date
Application number
TW100113585A
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English (en)
Chinese (zh)
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TW201218346A (en
Inventor
貝勒卡塞姆 哈巴
Original Assignee
泰斯拉公司
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Publication of TW201218346A publication Critical patent/TW201218346A/zh
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Publication of TWI401781B publication Critical patent/TWI401781B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01904—Manufacture or treatment of bond pads using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/344—Dispositions of die-attach connectors, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/953—Materials of bond pads not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Micromachines (AREA)
TW100113585A 2010-11-15 2011-04-19 藉由嵌入跡線界定之導電墊 TWI401781B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100113272A KR101059490B1 (ko) 2010-11-15 2010-11-15 임베드된 트레이스에 의해 구성된 전도성 패드
US12/963,938 US8432045B2 (en) 2010-11-15 2010-12-09 Conductive pads defined by embedded traces

Publications (2)

Publication Number Publication Date
TW201218346A TW201218346A (en) 2012-05-01
TWI401781B true TWI401781B (zh) 2013-07-11

Family

ID=44933774

Family Applications (2)

Application Number Title Priority Date Filing Date
TW100113585A TWI401781B (zh) 2010-11-15 2011-04-19 藉由嵌入跡線界定之導電墊
TW101144063A TWI482255B (zh) 2010-11-15 2011-04-19 藉由嵌入跡線界定之導電墊

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW101144063A TWI482255B (zh) 2010-11-15 2011-04-19 藉由嵌入跡線界定之導電墊

Country Status (6)

Country Link
US (2) US8432045B2 (https=)
JP (1) JP2014503992A (https=)
KR (1) KR101059490B1 (https=)
CN (1) CN103299419B (https=)
TW (2) TWI401781B (https=)
WO (1) WO2012067992A2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009018434B4 (de) * 2009-04-22 2023-11-30 Ev Group Gmbh Aufnahmeeinrichtung zur Aufnahme von Halbleitersubstraten
WO2016159245A1 (ja) * 2015-03-31 2016-10-06 株式会社ＮｅｊｉＬａｗ 通電路付部材及び通電路のパターニング方法、部材変化計測方法
US9653419B2 (en) 2015-04-08 2017-05-16 Intel Corporation Microelectronic substrate having embedded trace layers with integral attachment structures
CN104752443B (zh) * 2015-04-20 2016-03-02 京东方科技集团股份有限公司 衬底载板、柔性显示面板及相应的制作方法、柔性显示装置
US10080290B2 (en) * 2015-11-17 2018-09-18 Intel Corporation Stretchable embedded electronic package
EP3252873B1 (en) 2016-06-02 2019-07-24 TE Connectivity Germany GmbH Lubricated contact element and method for production thereof
TWI736093B (zh) 2019-12-31 2021-08-11 財團法人工業技術研究院 封裝結構

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200406884A (en) * 2002-10-30 2004-05-01 Intelligent Sources Dev Corp Method of forming a stacked-gate cell structure and its NAND-type flash memory array
TW200522274A (en) * 2003-12-26 2005-07-01 Intelligent Sources Dev Corp Paired stack-gate flash cell structure and its contactless nand-type flash memory arrays
TW200535435A (en) * 2004-03-29 2005-11-01 Applied Materials Inc High throughput measurement of via defects in interconnects

Family Cites Families (136)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160645A (ja) 1984-02-01 1985-08-22 Hitachi Ltd 積層半導体集積回路装置
NL8403613A (nl) 1984-11-28 1986-06-16 Philips Nv Elektronenbundelinrichting en halfgeleiderinrichting voor een dergelijke inrichting.
US4765864A (en) 1987-07-15 1988-08-23 Sri International Etching method for producing an electrochemical cell in a crystalline substrate
JPH03285338A (ja) * 1990-04-02 1991-12-16 Toshiba Corp ボンディングパッド
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
IL110261A0 (en) 1994-07-10 1994-10-21 Schellcase Ltd Packaged integrated circuit
GB2292015B (en) * 1994-07-29 1998-07-22 Plessey Semiconductors Ltd Trimmable inductor structure
US5703408A (en) * 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof
US6013948A (en) 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US5686762A (en) * 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
JP2904086B2 (ja) * 1995-12-27 1999-06-14 日本電気株式会社 半導体装置およびその製造方法
TW343210B (en) 1996-01-12 1998-10-21 Matsushita Electric Works Ltd Process for impregnating a substrate, impregnated substrate and products thereof
JP3699237B2 (ja) * 1996-03-13 2005-09-28 セイコーインスツル株式会社 半導体集積回路
US5808874A (en) 1996-05-02 1998-09-15 Tessera, Inc. Microelectronic connections with liquid conductive elements
US5700735A (en) * 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
JP3620936B2 (ja) 1996-10-11 2005-02-16 浜松ホトニクス株式会社 裏面照射型受光デバイスおよびその製造方法
US5791911A (en) * 1996-10-25 1998-08-11 International Business Machines Corporation Coaxial interconnect devices and methods of making the same
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
US6136458A (en) * 1997-09-13 2000-10-24 Kabushiki Kaisha Toshiba Ferrite magnetic film structure having magnetic anisotropy
US6573609B2 (en) 1997-11-25 2003-06-03 Tessera, Inc. Microelectronic component with rigid interposer
EP0926723B1 (en) 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
JP4651815B2 (ja) * 1998-01-23 2011-03-16 ローム株式会社 ダマシン配線および半導体装置
US6982475B1 (en) 1998-03-20 2006-01-03 Mcsp, Llc Hermetic wafer scale integrated circuit structure
US5986343A (en) 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
US6492201B1 (en) 1998-07-10 2002-12-10 Tessera, Inc. Forming microelectronic connection components by electrophoretic deposition
US6555913B1 (en) * 1998-07-17 2003-04-29 Murata Manufacturing Co., Ltd. Electronic component having a coil conductor with photosensitive conductive paste
TW386279B (en) * 1998-08-07 2000-04-01 Winbond Electronics Corp Inductor structure with air gap and method of manufacturing thereof
US6103552A (en) 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6261865B1 (en) 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
JP2000195896A (ja) * 1998-12-25 2000-07-14 Nec Corp 半導体装置
US6181016B1 (en) * 1999-06-08 2001-01-30 Winbond Electronics Corp Bond-pad with a single anchoring structure
US6368410B1 (en) 1999-06-28 2002-04-09 General Electric Company Semiconductor processing article
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
US6277669B1 (en) 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
JP3684978B2 (ja) 2000-02-03 2005-08-17 セイコーエプソン株式会社 半導体装置およびその製造方法ならびに電子機器
US6498387B1 (en) 2000-02-15 2002-12-24 Wen-Ken Yang Wafer level package and the process of the same
US6586955B2 (en) 2000-03-13 2003-07-01 Tessera, Inc. Methods and structures for electronic probing arrays
JP3879816B2 (ja) 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
US6472247B1 (en) 2000-06-26 2002-10-29 Ricoh Company, Ltd. Solid-state imaging device and method of production of the same
US6693358B2 (en) 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
EP1207015A3 (en) 2000-11-17 2003-07-30 Keltech Engineering, Inc. Raised island abrasive, method of use and lapping apparatus
US20020098620A1 (en) 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
KR100352236B1 (ko) 2001-01-30 2002-09-12 삼성전자 주식회사 접지 금속층을 갖는 웨이퍼 레벨 패키지
WO2002063681A1 (fr) 2001-02-08 2002-08-15 Hitachi, Ltd. Dispositif de circuit integre a semi-conducteur et son procede de fabrication
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
JP2002270718A (ja) 2001-03-07 2002-09-20 Seiko Epson Corp 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
US6531384B1 (en) * 2001-09-14 2003-03-11 Motorola, Inc. Method of forming a bond pad and structure thereof
US20030059976A1 (en) 2001-09-24 2003-03-27 Nathan Richard J. Integrated package and methods for making same
US6727576B2 (en) 2001-10-31 2004-04-27 Infineon Technologies Ag Transfer wafer level packaging
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW517361B (en) 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
US6743660B2 (en) 2002-01-12 2004-06-01 Taiwan Semiconductor Manufacturing Co., Ltd Method of making a wafer level chip scale package
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
JP2003318178A (ja) 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US7030010B2 (en) 2002-08-29 2006-04-18 Micron Technology, Inc. Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures
US6903442B2 (en) 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US7329563B2 (en) 2002-09-03 2008-02-12 Industrial Technology Research Institute Method for fabrication of wafer level package incorporating dual compliant layers
US20040104454A1 (en) 2002-10-10 2004-06-03 Rohm Co., Ltd. Semiconductor device and method of producing the same
US20050012225A1 (en) 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
JP4072677B2 (ja) 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
SG137651A1 (en) 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
JP3680839B2 (ja) 2003-03-18 2005-08-10 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
EP1519410A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
JP4373695B2 (ja) 2003-04-16 2009-11-25 浜松ホトニクス株式会社 裏面照射型光検出装置の製造方法
DE10319538B4 (de) 2003-04-30 2008-01-17 Qimonda Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
EP1482553A3 (en) 2003-05-26 2007-03-28 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
US9530857B2 (en) 2003-06-20 2016-12-27 Tessera Advanced Technologies, Inc. Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect
JP4499386B2 (ja) 2003-07-29 2010-07-07 浜松ホトニクス株式会社 裏面入射型光検出素子の製造方法
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7180149B2 (en) 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
JP2005093486A (ja) 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
GB2406720B (en) * 2003-09-30 2006-09-13 Agere Systems Inc An inductor formed in an integrated circuit
TWI259564B (en) 2003-10-15 2006-08-01 Infineon Technologies Ag Wafer level packages for chips with sawn edge protection
US20050156330A1 (en) 2004-01-21 2005-07-21 Harris James M. Through-wafer contact to bonding pad
US7368695B2 (en) 2004-05-03 2008-05-06 Tessera, Inc. Image sensor package and fabrication method
JP2005347442A (ja) * 2004-06-02 2005-12-15 Sanyo Electric Co Ltd 半導体装置
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
KR100605314B1 (ko) 2004-07-22 2006-07-28 삼성전자주식회사 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지의 제조 방법
US7750487B2 (en) 2004-08-11 2010-07-06 Intel Corporation Metal-metal bonding of compliant interconnect
US7378342B2 (en) 2004-08-27 2008-05-27 Micron Technology, Inc. Methods for forming vias varying lateral dimensions
US7129567B2 (en) 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
KR100604049B1 (ko) 2004-09-01 2006-07-24 동부일렉트로닉스 주식회사 반도체 칩 패키지 및 그 제조방법
JP4139803B2 (ja) 2004-09-28 2008-08-27 シャープ株式会社 半導体装置の製造方法
KR100676493B1 (ko) 2004-10-08 2007-02-01 디엔제이 클럽 인코 재배선 기판을 이용한 웨이퍼 레벨 칩 스케일 패키지의제조 방법
US7081408B2 (en) 2004-10-28 2006-07-25 Intel Corporation Method of creating a tapered via using a receding mask and resulting structure
JP4873517B2 (ja) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
KR20060087273A (ko) 2005-01-28 2006-08-02 삼성전기주식회사 반도체 패키지및 그 제조방법
US7675153B2 (en) 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US7538032B2 (en) 2005-06-23 2009-05-26 Teledyne Scientific & Imaging, Llc Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method
TWI264807B (en) 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI244186B (en) 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US20060264029A1 (en) 2005-05-23 2006-11-23 Intel Corporation Low inductance via structures
JP4694305B2 (ja) 2005-08-16 2011-06-08 ルネサスエレクトロニクス株式会社 半導体ウエハの製造方法
US20070049470A1 (en) 2005-08-29 2007-03-01 Johnson Health Tech Co., Ltd. Rapid circuit training machine with dual resistance
US20070052050A1 (en) 2005-09-07 2007-03-08 Bart Dierickx Backside thinned image sensor with integrated lens stack
JP2007157844A (ja) 2005-12-01 2007-06-21 Sharp Corp 半導体装置、および半導体装置の製造方法
US7456479B2 (en) * 2005-12-15 2008-11-25 United Microelectronics Corp. Method for fabricating a probing pad of an integrated circuit chip
US20080002460A1 (en) 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
KR100837269B1 (ko) 2006-05-22 2008-06-11 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조 방법
KR100764055B1 (ko) * 2006-09-07 2007-10-08 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 칩 스케일 패키지의 제조방법
JP2008091632A (ja) 2006-10-02 2008-04-17 Manabu Bonshihara 半導体装置の外部回路接続部の構造及びその形成方法
US7719121B2 (en) 2006-10-17 2010-05-18 Tessera, Inc. Microelectronic packages and methods therefor
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US7807508B2 (en) 2006-10-31 2010-10-05 Tessera Technologies Hungary Kft. Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US20080136038A1 (en) 2006-12-06 2008-06-12 Sergey Savastiouk Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate
JP2008147601A (ja) * 2006-12-13 2008-06-26 Yoshihiro Shimada フリップチップ接合方法及び半導体装置の製造方法
FR2911006A1 (fr) * 2007-01-03 2008-07-04 St Microelectronics Sa Puce de circuit electronique integre comprenant une inductance
JP2008177249A (ja) 2007-01-16 2008-07-31 Sharp Corp 半導体集積回路のボンディングパッド、その製造方法、半導体集積回路、並びに電子機器
EP2135280A2 (en) 2007-03-05 2009-12-23 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
JP2008258258A (ja) 2007-04-02 2008-10-23 Sanyo Electric Co Ltd 半導体装置
US20080284041A1 (en) 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
JP4937842B2 (ja) 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7767497B2 (en) 2007-07-12 2010-08-03 Tessera, Inc. Microelectronic package element and method of fabricating thereof
EP2183770B1 (en) 2007-07-31 2020-05-13 Invensas Corporation Method of forming through-substrate vias and corresponding decvice
KR101387701B1 (ko) 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
US7902069B2 (en) 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
KR100885924B1 (ko) 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
JP2009088201A (ja) 2007-09-28 2009-04-23 Nec Electronics Corp 半導体装置
US7446036B1 (en) 2007-12-18 2008-11-04 International Business Machines Corporation Gap free anchored conductor and dielectric structure and method for fabrication thereof
US20090212381A1 (en) 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US7842548B2 (en) * 2008-04-22 2010-11-30 Taiwan Semconductor Manufacturing Co., Ltd. Fixture for P-through silicon via assembly
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
JP5183340B2 (ja) 2008-07-23 2013-04-17 日本電波工業株式会社 表面実装型の発振器およびこの発振器を搭載した電子機器
US8932906B2 (en) * 2008-08-19 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via bonding structure
US7939926B2 (en) 2008-12-12 2011-05-10 Qualcomm Incorporated Via first plus via last technique for IC interconnects
TWI366890B (en) 2008-12-31 2012-06-21 Ind Tech Res Inst Method of manufacturing through-silicon-via and through-silicon-via structure
KR20100087566A (ko) 2009-01-28 2010-08-05 삼성전자주식회사 반도체 소자 패키지의 형성방법
US8697569B2 (en) 2010-07-23 2014-04-15 Tessera, Inc. Non-lithographic formation of three-dimensional conductive elements

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200406884A (en) * 2002-10-30 2004-05-01 Intelligent Sources Dev Corp Method of forming a stacked-gate cell structure and its NAND-type flash memory array
TW200522274A (en) * 2003-12-26 2005-07-01 Intelligent Sources Dev Corp Paired stack-gate flash cell structure and its contactless nand-type flash memory arrays
TW200535435A (en) * 2004-03-29 2005-11-01 Applied Materials Inc High throughput measurement of via defects in interconnects

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