JP2014503992A - 埋込みトレースによって画定される導電性パッド - Google Patents
埋込みトレースによって画定される導電性パッド Download PDFInfo
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- JP2014503992A JP2014503992A JP2013538966A JP2013538966A JP2014503992A JP 2014503992 A JP2014503992 A JP 2014503992A JP 2013538966 A JP2013538966 A JP 2013538966A JP 2013538966 A JP2013538966 A JP 2013538966A JP 2014503992 A JP2014503992 A JP 2014503992A
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Abstract
【選択図】図15
Description
本出願は、2010年11月15日に出願の韓国特許出願第10−2010−0113272号からの優先権を主張し、その特許出願の開示内容は引用することにより本明細書の一部をなすものとする。
露出した面を有する誘電体領域を含む第1の構成要素と、
前記第1の構成要素と第2の構成要素との電気的相互接続を可能にする前記面における導電性パッドであって、該導電性パッドは導電性素子によって画定され、該導電性素子は前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、理論直線が前記経路の少なくとも3つのセグメントに交差するようになっており、前記導電性素子の少なくとも2つの隣接セグメントは、前記導電性素子によって覆われていない前記面の一部分によって分離され、前記導電性素子は、前記面から該面の上の或る高さの上面まで延在し、該高さの少なくとも10倍の前記面に沿った長さを有する、導電性パッドと、
前記導電性パッドに接合された、300℃未満の融解温度を有する導電性結合材料であって、前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、導電性結合材料と
を備えてなり、前記導電性素子は前記上面から離れるように延在するエッジ面を有し、前記導電性結合材料は前記導電性素子の前記上面及び前記エッジ面に接触する、アセンブリである。
露出した面を有する誘電体領域を含む第1の構成要素と、
前記面に沿って延在し、少なくとも一部分が前記面に沿って湾曲した経路内に延在する連続した溝であって、前記面の下に配置された床面を有する、連続した溝と、
前記第1の構成要素と第2の構成要素との電気的相互接続を可能にする前記面において露出した導電性パッドであって、該導電性パッドは導電性素子によって画定され、該導電性素子は前記溝によって少なくとも部分的に画定された断面寸法を有し、前記溝の前記床面から該床面の上の或る高さまで延在し、前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、理論直線が前記経路の少なくとも3つのセグメントに交差するようになっており、前記導電性素子は、前記誘電体領域の前記面の露出した部分によって分離された少なくとも2つの隣接セグメントを有し、前記導電性素子は前記高さの少なくとも10倍の前記面に沿った長さを有する、導電性パッドと、
前記導電性パッドに接合された、300℃未満の融解温度を有する導電性結合材料であって、前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、導電性結合材料と
を備えてなる、アセンブリである。
(a)第1の構成要素の誘電体領域の一部分を除去することによって、該誘電体領域の露出した面に沿って延在する連続した溝を形成するステップであって、前記溝は少なくとも一部分が湾曲した経路内に延在し、前記溝は前記面の下に配置された床面を有する、溝を形成するステップと、
(b)前記第1の構成要素と第2の構成要素との電気的相互接続を可能にする前記面において露出した導電性パッドを形成するステップであって、該導電性パッドは導電性素子によって画定され、該導電性素子は、前記溝の前記経路によって少なくとも部分的に画定された断面寸法及び経路を有し、前記溝の前記床面から該床面の上の或る高さまで延在し、前記導電性素子は、前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、理論直線が前記経路の少なくとも3つのセグメントに交差するようになっており、前記導電性素子は、前記面の一部分によって分離された少なくとも2つの隣接セグメントを有し、前記導電性素子は前記高さの少なくとも10倍の前記面に沿った長さを有し、前記導電性素子は少なくとも部分的に前記溝内に埋め込まれる、形成するステップと、
(c)以下のステップのうちの少なくとも一方、すなわち、
300℃未満の融解温度を有する導電性結合材料を前記導電性パッドに塗布するステップであって、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、塗布するステップ、又は、
前記構成要素を前記第2の構成要素と組立てるステップであって、300℃未満の融解温度を有する導電性結合材料が前記導電性パッドを前記第2の構成要素の導電性パッドと接合し、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記誘電体領域の前記面の前記露出した部分をブリッジする、組立てるステップのうちの少なくとも一方を実行するステップと
を含んでなる方法である。
(a)マンドレルの平面上に導電性パッドをめっきするステップであって、前記導電性パッドは導電性素子によって画定され、該導電性素子は、前記面に沿って延在し、前記面に沿って湾曲した経路に少なくとも一部分が延在している、めっきするステップと、
(b)前記導電性パッドを少なくとも部分的に誘電体材料に埋め込むステップと、
(c)前記マンドレルを除去するステップであって、誘電体領域と該誘電体領域の面において露出した前記導電性パッドとを有する第1の構成要素を形成し、該第1の構成要素と第2の構成要素との電気的相互接続を可能にし、該導電性パッドの前記導電性素子は、前記誘電体領域の前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、理論直線が前記経路の少なくとも3つのセグメントに交差するようになっており、前記導電性素子は、前記誘電体領域の前記面の一部分によって分離された該導電性素子の少なくとも2つの隣接セグメントを有し、前記誘電体領域の前記面の少なくとも一部分が前記少なくとも2つのセグメント間で露出され、前記導電性素子は前記高さの少なくとも10倍の前記誘電体領域の前記面に沿った長さを有する、除去するステップと、
(d)以下のステップのうちの少なくとも一方、すなわち、
300℃未満の融解温度を有する導電性結合材料を前記導電性パッドに塗布するステップであって、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、塗布するステップ、又は
前記構成要素を前記第2の構成要素と組立てるステップであって、300℃未満の融解温度を有する導電性結合材料が前記導電性パッドを前記第2の構成要素の導電性パッドと接合し、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記誘電体領域の前記面の前記露出した部分をブリッジする、組立てるステップのうちの少なくとも一方を実行するステップと
を含んでなる方法である。
(a)導電性パッドを有するリードフレームを設けるステップであって、該導電性パッドは導電性素子によって画定され、該導電性素子は前記面に沿って延在し、前記面に沿って湾曲した経路に少なくとも一部分が延在している、設けるステップと、
(b)前記リードフレームを少なくとも部分的に誘電体材料に埋め込むステップと、
ここで、前記導電性パッドは前記構成要素と第2の構成要素との電気的相互接続を可能にするために前記誘電体材料の面において露出することができ、前記導電性パッドの前記導電性素子は、前記誘電体領域の前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、理論直線が前記経路の少なくとも3つのセグメントに交差するようになっており、前記導電性素子は、前記誘電体領域の前記面の一部分によって分離された該導電性素子の少なくとも2つの隣接セグメントを有し、前記誘電体領域の前記面の少なくとも一部分が前記少なくとも2つのセグメント間で露出され、前記導電性素子は前記高さの少なくとも10倍の前記誘電体領域の前記面に沿った長さを有することができ、
(c)以下のステップのうちの少なくとも一方、すなわち、
300℃未満の融解温度を有する導電性結合材料を前記導電性パッドに塗布するステップであって、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記面の前記部分をブリッジする、塗布するステップ、又は
前記構成要素を前記第2の構成要素と組立てるステップであって、300℃未満の融解温度を有する導電性結合材料が前記導電性パッドを前記第2の構成要素の導電性パッドと接合し、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記誘電体領域の前記面の前記露出した部分をブリッジする、組立てるステップのうちの少なくとも一方を実行するステップと
を含んでなる、構成要素アセンブリを形成する方法である。
Claims (68)
- アセンブリであって、
露出した面を有する誘電体領域を含む第1の構成要素と、
前記第1の構成要素と第2の構成要素との電気的相互接続を可能にする前記面における導電性パッドであって、該導電性パッドは導電性素子によって画定され、該導電性素子は前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、前記経路の少なくとも3つのセグメントに理論直線が交差するようになっており、前記導電性素子の少なくとも2つの隣接セグメントは、前記導電性素子によって覆われていない前記面の一部分によって分離され、前記導電性素子は、前記面から該面の上の或る高さの上面まで延在し、該高さの少なくとも10倍の前記面に沿った長さを有する、導電性パッドと、
前記導電性パッドに接合された、300℃未満の融解温度を有する導電性結合材料であって、前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、導電性結合材料と
を備えてなり、
前記導電性素子は前記上面から離れるように延在するエッジ面を有し、前記導電性結合材料は前記導電性素子の前記上面及び前記エッジ面に接触するものである、アセンブリ。 - 前記結合材料を通じて前記導電性パッドに接合された端子を有する前記第2の構成要素を更に備える、請求項1に記載のアセンブリ。
- 前記導電性素子の前記経路は、該経路自体に重なることも交差することもない、請求項1に記載のアセンブリ。
- 前記導電性素子の前記経路は、該経路自体に重なるか又は交差するかのうちの少なくとも一方となる、請求項1に記載のアセンブリ。
- 前記導電性素子は、前記パッドの最も外側のエッジによって画定された円形の境界内の前記誘電体領域の前記面の面積の75パーセント未満を占める、請求項1に記載のアセンブリ。
- 前記第1の構成要素は基板面を有する基板を更に備え、前記誘電体領域は前記基板面の上に少なくとも部分的に重なる、請求項1に記載のアセンブリ。
- 前記基板面は前記基板の上面であり、前記基板は、前記上面から離れた底面と、前記上面と前記底面との間に延在する開口部と、前記底面に配置された第2の導電性素子とを更に有し、前記パッドは前記基板の前記開口部及び前記誘電体領域の開口部を通って前記第2の導電性素子に電気的に接続される、請求項6に記載のアセンブリ。
- 前記誘電体領域の前記面は前記第1の構成要素の前記露出した面に露出しており、前記第1の構成要素は、前記露出した面から離れた底面と、前記上面と前記底面との間に延在する開口部と、前記底面に配置された第2の導電性素子とを更に有し、前記パッドは、前記第1の構成要素の前記開口部及び前記誘電体領域の開口部を通って前記第2の導電性素子に電気的に接続される、請求項1に記載のアセンブリ。
- 前記露出した面は裏面であり、前記第1の構成要素は前記裏面から離れた表面と、前記表面と前記裏面との間に延在する開口部とを有し、前記導電性素子は前記裏面に露出され、前記導電性素子の少なくとも一部分が前記開口部の内面に沿って延在する、請求項1に記載のアセンブリ。
- 前記第1の構成要素は前記表面において少なくとも1つのコンタクトを有し、前記少なくとも1つのコンタクトと前記導電性素子との間の電気的な接続は前記開口部を通じて行われる、請求項9に記載のアセンブリ。
- 前記第1の構成要素は、前記表面に隣接した複数のアクティブな半導体デバイスを有する超小型電子素子である、請求項10に記載のアセンブリ。
- 前記第1の構成要素は、前記面において複数のコンタクトを有する超小型電子素子であり、前記導電性パッドを前記複数のコンタクトのうちの少なくとも1つと電気的に接続するトレースを更に備える、請求項1に記載のアセンブリ。
- 前記第1の構成要素は上に複数のトレースを有する誘電体素子であり、前記導電性パッドは前記トレースのうちの少なくとも1つに電気的に接続される、請求項1に記載のアセンブリ。
- 前記面は第1の面であり、前記第1の構成要素は前記第1の面から離れた第2の面において複数のコンタクトを有する超小型電子素子であり、前記導電性パッドは前記複数のコンタクトのうちの少なくとも1つに電気的に接続される、請求項1に記載のアセンブリ。
- 前記結合材料ははんだである、請求項1に記載のアセンブリ。
- 前記パッドはニッケル又は金のうちの少なくとも一方を含む表面層を含み、前記結合材料が該表面層に接触している、請求項1に記載のアセンブリ。
- 請求項1に記載のアセンブリを備え、1つ以上の他の電子構成要素が前記アセンブリに電気的に接続される、システム。
- ハウジングと、前記アセンブリと、前記ハウジングに実装された前記他の電子構成要素とを更に備える、請求項17に記載のシステム。
- アセンブリであって、
露出した面を有する誘電体領域を含む第1の構成要素と、
前記面に沿って延在し、少なくとも一部分が前記面に沿って湾曲した経路内に延在する連続した溝であって、前記面の下に配置された床面を有する、連続した溝と、
前記第1の構成要素と第2の構成要素との電気的相互接続を可能にする前記面において露出した導電性パッドであって、該導電性パッドは導電性素子によって画定され、該導電性素子は前記溝によって少なくとも部分的に画定された断面寸法を有し、前記溝の前記床面から該床面の上の或る高さまで延在し、前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、前記経路の少なくとも3つのセグメントに理論直線が交差するようになっており、前記導電性素子は、前記誘電体領域の前記面の露出した部分によって分離された少なくとも2つの隣接セグメントを有し、前記導電性素子は前記高さの少なくとも10倍の前記面に沿った長さを有する、導電性パッドと、
前記導電性パッドに接合された、300℃未満の融解温度を有する導電性結合材料であって、前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、導電性結合材料と
を備えてなる、アセンブリ。 - 前記第1の構成要素はその前記面における複数のコンタクトと該面に隣接した複数のアクティブな半導体デバイスとを有する超小型電子素子であり、前記アセンブリは前記導電性パッドを前記複数のコンタクトのうちの少なくとも1つと電気的に接続するトレースを更に備える、請求項19に記載のアセンブリ。
- 前記第1の構成要素はその上に複数のトレースを有する誘電体素子であり、前記導電性パッドは前記トレースのうちの少なくとも1つと電気的に接続される、請求項19に記載のアセンブリ。
- 前記面は第1の面であり、前記第1の構成要素は前記第1の面から離れた第2の面における複数のコンタクトと該第2の面に隣接する複数のアクティブな半導体デバイスとを有する超小型電子素子であり、前記導電性パッドは前記複数のコンタクトのうちの少なくとも1つと電気的に接続される、請求項19に記載のアセンブリ。
- 前記第2の構成要素を更に備え、前記結合材料は前記導電性パッドを前記第2の構成要素の端子と接合している、請求項19〜22のいずれかに記載のアセンブリ。
- 前記結合材料ははんだである、請求項19に記載のアセンブリ。
- 前記第1の構成要素は前記表面と前記裏面との間に延在する開口部を含み、前記導電性素子の少なくとも一部分が前記開口部の内面に沿って延在し、前記溝の少なくとも一部分が前記内面に沿って延在し、前記導電性素子は前記溝の前記部分内に延在する、請求項19に記載のアセンブリ。
- 前記少なくとも1つのコンタクトと前記導電性素子との間の電気接続は前記開口部を通じて行われる、請求項25に記載のアセンブリ。
- 前記導電性素子の前記高さは、前記誘電体領域の前記床面と前記面との間の距離よりも大きい、請求項19に記載のアセンブリ。
- 前記導電性素子の前記高さは、前記誘電体領域の前記床面と前記面との間の距離以下である、請求項19に記載のアセンブリ。
- 前記パッドの最も外側のエッジが前記面に対して円形又は正方形の形状の境界を画定する、請求項19に記載のアセンブリ。
- 前記導電性素子の前記経路は、該経路自体に重なることも交差することもない、請求項29に記載のアセンブリ。
- 前記導電性素子の前記経路は、該経路自体に重なるか又は交差するかのうちの少なくとも一方となる、請求項29に記載のアセンブリ。
- 前記導電性素子は、前記境界内の前記面の表面積の75パーセント未満を占める、請求項29に記載のアセンブリ。
- 前記導電性素子の前記高さは前記床面と前記面との間の距離よりも大きく、それによって前記導電性素子は前記誘電体領域の前記面において露出した上面と該上面から離れるように延在するエッジ面とを有し、前記結合材料は前記導電性素子の前記上面及び前記エッジ面に接触する、請求項19に記載のアセンブリ。
- 前記パッドはニッケル又は金の少なくとも一方を含む表面層を含む、請求項19に記載のアセンブリ。
- 前記誘電体領域の前記面は前記第1の構成要素の前記露出した面において露出され、前記第1の構成要素は前記露出した面と反対側の底面を更に有し、前記露出した面と前記底面との間に開口部が延在し、前記底面の上に第2の導電性素子が重なり、前記パッドは前記第1の構成要素内の前記開口部及び前記誘電体領域内の開口部を通じて前記第2の導電性素子に電気的に接続される、請求項19に記載のアセンブリ。
- 前記誘電体領域ははんだマスクを含む、請求項19に記載のアセンブリ。
- 前記誘電体領域は高分子材料である、請求項19に記載のアセンブリ。
- 前記誘電体領域は無機材料である、請求項19に記載のアセンブリ。
- 前記誘電体領域は誘電体材料の2つ以上の積層を含み、そのうちの少なくとも2つの隣接する層が異なる材料を含む、請求項19に記載のアセンブリ。
- 請求項19に記載のアセンブリを備え、1つ以上の他の電子構成要素が前記アセンブリに電気的に接続される、システム。
- ハウジングと、前記アセンブリと、前記ハウジングに実装された前記他の電子構成要素とを更に備える、請求項40に記載のシステム。
- 第1の構成要素上に導電性構造を形成する方法であって、
(a)第1の構成要素の誘電体領域の一部分を除去することによって、該誘電体領域の露出した面に沿って延在する連続した溝を形成するステップであって、前記溝は少なくとも一部分が湾曲した経路内に延在し、前記溝は前記面の下に配置された床面を有する、連続した溝を形成するステップと、
(b)前記第1の構成要素と第2の構成要素との電気的相互接続を可能にする前記面において露出した導電性パッドを形成するステップであって、該導電性パッドは導電性素子によって画定され、該導電性素子は、前記溝の前記経路によって少なくとも部分的に画定された断面寸法及び経路を有し、前記溝の前記床面から該床面の上の或る高さまで延在し、前記導電性素子は、前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、理論直線が前記経路の少なくとも3つのセグメントに交差するようになっており、前記導電性素子は、前記面の一部分によって分離された少なくとも2つの隣接セグメントを有し、前記導電性素子は前記高さの少なくとも10倍の前記面に沿った長さを有し、前記導電性素子は少なくとも部分的に前記溝内に埋め込まれる、導電性パッドを形成するステップと、
(c)以下のステップのうちの少なくとも一方、すなわち、
300℃未満の融解温度を有する導電性結合材料を前記導電性パッドに塗布するステップであって、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、塗布するステップ、又は
前記構成要素を前記第2の構成要素と組立てるステップであって、300℃未満の融解温度を有する導電性結合材料が前記導電性パッドを前記第2の構成要素の導電性パッドと接合し、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記誘電体領域の前記面の前記露出した部分をブリッジする、組立てるステップのうちの少なくとも一方を実行するステップと
を含んでなる、第1の構成要素上に導電性構造を形成する方法。 - 前記導電性素子の前記高さは前記床面と前記面との間の距離よりも大きい、請求項42に記載の方法。
- 前記導電性素子は、前記誘電体領域の前記面に平行な露出した上面と、該導電性素子の前記上面と前記誘電体領域の前記面との間に延在する露出した垂直面とを備え、前記結合材料は前記導電性素子の前記上面及び前記垂直面と接触する、請求項43に記載の方法。
- 前記導電性素子の前記高さは、前記床面と前記面との間の距離以下である、請求項42に記載の方法。
- 前記床面と前記面との間の距離は前記導電性素子の幅よりも大きい、請求項42に記載の方法。
- 前記ステップ(b)は、前記導電性素子が該導電性素子自体に重なることも交差することもないように該導電性素子を形成することを含む、請求項42に記載の方法。
- 前記ステップ(b)は、前記導電性素子が該導電性素子自体に重なるか又は交差するかのうちの少なくとも一方となるように該導電性素子を形成することを含む、請求項42に記載の方法。
- 前記ステップ(c)は、前記溝の少なくとも前記床面の上に重なる触媒層を形成することと、前記触媒層が存在するエリア上に金属を選択的に堆積することであって、前記導電性素子を形成することとを含む、請求項42に記載の方法。
- 前記結合材料は、少なくとも前記第1の構成要素の前記パッドの前記最も外側のエッジ間に延在する、請求項42に記載の方法。
- 前記ステップ(b)は、前記第1の構成要素の前記パッドの面において露出したニッケル又は金のうちの少なくとも一方を含む表面層をめっきすることを含む、請求項42に記載の方法。
- 前記第1の構成要素は第2の領域を含み、前記ステップ(a)及び前記ステップ(b)が実行されるとき、前記誘電体領域は前記第2の領域の上に重なる、請求項42に記載の方法。
- 前記基板は前記上面と反対側の底面と、前記上面と前記底面との間を延在する開口部と、下側の面の上に重なる導電性素子とを有し、前記第1の構成要素の前記パッドは前記基板内の前記開口部及び前記誘電体領域内の隣接する開口部を通じて前記導電性素子に電気的に接続される、請求項52に記載の方法。
- 前記ステップ(a)は、レーザを少なくとも前記面に向けて方向付けて前記誘電体領域の前記部分を焼灼すること、機械的フライス加工、又はサンドブラストのうちの少なくとも1つを含む処理によって実行される、請求項42に記載の方法。
- 前記ステップ(b)は、少なくとも1つの開口部を有する金属ステンシルを前記誘電体領域の上に重なるように位置決めすることと、前記少なくとも1つの開口部を通じて露出した前記誘電体領域の前記部分をサンドブラストによって除去することとを含む、請求項42に記載の方法。
- 前記ステップ(b)は、機械的フライス加工によって前記誘電体領域の一部分を除去することを含む、請求項42に記載の方法。
- 前記ステップ(b)は、前記誘電体領域の前記面と前記溝の少なくとも一部分との上に重なる導電性材料を堆積することと、前記面の少なくとも一部分の上に重なる前記導電性材料を除去することであって、前記誘電体領域の前記面を露出することとを含む、請求項42に記載の方法。
- 前記ステップ(c)は、前記導電性パッドに前記結合材料を塗布することを含み、該結合材料は、前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、請求項42に記載の方法。
- 前記ステップ(c)は、前記構成要素を前記第2の構成要素と組立てることを含み、前記結合材料は前記導電性パッドを前記第2の構成要素の前記導電性パッドと接合し、前記結合材料は前記少なくとも2つの隣接するセグメント間の前記誘電体領域の前記面の前記露出した部分をブリッジする、請求項42に記載の方法。
- 第1の構成要素アセンブリを形成する方法であって、
(a)マンドレルの平面上に導電性パッドをめっきするステップであって、前記導電性パッドは導電性素子によって画定され、該導電性素子は前記面に沿って延在し、前記面に沿って湾曲した経路に少なくとも一部分が延在する、めっきするステップと、
(b)前記導電性パッドを少なくとも部分的に誘電体材料に埋め込むステップと、
(c)前記マンドレルを除去するステップであって、誘電体領域と該誘電体領域の面において露出した前記導電性パッドとを有する第1の構成要素を形成し、該第1の構成要素と第2の構成要素との電気的相互接続を可能にし、該導電性パッドの前記導電性素子は、前記誘電体領域の前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、理論直線が前記経路の少なくとも3つのセグメントに交差するようになっており、前記導電性素子は、前記誘電体領域の前記面の一部分によって分離された該導電性素子の少なくとも2つの隣接セグメントを有し、前記誘電体領域の前記面の少なくとも一部分が前記少なくとも2つのセグメント間で露出され、前記導電性素子は前記高さの少なくとも10倍の前記誘電体領域の前記面に沿った長さを有する、除去するステップと、
(d)以下のステップのうちの少なくとも一方、すなわち、
300℃未満の融解温度を有する導電性結合材料を前記導電性パッドに塗布するステップであって、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、塗布するステップ、又は
前記構成要素を前記第2の構成要素と組立てるステップであって、300℃未満の融解温度を有する導電性結合材料が前記導電性パッドを前記第2の構成要素の導電性パッドと接合し、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記誘電体領域の前記面の前記露出した部分をブリッジする、組立てるステップのうちの少なくとも一方を実行するステップと
を含んでなる、第1の構成要素アセンブリを形成する方法。 - 前記マンドレルは金属シートを含み、前記ステップ(c)は前記金属シートをエッチングすることであって、前記第1の構成要素の前記パッドを露出させることを含む、請求項60に記載の方法。
- 前記ステップ(b)は、前記第1の構成要素の前記導電性パッドを、前記誘電体材料を含む少なくとも部分的に硬化した誘電体領域内に埋め込むことを含む、請求項60に記載の方法。
- 前記ステップ(b)は、前記誘電体材料を堆積することであって、前記第1の構成要素の前記導電性パッドの少なくとも一部分と接触させることを含む、請求項60に記載の方法。
- 前記ステップ(d)は、前記導電性パッドに前記結合材料を塗布することを含み、該結合材料は前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、請求項60に記載の方法。
- 前記ステップ(d)は、前記構成要素を前記第2の構成要素と組立てることを含み、前記結合材料は前記導電性パッドを前記第2の構成要素の前記導電性パッドと接合し、前記結合材料は前記少なくとも2つの隣接するセグメント間の前記誘電体領域の前記面の前記露出した部分をブリッジする、請求項60に記載の方法。
- 構成要素アセンブリを形成する方法であって、
(a)導電性パッドを有するリードフレームを設けるステップであって、該導電性パッドは導電性素子によって画定され、該導電性素子は前記面に沿って延在し、前記面に沿って湾曲した経路に少なくとも一部分が延在する、設けるステップと、
(b)前記リードフレームを少なくとも部分的に誘電体材料に埋め込むステップと、
ここで、前記導電性パッドは前記構成要素と第2の構成要素との電気的相互接続を可能にするために前記誘電体材料の面において露出され、前記導電性パッドの前記導電性素子は、前記誘電体領域の前記面に沿った振子様経路又は螺旋経路のうちの少なくとも一方に少なくとも一部分が延在し、前記経路の少なくとも3つのセグメントに理論直線が交差するようになっており、前記導電性素子は、前記誘電体領域の前記面の一部分によって分離された該導電性素子の少なくとも2つの隣接セグメントを有し、前記誘電体領域の前記面の少なくとも一部分が前記少なくとも2つのセグメント間で露出され、前記導電性素子は前記高さの少なくとも10倍の前記誘電体領域の前記面に沿った長さを有し、
(c)以下のステップのうちの少なくとも一方、すなわち、
300℃未満の融解温度を有する導電性結合材料を前記導電性パッドに塗布するステップであって、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記面の前記部分をブリッジする、塗布するステップ、又は
前記構成要素を前記第2の構成要素と組立てるステップであって、300℃未満の融解温度を有する導電性結合材料が前記導電性パッドを前記第2の構成要素の導電性パッドと接合し、前記導電性結合材料は前記少なくとも2つの隣接セグメント間で前記誘電体領域の前記面の前記露出した部分をブリッジする、組立てるステップのうちの少なくとも一方を実行するステップと
を含んでなる、構成要素アセンブリを形成する方法。 - 前記ステップ(c)は、前記導電性パッドに前記結合材料を塗布することを含み、該結合材料は前記少なくとも2つの隣接セグメント間で前記面の前記露出した部分をブリッジする、請求項66に記載の方法。
- 前記ステップ(c)は、前記構成要素を前記第2の構成要素と組立てることを含み、前記結合材料は前記導電性パッドを前記第2の構成要素の前記導電性パッドと接合し、前記結合材料は前記少なくとも2つの隣接するセグメント間の前記誘電体領域の前記面の前記露出した部分をブリッジする、請求項66に記載の方法。
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US8772908B2 (en) | 2014-07-08 |
CN103299419B (zh) | 2016-05-18 |
TW201312720A (zh) | 2013-03-16 |
KR101059490B1 (ko) | 2011-08-25 |
CN103299419A (zh) | 2013-09-11 |
TWI482255B (zh) | 2015-04-21 |
TW201218346A (en) | 2012-05-01 |
US20120119367A1 (en) | 2012-05-17 |
TWI401781B (zh) | 2013-07-11 |
WO2012067992A3 (en) | 2012-12-20 |
US8432045B2 (en) | 2013-04-30 |
WO2012067992A2 (en) | 2012-05-24 |
US20120306092A1 (en) | 2012-12-06 |
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