CN103299419A - 由嵌入式迹线限定的导电垫 - Google Patents

由嵌入式迹线限定的导电垫 Download PDF

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Publication number
CN103299419A
CN103299419A CN201180064944XA CN201180064944A CN103299419A CN 103299419 A CN103299419 A CN 103299419A CN 201180064944X A CN201180064944X A CN 201180064944XA CN 201180064944 A CN201180064944 A CN 201180064944A CN 103299419 A CN103299419 A CN 103299419A
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components
parts
conducting element
conductive pad
dielectric regions
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CN103299419B (zh
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贝勒卡西姆·哈巴
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

提供了组件(100)及制造组件的方法。组件(100)可包括第一元器件(105)，第一元器件包括具有暴露表面(122)的介电区域(120)、在表面(122)上由导电元件(132)限定的导电垫(134)、及与导电垫(134)接合的导电结合材料(140)，导电元件的至少一部分在振荡路径或螺旋路径中沿表面(122)延伸，导电结合材料与介电表面(122)的位于相邻段(136,138)之间的暴露部分(137)桥接。导电垫(134)可允许第一元器件(105)与具有端子(108)的第二元器件(107)电互连，端子与垫(134)通过导电结合材料(140)而接合。导电元件(132)的路径可自身重叠或横穿，或可不自身重叠或横穿。

Description

由嵌入式迹线限定的导电垫
相关申请的交叉引用
本发明要求申请号为10-2010-0113272、申请日为2010年11月15日的韩国专利申请的优先权，其公开的内容以引用的方式并入本文。
背景技术
本发明涉及微电子器件的形成，尤其是导电垫的形成。
微电子器件通常包括如硅或砷化镓等半导体材料的薄板，一般称为裸片或半导体芯片。半导体芯片一般设置为单独的预封装单元。在一些单元的设计中，半导体芯片安装至基板或芯片载体上，而基板或芯片载体再安装至如印刷电路板等的电路板上。
有源电路在半导体芯片的第一面（如正面）制备。为便于与有源电路的电连接，在芯片的同一面设置有结合垫。结合垫通常由如铜或铝等的导电金属制成，大约为0.5微米厚。结合垫可包括单层或多层的金属。结合垫的大小随器件类型而变化，但典型地，在一侧的尺寸为几十微米至几百微米。
微电子器件通常安装在包括介电元件的封装内，介电元件具有如端子或其他导电垫等的一组导电元件。封装芯片或在某些情况下裸芯片可安装至电路板，并与电路板的导电垫电互连。典型地，这种介电元件或电路板上的导电垫可通过光栅法或光刻法而形成。这些过程可能伴有缺点。通过光栅法激光形成导电垫可能会生成表面不平的垫，因为每个随后的光栅段都与前段部分地重叠。光刻法可能效率很低，尤其是当小批量生产时，用于特定应用或系统的最优化掩模的设计、测试、及校正可能是沉重的负担。
在芯片的任一几何布置中，尺寸是重要的考虑因素。随着便携式电子装置的快速发展，芯片的更紧凑几何布置的需求变得更为强烈。仅以示例的方式说明，通常称为“智能手机”的装置，集成了移动电话及强大的数据处理器、存储器、如全球定位系统接收器、数码相机等的辅助器件等的功能，以及局域网连接，并伴有高分辨率的显示及相关的图像处理芯片。这种装置可提供如完整的互联网连接、包括高清视频等的娱乐、导航、电子银行及更多的性能，都设置在袖珍式的装置内。复杂的便携装置要求把大量芯片包装至狭小的空间内。此外，一些芯片具有许多输入和输出接口，一般称为“I/O口”。这些I/O口必须与其他芯片的I/O口互连。这种互连应尽量短且应具有低的阻抗，以使信号传输延迟最小化。形成这些互连的元器件不应大幅度增加组件的尺寸。类似需求也出现在其他应用中，例如，数据服务器，如在互联网搜索引擎中使用的数据服务器。例如，在复杂芯片之间设置大量短且阻抗低的互连的结构，可增加搜索引擎的频带宽度（bandwidth），并降低其能耗。
尽管在具有导电垫的元器件的制造方面，已作出或已提出了进展，但仍可以作出进一步的改善。
发明内容
本发明的第一方面为包括第一元器件的组件，第一元器件包括具有暴露表面的介电区域；表面上的导电垫允许第一元器件与第二元器件电互连，导电垫由导电元件限定，导电元件的至少一部分在振荡路径或螺旋路径中至少一种路径内沿表面延伸，使得理论直线与路径的至少三段相交，且导电元件的至少两个相邻段被表面的没有导电元件覆盖的一部分隔开，导电元件从表面延伸至表面上方一高度的顶面，且具有沿表面至少为高度十倍的长度；与导电垫接合的导电结合材料具有低于300℃的熔点，且与位于至少两个相邻段之间的表面暴露部分桥接，其中导电元件具有远离顶面延伸的边缘表面，且导电结合材料与导电元件的顶面及边缘表面都接触。
根据此第一方面的某些实施例，组件可进一步包括具有端子的第二元器件，端子与导电垫通过导电结合材料而接合。导电元件的路径可不自身重叠或横穿。导电元件的路径可至少自身重叠或横穿。导电元件所占据的面积可小于，介电区域位于垫最外边缘所限定的圆形边界内的表面积的百分之七十五。第一元器件可进一步包括具有基板表面的基板，介电区域至少部分地覆盖基板表面。基板表面可为基板的顶面，基板进一步具有远离顶面的底面、在顶面与底面之间延伸的开口、及设置底面上的第二导电元件，垫与第二导电元件通过基板内的开口及介电区域内的开口而连接。
介电区域的表面可暴露在第一元器件的暴露表面上，第一元器件进一步具有远离暴露表面的底面、在顶面与底面之间延伸的开口、及设置在底面上的第二导电元件，垫与第二导电元件穿过第一元件内的开口及介电区域内的开口而电连接。暴露表面可为背面，第一元器件可具有远离背面的正面、及在正面与背面之间延伸的开口，其中导电元件在背面暴露，且导电元件的至少一部分沿开口的内表面延伸。第一元器件可具有在正面上的至少一个触点，其中至少一个触点与导电元件之间的电连接可通过开口而实现。第一元器件可为微电子元件，具有邻近正面的复数个有源半导体器件。
第一元器件可为在表面上具有复数个触点的微电子元件，且组件可进一步包括使导电垫与复数个触点中至少一个电连接的迹线。第一元器件可为其上具有复数条迹线的介电元件，其中导电垫与至少一条迹线电连接。表面可为第一表面，第一元器件可为微电子元件，具有在远离第一表面的第二表面上的复数个触点，导电垫可与复数个触点中至少一个电连接。导电结合材料可为焊料。垫可包括含有镍或金中至少一种的表面层，且导电结合材料与表面层接触。系统可包括上述的组件及一个或多个与组件电连接的其他电子元器件。系统可进一步包括外壳，组件及其他电子元器件安装至外壳。
本发明的第二方面为包括第一元器件的组件，第一元器件包括具有暴露表面的介电区域；连续凹槽沿表面延伸，且其至少一部分沿表面在曲线路径内延伸，凹槽具有设置在表面下方的底部；导电垫在表面上暴露，允许第一元器件与第二元器件电互连，导电垫由导电元件限定，导电元件具有至少部分地由凹槽限定的横截面尺寸，并从凹槽的底部延伸至底部上方的高度，且其至少一部分在振荡路径或螺旋路径中的至少一条路径内沿表面延伸，使得理论直线与路径的至少三段相交，导电元件具有被介电区域表面的暴露部分隔开的至少两个相邻段，且导电元件具有沿表面至少为高度十倍的长度；熔点低于300℃的导电结合材料与导电垫接合，并与表面位于至少两个相邻段之间的暴露部分桥接。
根据第二方面的某些实施例，第一元器件可为微电子元件，具有在其表面上的复数个触点、及邻近表面的复数个有源半导体器件，组件可进一步包括使导电垫与复数个触点中至少一个电连接的迹线。第一元器件可为其上具有复数条迹线的介电元件，其中导电垫可与至少一条迹线电连接。表面可为第一表面，第一元器件可为微电子元件，具有在远离第一表面的第二表面上的复数个触点、及邻近第二表面的复数个有源半导体器件，且导电垫可与复数个触点中至少一个电连接。
组件可进一步包括第二元器件，导电结合材料使导电垫与第二元器件的端子接合。导电结合材料可为焊料。第一元器件可包括在正面与背面之间延伸的开口，导电元件的至少一部分沿开口的内表面延伸，凹槽的至少一部分沿内表面延伸，导电元件在凹槽的该部分内延伸。至少一个触点与导电元件之间的电连接可通过开口而实现。导电元件的高度可大于底部与介电区域表面之间的距离。导电元件的高度可等于或小于底部与介电区域表面之间的距离。
垫的最外边缘可对于表面限定圆形或方形的边界。导电元件的路径可不自身重叠或横穿。导电元件的路径可至少自身重叠或横穿。导电元件所占据的面积可小于位于边界内的表面面积的百分之七十五。导电元件的高度可大于底部与表面之间的距离，使得导电元件具有在介电区域表面暴露的顶面、及远离顶面而延伸的边缘表面，导电结合材料与导电元件的顶面及边缘表面都接触。垫可包括含有镍或金中至少一种的表面层。
介电区域的表面可暴露在第一元器件的暴露表面，第一元器件可进一步包括与暴露表面相对的底面、在暴露表面与底面之间延伸的开口、及覆盖底面的第二导电元件，垫与第二导电元件通过第一元器件内的开口及介电区域内的开口而电连接。介电区域可包括焊料掩模。介电区域可为聚合物材料。介电区域可为无机材料。介电区域可包括两层或更多层的介电材料堆叠层，至少两个相邻的层包括不同材料。系统可包括上述的组件及一个或多个与组件电连接的其他电子元器件。系统可进一步包括外壳，组件及其他电子元器件安装至外壳。
本发明的第三方面为在第一元器件上形成导电结构的方法，包括：（a）通过除去介电区域的一部分而形成沿第一元器件的介电区域的暴露表面延伸的连续凹槽，凹槽的至少一部分在曲线路径内延伸，凹槽具有位于表面下方的底部；（b）形成在表面暴露的导电垫，以允许第一元器件与第二元器件电互连，导电垫由导电元件限定，导电元件具有横截面尺寸、及至少部分由凹槽的路径所限定的路径，并从凹槽的底部延伸至底部上方的高度，导电元件的至少一部分在振荡路径或螺旋路径中至少一种路径内沿表面延伸，使得理论直线与路径的至少三段相交，导电元件具有被表面的一部分隔开的至少两个相邻段，导电元件具有沿表面至少为高度十倍的长度，导电元件至少部分地嵌入凹槽内；及（c）进行以下之一：在导电垫上施加熔点低于300℃的导电结合材料，导电结合材料与至少两个相邻段之间的表面暴露部分桥接；或组装该元器件与第二元器件，利用熔点低于300℃的导电结合材料，使导电垫与第二元器件的导电垫接合，导电结合材料与至少两个相邻段之间的介电区域的表面暴露部分桥接。
根据此第三方面的某些实施例，导电元件的高度可大于底部与表面之间的距离。导电元件可包括与介电区域的表面平行的暴露顶面、及在其顶面与介电区域的表面之间延伸的暴露竖直表面，导电结合材料与导电元件的顶面及竖直表面都接触。导电元件的高度可等于或小于底部与表面之间的距离。底部与表面之间的距离可大于导电元件的宽度。
步骤（b）可包括，形成导电元件，使得其不自身重叠或横穿。步骤（b）可包括，形成导电元件，使得其至少自身重叠或横穿。步骤（c）可包括，形成至少覆盖凹槽底部的催化剂层，然后在可能存在催化剂层的区域选择性地沉积金属，以形成导电元件。导电结合材料可至少在第一元器件的垫最远边缘之间延伸。步骤（b）可包括，电镀含有镍或金中至少一种的表面层，在第一元器件的垫表面暴露。
第一元器件可包括第二区域，当步骤（a）和步骤（b）进行时，介电区域覆盖第二区域。基板可具有与顶面相对的底面、在顶面与底面之间延伸的开口、及覆盖底面的导电元件，第一元器件的垫与导电元件通过基板内的开口与介电元件内的邻接开口而电连接。
步骤（a）可通过包括以下至少一种的过程而进行：至少朝表面引入激光以烧蚀介电区域的该部分、机械球磨、或喷砂。步骤（b）可包括，放置金属模板以覆盖介电区域，金属模板具有至少一个开口，并通过喷砂穿过至少一个开口除去介电区域的暴露部分。步骤（b）可包括，通过机械球磨除去介电区域的一部分。步骤（b）可包括，沉积覆盖介电区域表面及至少一部分凹槽的导电材料，并除去覆盖至少一部分表面的导电材料，以暴露介电区域的表面。
步骤（c）可包括，在导电垫上施加导电结合材料，导电结合材料与至少两个相邻段之间的表面暴露部分桥接。步骤（c）可包括，组装元器件与第二元器件，利用导电结合材料使导电垫与第二元器件的导电垫接合，导电结合材料与至少两相邻段之间的介电区域的表面暴露部分桥接。
本发明的第四方面为形成第一元器件组件的方法，该方法包括：（a）在芯模的平坦表面上电镀导电垫，导电垫由沿表面延伸的导电元件限定，且具有在曲线路径内沿表面延伸的至少一部分；（b）使导电垫至少部分地嵌入介电材料内；（c）去除芯模，以形成具有介电区域及导电垫的第一元器件，导电垫暴露在介电区域的表面，用于允许元器件与第二元器件电互连，导电垫的导电元件具有在振荡路径或螺旋路径中至少一种路径内沿介电区域的表面延伸的至少一部分，使得理论直线与路径的至少三段相交，导电元件具有被介电区域表面的一部分隔开的至少两个相邻段，介电区域表面的至少一部分在至少两个相邻段之间暴露，导电元件具有沿介电区域表面至少为高度十倍的长度；及（d）进行以下之一：在导电垫上施加熔点低于300℃的导电结合材料，导电结合材料与至少两个相邻段之间的表面暴露部分桥接；或组装元器件与第二元件，利用熔点低于300℃的导电结合材料，使导电垫与第二元器件的导电垫接合，导电结合材料与至少两个相邻段之间的介电区域的表面暴露部分桥接。
根据此第四方面的某些实施例，芯模可包括金属片，步骤（c）可包括，蚀刻金属片，以暴露第一元器件的垫。步骤（b）可包括，使第一元器件的导电垫嵌入至少部分固化的包括介电材料的介电区域内。步骤（b）可包括，沉积与第一元器件的导电垫的至少一部分接触的介电材料。步骤（d）可包括，在导电垫上施加导电结合材料，导电结合材料与至少两个相邻段之间的表面暴露部分桥接。步骤（d）可包括，组装元器件与第二元器件，利用导电结合材料使导电垫与第二元器件的导电垫接合，导电结合材料与至少两个相邻段之间的介电区域的表面暴露部分桥接。
本发明的第五方面为形成元器件组件的方法，该方法包括：（a）提供具有导电垫的引线框架，导电垫由导电元件限定，导电元件沿表面延伸且具有在曲线路径内沿表面延伸的至少一部分；（b）使引线框架至少部分地嵌入介电材料内，其中导电垫可在介电材料的表面暴露，用于允许元器件与第二元器件电互连，导电垫的导电元件具有在振荡路径或螺旋路径中至少一种路径内沿介电区域表面延伸的至少一部分，使得理论直线与路径的至少三段相交，导电元件具有被介电区域表面的一部分隔开的至少两个相邻段，介电区域表面的至少一部分在至少两个相邻段之间暴露，导电元件具有沿介电区域表面可为高度至少十倍的长度；及（c）进行以下之一：在导电垫上施加熔点低于300℃的导电结合材料，导电结合材料与至少两个相邻段之间的表面暴露部分桥接；或组装元器件与第二元器件，利用熔点低于300℃的导电结合材料使导电垫与第二元器件的导电垫接合，导电结合材料与介电区域的表面在至少两个相邻段之间的暴露部分桥接。
根据此第五方面的某些实施例，步骤（c）可包括，在导电垫上施加导电结合材料，导电结合材料与至少两个相邻段之间的表面暴露部分桥接。步骤（c）可包括，组装元器件与第二元器件，利用导电结合材料使导电垫与第二元器件的导电垫接合，导电结合材料与至少两个相邻段之间的介电区域的表面暴露部分桥接。
附图说明
图1是根据本发明具有凹槽的基板的俯视图。
图2是图1中基板沿线A-A剖切的侧剖视图。
图3是具有垫的图1中基板的俯视图。
图4是图3中基板沿线B-B剖切的侧剖视图。
图5至图7是图3中基板与垫的变例的侧剖视图。
图8是具有结合材料的图3中基板与垫的俯视图。
图9是图8中基板与结合材料沿线C-C剖切的侧剖视图。
图10是附接至第二元器件的图8中基板、垫及结合材料的侧剖视图。
图11是具有垫的基板变例的俯视图。
图12是设置在边界内的图3中垫的俯视图。
图13和图14是根据本发明具有垫的基板变例的俯视图。
图15是根据本发明具有与芯片电连接的垫的基板的俯视立体图。
图16是图15中基板沿线E-E剖切的侧剖视图。
图17是图15中基板与垫变例的侧剖视图。
图18是具有结合材料的图17中基板与垫的侧剖视图。
图19是根据本发明具有形成于其上的垫的芯模的顶面立体图。
图20是图15中芯模与垫沿线F-F剖切的侧剖视图。
图21和图22是示出嵌入介电区域内的图19中垫的侧剖视图。
图23是根据本发明一个实施例系统的示意图。
具体实施方式
如在本文应用的，声明导电元件“暴露在”介电元件的表面，指的是导电元件可与一理论点接触，该理论点以垂直于该介电元件表面的方向从介电元件外部向该介电元件表面移动。因此，暴露在介电元件表面上的端子或其他导电元件可从该表面突出；可与该表面平齐；或可相对该表面凹陷，并通过介电元件上的孔或凹坑暴露。
如图8和图9所示，组件100的第一实施例，将根据其构造方法进行描述。组件100包括，例如图1和图2所示的第一元器件105。元器件包括至少一介电区域120，且还可包括如基板等的支撑元件，置于介电区域120下方。例如，第一元器件可为，制备成芯片载体、封装的其他元器件或电路板的介电元件。基板110可为元器件105的附加介电层、或可为如将在下文进一步描述的其他结构。从图1至图2可以看出，具有底部126的连续凹槽124形成为，沿介电区域的表面122延伸。底部126定义为凹槽124的最低部分。凹槽124的至少一部分对于表面122沿曲线路径延伸。
凹槽124可通过除去介电区域120的一部分而形成，在一个示例中，可通过在表面122上引入激光进行激光烧蚀而制成。例如，如计算机等的系统，可用于把激光产生的光照点移动至表面122上的不同位置。激光烧蚀或其他方式除去牺牲层（如果存在）的一部分及介电区域120的一部分。所画出的凹槽124具有弯曲或圆形的底部126，但是，或者有意地、或者为采用激光约束的结果，也可形成如长方形等的其他横截面。
在激光烧蚀步骤之前，尽管并没有画出，可设置覆盖介电区域120的表面122的牺牲层。典型地，牺牲层可为聚合物材料，且具有与表面122轮廓一致的暴露表面。牺牲层可通过喷涂、旋涂、浸渍或其他方法而涂敷。在特定实施例中，牺牲层可通过化学方法去除，如采用蚀刻剂。在一个实施例中，牺牲层可通过剥离而去除。尽管可采用牺牲层，凹槽124的形成并不要求使用牺牲层。
在凹槽形成后，形成沿表面122以凹槽方向延伸的导电元件。在一个实施例中，可形成覆盖介电区域120和/或牺牲层（如果存在的话）暴露部分的催化剂层。催化剂层至少覆盖凹槽124的底部126，且通常由金属颗粒薄层组成，可催化随后的金属沉积过程，例如，随后在其上电镀金属层时采用的水溶液沉积过程。在一个示例中，催化剂层可包括铂颗粒。在一个示例中，催化剂层可通过在牺牲层的暴露表面提供含有催化剂颗粒的液体而形成，例如，通过把基板浸入包含催化剂颗粒的浴槽中。典型地，催化剂层均匀地涂敷在第一元器件105上。如果存在牺牲层，把其从第一元器件105上去除，从而也除去了位于牺牲层上的催化剂层。以这种方式，在牺牲层除去后，催化剂层只设置在凹槽124内。如果没有牺牲层，催化剂可只在第一元器件105的将电镀形成导电元件的区域内或沿该区域沉积，例如，可只在凹槽124内的区域沉积。
然后可在催化剂层上选择性地沉积籽晶层，且过程可继续，以沉积一层或多层的金属层，其可包括粘接层、金属隔离层与原生金属层中任意层或所有层。典型地，这种籽晶层、粘接层、金属隔离层或原生金属层通过电镀而沉积。从图3和图4中可以看出，这种选择性地在具有催化剂层的区域上沉积金属的过程，结果在凹槽124内形成了导电元件132。图4中更清楚地示出，导电元件134的横截面尺寸，即导电元件132的宽度及在凹槽124底部126上方的高度或厚度，是至少部分地由凹槽124限定的。所画出的导电元件132具有平坦的顶面135，但在实际上，可能产生一定程度 “U”型的表面。因此，导电元件132的高度可定义为，从其最低点（即凹槽124的最低点）延伸至其最高点。如图2所示，凹槽124的深度128和宽度130的相应横截面尺寸，辅助限定导电元件132。深度128是在底部126与介电区域120的表面122之间测量的。当凹槽的宽度130以沿着表面130的垂直方向测量，且该方向与深度128及凹槽124的纵向125都垂直时，深度可比凹槽的宽度130大。进一步地，深度128可大于与宽度130对应的导电元件132的宽度。以这种方式，导电元件132可具有与凹槽124内表面一致的轮廓，且至少部分地嵌入介电区域120的凹槽124内。在一个实施例中，沿导电元件各段的整个路径，导电元件132的高度可至少基本相同。
在上述实施例的变例中，可在构成导电元件132的一层或多层金属层沉积后，再去除牺牲层。例如，在一个实施例中，可在籽晶层、粘接层、金属隔离层、或原生金属层沉积前所设置的其他金属层中任意层或所有层都沉积后，再去除牺牲层。在这种情况下，牺牲层可在从介电区域“剥离(lift-off)”的过程中除去，如通过蚀刻、剥离或其他方法。然后，在牺牲层除去后，可继续金属沉积过程，以沉积随后的包括原生金属层在内的一层或多层金属层，用于形成导电元件132。
从图3至图4可以看出，导电元件132形成了在介电区域120的表面122暴露的垫134。垫134可与一个或多个其他导电元件（未示出），如导电迹线、其他导电垫、或其他电路元器件等，连接或一体形成。在导电元件134的一个或多个位置处，如导电元件的端部139或路径中位置141，这种其他导电元件可从导电元件延伸或与其连接。
如图10所示，垫134允许第一元器件105与第二元器件107电互连。导电元件132所限定的垫134，具有横截面尺寸、及至少部分地由凹槽124路径所限定的路径。导电元件132从凹槽124的底部126延伸至底部126上方的高度。如图4所示，导电元件132的高度大于底部126与表面122之间的距离。但是，在图5和图6所示的本发明的变例中，导电元件在底部上方的高度可分别与该距离相等或小于该距离。在图5中，导电元件232延伸至底部226上方的高度等于底部226与介电区域220的表面222之间的距离。在这种情况下，导电元件232的顶面244可与介电区域的表面222共面。图6示出的导电元件332延伸至底部326上方的高度小于底部326与介电区域320的表面322之间的距离。从而导电元件的顶面344位于介电区域的表面322下方。
如图3所示，导电元件132包括至少两个被介电区域120的一部分137隔开的相邻段136、138。相应地，可以说理论直线199与导电元件132的至少三个段136、138和150相交。导电元件132具有沿表面122的总体长度，至少为其高度133的十倍，如高度从底部126至顶面135而测量。垫134可构造为，使得导电元件132占据的面积小于位于基本为圆形的边界146内的介电元件120的表面面积的百分之七十五，如图12所示，边界146大致由垫134的最远边缘限定。在优选实施例中，根据本发明的导电元件占据该边界内面积的百分之十至百分之七十五，在某些实施例中，导电元件可约占据此边界内面积的百分之二十五。
在一个结构中示出并描述了第一元器件105，但组件100及第一元器件105的其他结构也可通过本发明实现，并将在下文更充分地描述。例如，第一元器件105包括具有螺旋路径的导电元件132（如图1和图3所示）。在其他示例中，第一元器件505可包括在表面522上具有正弦曲线路径的导电元件532（如图13所示），或第一元器件605可包括在表面622上具有振荡路径的导电元件632（如图14所示）。正弦曲线的路径通常是波状的，而振荡路径是大致以交替地从一边到另一边的方式、沿从导电元件的始端至末端的方向延伸。“振荡路径”广义地描述导电元件各构造元素的排列，包括正弦曲线路径。另外，振荡路径无需是如图14所示的均匀路径。导电元件632可形成为振荡路径，该振荡路径形成垫的一部分，而另外的一个或多个部分以其他方式设置。例如，垫可包括形成振荡路径的一部分、及横穿振荡路径但无法描述成任何特定类型形状的另一部分。例如，振荡路径可为三角波状、锯齿状（zig-zag）图形或任意其他类似图形。振荡路径无需具有均一长度的段636，或路径在各段之间也无需以相同角度634反向。路径的至少一些相邻段可以不是两端都接合在一起。而是，在一些情况下，导电元件可具有在为导电垫设定的限定区域内“蜿蜒”的振荡路径，其中路径的各段可具有不同长度，且在各段之间可具有不同角度。对于导电元件532和632来说，每个所占据的面积，可都分别小于位于各导电元件532及632的最外边缘所大致限定的、基本为方形的边界内的各表面522、622的面积的百分之七十五。根据本发明，可实现任意其他适当形状或结构的导电元件，以形成垫。本发明的一个优点是能够限定垫的大致外边界，位于所述边界内的导电元件可为任意图案。因此，导电元件无需精确图案，由于总体结构为垫，因而是有效的。如图3所示，导电元件132，沿其路径没有自身重叠或横穿。在替代实施例中，如图11中所画出的，第一元器件405的导电元件432可在表面422的一个或多个区域内自身重叠或横穿。
在形成垫134的另一方法中，可沉积覆盖介电区域120的表面122及凹槽124的至少一部分的导电材料。然后，可去除至少覆盖表面122的一部分的一些导电材料，以暴露介电区域120的表面122。
在形成垫134后，可设置至少部分地覆盖垫134的导电结合材料140，如图8和图9所示。导电结合材料140，优选地具有低于300℃的熔点，可为焊接材料，且可至少在垫134的最外边缘之间延伸，从而当从垂直于表面122的方向来看时，导电结合材料完全覆盖垫134，如图8所示。导电结合材料140可与导电垫134接合，以与介电区域120的位于导电元件132的段136、138之间的部分137桥接，图3中更清楚地示出。如图10所示，第二元器件107包括通过结合材料140而与垫134接合的端子108。虽然在第一元器件105与第二元器件107组装前，结合材料140可直接施加在垫132上，但在将上述元器件组装在一起前，结合材料也可替代地只施加在第二元器件107的端子108上，或可分别施加每个垫132及端子108上。
如图9所示，导电元件132延伸至表面122上方的高度，导电元件132包括暴露在介电区域120的表面122上方的暴露顶面144、及在顶面144与表面122之间延伸的暴露“竖直表面”142。“竖直表面”142为远离顶面144延伸的边缘表面，但其相对顶面144及介电区域表面122可为沿竖直或垂直方向，或可为不沿该方向。结合材料140与顶面144及竖直表面142都接触。在变例中，如图5和图6中所画出的，结合材料与导电元件及表面以不同的方式接触。在图5中，顶面244基本与介电区域220的表面222平齐。因此，结合材料将具有与导电元件232的顶面244及表面222接触的基本平坦的接触表面。在图6中，导电元件332的顶面344位于表面322下方，结合材料还与凹槽324的在导电元件332的顶面344与介电区域320的表面322之间暴露的竖直表面348接触。可以理解的是，能与结合材料接触的表面积越大，结合材料与第一元器件之间的粘附力越大。此外，可用电镀或其他方法形成含有镍、金或其他金属的表面层，在垫134的一个或多个表面、例如顶面142和边缘表面144暴露。
根据本发明，第一元器件的实施例可由单个介电区域组成、可包括置于介电区域下方的基板、或可包括以堆叠形式的超过一个的介电区域或层。介电区域可包括两层或更多层的介电材料堆叠层，至少两个相邻层包括不同的材料。介电区域典型地包括一种或多种介电材料，如任意形式的二氧化硅、硅的其他介电化合物、聚合物材料、或如陶瓷材料等的其他无机介电材料、及其他。根据本发明的基板典型地主要由单晶半导体材料组成，如硅、硅与其他材料的合金、如砷化镓及其他的一种或多种Ⅲ-Ⅴ族半导体化合物、或一种或多种Ⅱ-VI族半导体化合物。在特定实施例中，基板可为绝缘体上硅的基板，包括使正面的有源半导体器件层与背面大块的半导体区域隔开的埋层氧化物（“BOX”）层。
在图7所示的实施例中，基板110包括在背面112与正面114之间延伸的开口116、及设置在正面114上的复数个导电元件118。通过贯穿基板110内的开口116及介电元件120内的邻接开口延伸，导电元件132使垫134与至少一个导电元件118电连接。凹槽124的至少一部分可沿开口116的内表面延伸，且导电元件132可在凹槽124的该部分内延伸。
另一实施例的第一元器件705如图15至图18所示，包括芯片710和覆盖芯片710上表面的钝化层703。结合垫750设置在钝化层703的暴露表面704上，该钝化层为具有暴露表面的介电区域。导电垫734也以上述的方式形成在表面704上。迹线752与芯片750电连接，并沿表面704延伸，以与垫734的一部分电连接。迹线752可在上文概述的过程中与垫734一同形成，或可在形成垫734后再形成迹线752，以使芯片750与垫734电连接。在迹线752所设置的位置，如图15所示，可还设置复数条迹线或可设置替代迹线752的复数条迹线。
垫734允许芯片750与外部元器件电连接，外部元器件可如参照图10在上文所述的方式与芯片接合。在此时，如图17所示，可沉积覆盖钝化层703和迹线752的焊料掩模756，例如采用光刻(photolithographic)法。正是如此，仍暴露的垫132可被导电结合材料740覆盖（图18）。然后，利用与图10所画出的类似方式的结合材料740，另一元器件可与芯片750电连接。替代地，具有端子的第二元器件可与垫734接合，以形成电连接，而端子上设有结合材料。
图19至图22描述了另一实施例，示出根据本发明形成第一元器件805的另一方法。在芯模860或其他类型的引线框架的平坦表面862上，形成导电垫834（图19至图20）。以与上文所述类似的布置，垫834作为电镀导电元件而形成。然后芯模860放置在介电区域820邻近，使得垫834与介电区域820的表面822邻接（图21）。向芯模860施加压力，使垫834嵌入可至少部分地固化的介电区域820内。然后去除芯模860，所生成的第一元器件805（图22）与上述实施例的第一元器件类似。
在某些实施例中，芯模860可由一个或多个金属片组成，通过蚀刻掉每个金属片而进行除去芯模的步骤，以使垫834暴露。在其他实施例中，介电区域820可不是预成型的，而是可在芯模860的表面862上沉积介电材料，然后去除芯模860，以形成第一元器件805。
在本文所描述的任意实施例或所有实施例中，具有如上文所述螺旋或振荡路径的导电垫的、或根据上文所述技术而形成的第一元器件，可与第二元器件接合或电连接，利用导电结合材料与导电垫的表面以上文所述的方式接触，并与第二元器件的端子接触。结合材料与介电区域的表面的、位于导电垫的至少两相邻段之间的部分桥接。在第一元器件与第二元器件组装之前，可在该导电垫上施加结合材料，在这种情况下，导电垫上的结合材料将成为第一元器件与第二元器件之间的接合点或导电连接的一部分。替代地，在第一元器件与第二元器件组装前，结合材料可施加在第二元器件的端子上而没有施加在该导电垫上。在组装步骤中，第二元器件端子上的结合材料将流至导电垫的表面，然后将与介电区域的表面的位于至少两相邻段之间的部分桥接。在一个示例中，可通过加热如焊料等的结合金属至足以使结合金属流动的温度、然后结合金属与该垫的表面及第二元件上的与垫并置的端子都接触。然后结合金属再次凝固以形成导电接合点。在另一示例中，结合材料可分别施加至该导电垫及第二元器件的端子上，之后第一元器件与第二元器件可放在一起并如上文所述接合。
根据本发明的第一元器件，可为具有邻近介电区域表面的复数个有源半导体器件的微电子元件。在变例中，第一元器件可为在其表面上具有复数个触点的微电子元件，且可进一步包括使导电垫与复数个触点中至少一个电连接的迹线。在又一实施例中，第一元器件可为在表面上具有复数个触点的微电子元件，导电垫可与复数个触点中的至少一个电连接。
在本发明的某些实施例中，基板实质上由单晶半导体材料组成，覆盖基板的介电区域包括与基板的倾斜表面的轮廓一致的介电材料层。在变例中，基板可实质上由介电材料组成，或可包括实质上由导电材料组成的区域，其中介电区域覆盖该导电材料区域。
作为光刻法的替代，利用激光形成导电元件，可允许元件的布局更容易改变。在本方法中，改变布局可只需改变控制激光移动的计算机程序，因为激光的移动决定了导电元件的外形和尺寸。这与通过光刻法形成迹线所用的光掩模的制造与检验所需的时间与费用形成对比。
上述实施例可包括通过如直接记录法而形成的凹槽和孔隙，如采用激光限定路径。但是，可采用其他方法形成根据本发明的这些特征。可利用机械球磨，其中可称为锤的小直径元件，反复敲击牺牲层，如果存在的话，及介电区域，以松动及去除这些材料以形成凹槽或孔隙。另一可利用的方法是与金属模板一起应用的喷砂技术，金属模板放置在牺牲层和/或介电区域上，且包括形状根据导电元件的所需最终图案而定的开口。喷砂技术通过沿一方向向介电区域引入砂基材料而进行，使砂基材料敲击牺牲层和/或介电区域的在开口内暴露的区域。从而在介电区域内形成一个或多个凹槽。机械球磨和喷砂等这些特定技术可称为“非光刻技术”，因为其不是主要依靠通过光掩模暴露光致抗蚀剂而图案化。这些图案化技术及可用其形成的其他结构的描述，出现在共同拥有的申请号为12/842669、申请日为2010年7月23日的美国专利申请中，其公开的内容以引用的方式并入本文。根据本发明构造结构的方法的剩余步骤如上文所记载。
在一个实施例中，与现有方法、如光栅法相比，本文公开的方法可获得具有更大平面度的垫顶面。因为根据本发明的垫典型地包括由间隙隔开的段，通过相邻段的顶面为共面的或基本限定单个平面，可获得顶面的平面度。
需指出的是，除去牺牲层的某些方法，需要牺牲层性质上更脆。例如，上述的喷砂技术除去较脆的牺牲层更有效，从而砂基材料不是嵌入牺牲层内而是击碎及去除牺牲层。
在上述的特定实施例中，生成的组件可为或包括具有有源电路元件的微电子单元，如晶体管、二极管或其他微电子或微机电器件、及其他，且可具有通过上述的一种或多种技术、甚至如非光刻技术而形成的迹线。同样在上述的某些实施例中，生成的组件可为或包括插板结构，插板结构具有半导体或介电材料中的至少一种的基板，且基板具有如上述方法形成的迹线，但没有有源电路元件。根据这些实施例的插板结构或元器件，可具有暴露在正面与背面中一个或多个上的导电元件，用于与一个或多个外部元器件互连，例如，微电子元件、基板或电路板。
在上述的特定实施例中，生成的组件可为或包括具有有源电路元件的微电子单元，如晶体管、二极管或其他微电子或微机电器件、及其他，且可具有通过上述的一种或多种技术而形成的迹线。同样在上述的某些实施例中，生成的组件可为或包括插板结构，插板结构具有半导体或介电材料中的至少一种的基板，且基板具有如上述方法形成的迹线，但没有有源电路元件。根据这些实施例的插板结构或元器件，可具有暴露在正面与背面中一个或多个上的导电元件，用于与一个或多个外部元器件互连，例如，微电子元件、基板或电路板。
上述的结构提供了超常的三维互连能力。这些能力可用于任意类型的芯片。仅以示例的方式说明，芯片的下面的组合可在如上文所述的结构中包括：（i）处理器及与该处理器一起使用的存储器；（ii）相同类型的复数个存储器芯片；（iii）不同类型的复数个存储器芯片，如DRAM（动态随机存储器）和SRAM（静态存储器）；（iv）图像传感器和用于处理来自传感器的图像的图像处理器；（v）专用集成电路（“ASIC”）和存储器。上述的结构可在不同的电子系统的构造中利用。例如，根据本发明进一步实施例的系统900包括如上文所述的结构906与其他电子元器件908和910配合使用。在描述的示例中，元器件908为半导体芯片，而元器件910为显示屏，但任意其他元器件都可应用。当然，尽管为清楚图示起见，在图23中只描述了两个附加元器件，系统可包括任意数量的这种元器件。如上文所述的结构906可为，例如，复合芯片或包含复数个芯片的结构。在另一变例中，二者都可提供，且任意数量的这种结构都可应用。结构906和元器件908、910都安装至以虚线示意性地描绘的共同外壳901内，且彼此电互连以形成所需的电路。在所示的示例性系统中，系统包括如柔性印刷电路板等的电路板902，且电路板包括使元器件之间彼此互连的大量导电体904，其中在图23中只示出了一个。但是，这只是示例，任意适当的用于形成电连接的结构都可应用。外壳901作为便携式外壳而描述，具有用于如移动电话或个人数字助理等的类型，显示屏910暴露在外壳的表面。其中结构906包括如成像芯片等的光敏元件，还可配置镜头911或其他光学器件，以提供光至结构的路线。同样，图23内所示的简化系统只是示例，其他系统，包括一般视为固定结构的系统，如台式计算机、路由器及类似的结构，都可应用上述的结构而制成。
尽管本发明参照特定实施例进行描述，可以理解的是，这些实施例只是说明本发明的原理和应用。因此，应理解为，在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下，说明的实施例可做出许多修改及可设计出其他布置。
工业实用性
本发明享有广泛的工业实用性，包括但不限于组件及在基板上设置导电元件的方法。

Claims (68)

1. 组件，包括：
第一元器件，包括具有暴露表面的介电区域；
导电垫，在所述表面上，允许所述第一元器件与第二元器件电互连，所述导电垫由导电元件限定，所述导电元件的至少一部分在振荡路径或螺旋路径中的至少一条路径内沿所述表面延伸，使得理论直线与所述路径的至少三段相交，且所述导电元件的至少两个相邻段被所述表面的没有被所述导电元件覆盖的一部分隔开，所述导电元件从所述表面延伸至所述表面上方一高度的顶面，且具有沿所述表面至少为所述高度十倍的长度；
导电结合材料，具有低于300℃的熔点，与所述导电垫接合，且与所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接，
其中所述导电元件具有远离所述顶面延伸的边缘表面，且所述导电结合材料与所述导电元件的所述顶面及所述边缘表面都接触。
2. 根据权利要求1所述的组件，进一步包括具有端子的第二元器件，所述端子与所述导电垫通过所述结合材料而接合。
3.根据权利要求1所述的组件，其中所述导电元件的所述路径不自身重叠或横穿。
4.根据权利要求1所述的组件，其中所述导电元件的所述路径至少为以下之一：自身重叠或横穿。
5.根据权利要求1所述的组件，其中所述导电元件所占据的面积，小于所述介电区域位于所述垫的最外边缘所限定的圆形边界内的表面积的百分之七十五。
6.根据权利要求1所述的组件，其中所述第一元器件进一步包括具有基板表面的基板，所述介电区域至少部分地覆盖所述基板表面。
7.根据权利要求6所述的组件，其中所述基板表面为所述基板的顶面，所述基板进一步具有远离所述顶面的底面、在所述顶面与所述底面之间延伸的开口、及设置在所述底面上的第二导电元件，所述垫与所述第二导电元件通过所述基板内的所述开口及所述介电区域内的开口而电连接。
8.根据权利要求1所述的组件，其中所述介电区域的所述表面暴露在所述第一元器件的所述暴露表面上，所述第一元器件进一步具有远离所述暴露表面的底面、在所述顶面与所述底面之间延伸的开口、及设置在所述底面上的第二导电元件，所述垫与所述第二导电元件穿过所述第一元器件内的所述开口及所述介电区域内的开口而电连接。
9.根据权利要求1所述的组件，其中所述暴露表面为背面，所述第一元器件具有远离所述背面的正面、及在正面与背面之间延伸的开口，其中所述导电元件在所述背面暴露，且所述导电元件的至少一部分沿所述开口的内表面延伸。
10.根据权利要求9所述的组件，其中所述第一元器件具有在所述正面上的至少一个触点，其中所述至少一个触点与所述导电元件之间的电连接通过所述开口而实现。
11.根据权利要求10所述的组件，其中所述第一元器件为微电子元件，其具有邻近所述正面的复数个有源半导体器件。
12.根据权利要求1所述的组件，其中所述第一元器件为在所述表面上具有复数个触点的微电子元件，进一步包括使所述导电垫与所述复数个触点中至少一个电连接的迹线。
13.根据权利要求1所述的组件，其中所述第一元器件为其上具有复数条迹线的介电元件，其中所述导电垫与至少一条迹线电连接。
14.根据权利要求1所述的组件，其中所述表面为第一表面，所述第一元器件为具有在远离所述第一表面的第二表面上的复数个触点的微电子元件，所述导电垫与所述复数个触点中至少一个电连接。
15.根据权利要求1所述的组件，其中所述结合材料为焊料。
16.根据权利要求1所述的组件，其中所述垫包括含有镍或金中至少一种的表面层，且所述结合材料与所述表面层接触。
17.系统，包括：根据权利要求1所述的组件及一个或多个与所述组件电连接的其他电子元器件。
18.根据权利要求17所述的系统，进一步包括外壳，所述组件及所述其他电子元器件安装至所述外壳。
19.组件，包括：
第一元器件，包括具有暴露表面的介电区域；
连续凹槽，沿所述表面延伸，且具有至少一部分沿所述表面在曲线路径内延伸，所述凹槽具有设置在所述表面下方的底部；
导电垫，在所述表面上暴露，允许所述第一元器件与第二元器件电互连，所述导电垫由导电元件限定，所述导电元件具有至少部分地由所述凹槽限定的横截面尺寸，并从所述凹槽的所述底部延伸至所述底部上方的高度，且具有在振荡路径或螺旋路径中的至少一条路径内沿所述表面延伸的至少一部分，使得理论直线与所述路径的至少三段相交，所述导电元件具有被所述介电区域的所述表面的暴露部分隔开的至少两个相邻段，且所述导电元件具有沿所述表面的至少为所述高度十倍的长度；及
导电结合材料，熔点低于300℃，与所述导电垫接合，并与所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接。
20. 根据权利要求19所述的组件，其中所述第一元器件为微电子元件，其具有在其所述表面上的复数个触点及邻近所述表面的复数个有源半导体器件，进一步包括使所述导电垫与所述复数个触点中至少一个电连接的迹线。
21.根据权利要求19所述的组件，其中所述第一元器件为其上具有复数条迹线的介电元件，其中所述导电垫与至少一条迹线电连接。
22.根据权利要求19所述的组件，其中所述表面为第一表面，所述第一元器件为微电子元件，其具有在远离所述第一表面的第二表面上的复数个触点、及邻近所述第二表面的复数个有源半导体器件，且所述导电垫与所述复数个触点中至少一个电连接。
23.根据权利要求19、20、21或22所述的组件，进一步包括第二元器件，所述结合材料使所述导电垫与所述第二元器件的端子接合。
24.根据权利要求19所述的组件，其中所述结合材料为焊料。
25.根据权利要求19所述的组件，其中所述第一元器件包括在所述正面与所述背面之间延伸的开口，所述导电元件的至少一部分沿所述开口的内表面延伸，所述凹槽的至少一部分沿所述内表面延伸，所述导电元件在所述凹槽的该部分内延伸。
26.根据权利要求25所述的组件，其中所述至少一个触点与所述导电元件之间的电连接通过所述开口而实现。
27.根据权利要求19所述的组件，其中所述导电元件的所述高度大于所述底部与所述介电区域的所述表面之间的距离。
28.根据权利要求19所述的组件，其中所述导电元件的所述高度等于或小于所述底部与所述介电区域的所述表面之间的距离。
29.根据权利要求19所述的组件，其中所述垫的最外边缘对于所述表面限定圆形或方形的边界。
30.根据权利要求29所述的组件，其中所述导电元件的所述路径不自身重叠或横穿。
31.根据权利要求29所述的组件，其中所述导电元件的所述路径至少为自身重叠或横穿中的一种。
32.根据权利要求29所述的组件，其中所述导电元件所占据的面积小于位于所述边界内的所述表面的表面积的百分之七十五。
33.根据权利要求19所述的组件，其中所述导电元件的所述高度大于所述底部与所述表面之间的距离，使得所述导电元件具有暴露在所述介电区域的所述表面的顶面、及远离所述顶面而延伸的边缘表面，所述结合材料与所述导电元件的所述顶面及所述边缘表面都接触。
34.根据权利要求19所述的组件，其中所述垫包括含有镍或金中至少一种的表面层。
35.根据权利要求19所述的组件，其中所述介电区域的所述表面暴露在所述第一元器件的所述暴露表面，所述第一元器件进一步包括与所述暴露表面相对的底面、在所述暴露表面与所述底面之间延伸的开口、及覆盖所述底面的第二导电元件，所述垫与所述第二导电元件通过所述第一元器件内的所述开口及所述介电区域内的开口而电连接。
36.根据权利要求19所述的组件，其中所述介电区域包括焊料掩模。
37.根据权利要求19所述的组件，其中所述介电区域为聚合物材料。
38.根据权利要求19所述的组件，其中所述介电区域为无机材料。
39.根据权利要求19所述的组件，其中所述介电区域包括两层或更多层的介电材料堆叠层，其中至少两个相邻的层包括不同材料。
40.系统，包括，根据权利要求19所述的组件及一个或多个与所述组件电连接的其他电子元器件。
41.根据权利要求40所述的系统，进一步包括外壳，所述组件及所述其他电子元器件安装至所述外壳。
42.在第一元器件上形成导电结构的方法，包括：
（a）通过除去介电区域的一部分而形成沿第一元器件的介电区域的暴露表面延伸的连续凹槽，所述凹槽的至少一部分在曲线路径内延伸，所述凹槽具有位于所述表面下方的底部；
（b）形成在所述表面暴露的导电垫，以允许所述第一元器件与第二元器件电互连，所述导电垫由导电元件限定，所述导电元件具有横截面尺寸、及至少部分地由所述凹槽的路径所限定的路径，并从所述凹槽的所述底部延伸至所述底部上方的高度，所述导电元件的至少一部分在振荡路径或螺旋路径中至少一种路径内沿所述表面延伸，使得理论直线与所述路径的至少三段相交，所述导电元件具有被所述表面的一部分隔开至少两个相邻段，所述导电元件具有沿所述表面的至少为所述高度十倍的长度，所述导电元件至少部分地嵌入所述凹槽内；及
（c）进行以下之一：
在所述导电垫上施加熔点低于300℃的导电结合材料，所述导电结合材料与所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接；或
利用熔点低于300℃的导电结合材料，组装所述元器件与所述第二元器件，使所述导电垫与所述第二元器件的导电垫接合，所述导电结合材料与所述介电区域的所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接。
43.根据权利要求42所述的方法，其中所述导电元件的所述高度大于所述底部与所述表面之间的距离。
44.根据权利要求43所述的方法，其中所述导电元件包括与所述介电区域的所述表面平行的暴露顶面、及在其顶面与所述介电区域的所述表面之间延伸的暴露竖直表面，所述结合材料与所述导电元件的所述顶面及所述竖直表面都接触。
45.根据权利要求42所述的方法，其中所述导电元件的所述高度等于或小于所述底部与所述表面之间的距离。
46.根据权利要求42所述的方法，其中所述底部与所述表面之间的距离大于所述导电元件的宽度。
47.根据权利要求42所述的方法，其中步骤（b）包括，形成所述导电元件，使得其不自身重叠或横穿。
48.根据权利要求42所述的方法，其中步骤（b）包括，形成所述导电元件，使得其为自身重叠或横穿中至少一种。
49.根据权利要求42所述的方法，其中步骤（c）包括，形成至少覆盖所述凹槽的所述底部的催化剂层，然后在存在所述催化剂层的区域选择性地沉积金属，以形成所述导电元件。
50.根据权利要求42所述的方法，其中所述结合材料至少在所述第一元器件的所述垫的最远边缘之间延伸。
51.根据权利要求42所述的方法，其中步骤（b）包括，电镀含有镍或金中至少一种的表面层，所述表面层在所述第一元器件的所述垫的表面暴露。
52.根据权利要求42所述的方法，其中所述第一元器件包括第二区域，当进行步骤（a）和步骤（b）时，所述介电区域覆盖所述第二区域。
53.根据权利要求52所述的方法，其中所述基板具有与所述顶面相对的底面、在所述顶面与所述底面之间延伸的开口、及覆盖所述底面的所述导电元件，所述第一元器件的所述垫与所述导电元件通过所述基板内的所述开口与所述介电元件内的邻接开口而电连接。
54.根据权利要求42所述的方法，其中步骤（a）通过包括以下至少一种的过程而进行：至少朝所述表面引入激光以烧蚀所述介电区域的一部分、机械球磨、或喷砂。
55.根据权利要求42所述的方法，其中步骤（b）包括，放置金属模板以覆盖所述介电区域，所述金属模板具有至少一个开口，并通过喷砂除去所述介电区域通过所述至少一个开口暴露的部分。
56.根据权利要求42所述的方法，其中步骤（b）包括，通过机械球磨除去所述介电区域的一部分。
57.根据权利要求42所述的方法，其中步骤（b）包括，沉积覆盖所述介电区域的所述表面及所述凹槽的至少一部分的导电材料，并除去覆盖至少一部分所述表面的所述导电材料，以暴露所述介电区域的所述表面。
58.根据权利要求42所述的方法，其中步骤（c）包括，在所述导电垫上施加所述结合材料，所述结合材料与所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接。
59.根据权利要求42所述的方法，其中步骤（c）包括，组装所述元器件与所述第二元器件，利用所述结合材料使所述导电垫与所述第二元器件的导电垫接合，所述结合材料与所述介电区域的所述表面的位于所述至少两相邻段之间的所述暴露部分桥接。
60.形成第一元器件组件的方法，所述方法包括：
（a）在芯模的平坦表面上电镀导电垫，所述导电垫由沿所述表面延伸的导电元件限定，且具有在曲线路径内沿所述表面延伸的至少一部分；
（b）使所述导电垫至少部分地嵌入介电材料内；
（c）除去所述芯模以形成具有介电区域及所述导电垫的所述第一元器件，所述导电垫暴露在所述介电区域的表面，用于允许所述元器件与第二元器件电互连，所述导电垫的所述导电元件具有在振荡路径或螺旋路径中至少一种路径内沿所述介电区域的所述表面延伸的至少一部分，使得理论直线与所述路径的至少三段相交，所述导电元件具有被所述介电区域的所述表面的一部分隔开的至少两个相邻段，所述介电区域的所述表面的至少一部分在所述至少两个相邻段之间暴露，所述导电元件具有沿所述介电区域的所述表面至少为所述高度十倍的长度；及
（d）进行以下一种：
在所述导电垫上施加熔点低于300℃的导电结合材料，所述导电结合材料与所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接；或
组装所述元器件与所述第二元器件，利用熔点低于300℃的导电结合材料使所述导电垫与所述第二元器件的导电垫接合，所述导电结合材料与所述介电区域的所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接。
61.根据权利要求60所述的方法，其中所述芯模包括金属片，步骤（c）包括，蚀刻所述金属片，以暴露所述第一元器件的所述垫。
62.根据权利要求60所述的方法，其中步骤（b）包括，使所述第一元器件的所述导电垫嵌入包括所述介电材料的至少部分固化的介电区域内。
63.根据权利要求60所述的方法，其中步骤（b）包括，沉积与所述第一元器件的所述导电垫的至少一部分接触的介电材料。
64.根据权利要求60所述的方法，其中步骤（d）包括，在所述导电垫上施加所述结合材料，所述结合材料与所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接。
65.根据权利要求60所述的方法，其中步骤（d）包括，组装所述元器件与所述第二元器件，利用所述结合材料使所述导电垫与所述第二元器件的导电垫接合，所述结合材料与所述介电区域的所述表面的位于所述至少两外相邻段之间的所述暴露部分桥接。
66.形成元器件组件的方法，所述方法包括：
（a）提供具有导电垫的引线框架，所述导电垫由导电元件限定，所述导电元件沿所述表面延伸且具有在曲线路径内沿所述表面延伸的至少一部分；
（b）使所述引线框架至少部分地嵌入介电材料内，
其中所述导电垫在所述介电材料的表面暴露，用于允许所述元器件与第二元器件电互连，所述导电垫的所述导电元件具有在振荡路径或螺旋路径中至少一种路径内沿所述介电区域的所述表面延伸的至少一部分，使得理论直线与所述路径的至少三段相交，所述导电元件具有被所述介电区域的所述表面的一部分隔开的至少两个相邻段，所述介电区域的所述表面的至少一部分在所述至少两个相邻段之间暴露，所述导电元件具有沿所述介电区域的所述表面至少为所述高度十倍的长度；及
（c）进行以下之一：
在所述导电垫上施加熔点低于300℃的导电结合材料，所述导电结合材料与所述表面的位于所述至少两个相邻段之间的所述部分桥接；或
组装所述元器件与所述第二元器件，利用熔点低于300℃的导电结合材料使所述导电垫与所述第二元器件的导电垫接合，所述导电结合材料与所述介电区域的所述表面在所述至少两个相邻段之间的所述暴露部分桥接。
67.根据权利要求66所述的方法，其中步骤（c）包括，在所述导电垫上施加所述结合材料，所述结合材料与所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接。
68.根据权利要求66所述的方法，其中步骤（c）包括，组装所述元器件与所述第二元器件，利用所述结合材料使所述导电垫与所述第二元器件的导电垫接合，所述结合材料与所述介电区域的所述表面的位于所述至少两个相邻段之间的所述暴露部分桥接。
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