TW201312720A - 藉由嵌入跡線界定之導電墊 - Google Patents

藉由嵌入跡線界定之導電墊 Download PDF

Info

Publication number
TW201312720A
TW201312720A TW101144063A TW101144063A TW201312720A TW 201312720 A TW201312720 A TW 201312720A TW 101144063 A TW101144063 A TW 101144063A TW 101144063 A TW101144063 A TW 101144063A TW 201312720 A TW201312720 A TW 201312720A
Authority
TW
Taiwan
Prior art keywords
component
conductive
conductive element
dielectric region
pad
Prior art date
Application number
TW101144063A
Other languages
English (en)
Other versions
TWI482255B (zh
Inventor
Haba Belgacem
Original Assignee
Tessera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera Inc filed Critical Tessera Inc
Publication of TW201312720A publication Critical patent/TW201312720A/zh
Application granted granted Critical
Publication of TWI482255B publication Critical patent/TWI482255B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/031—Manufacture and pre-treatment of the bonding area preform
    • H01L2224/0311—Shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05576—Plural external layers being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29016—Shape in side view
    • H01L2224/29018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1037—II-VI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20107—Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Micromachines (AREA)

Abstract

本發明提供一種總成及其製作方法。該總成可包括：一第一組件，其包括具有一經曝露表面之一介電區；一導電墊，其在該表面處，由具有沿該表面以一振盪或螺旋路徑延伸之至少一部分之一導電元件界定；及一導電結合材料，其接合至該導電墊並橋接毗鄰段之間的該介電表面之一經曝露部分。該導電墊可准許該第一組件與具有透過該導電結合材料接合至該墊的一端子之一第二組件的電互連。該導電元件之該路徑可或可不自身重疊或交叉。

Description

藉由嵌入跡線界定之導電墊
本發明係關於微電子裝置之形成，尤其是半導體墊之形成。
本申請案請求於2010年11月15日提出申請之韓國申請案第10-2010-0113272號之優先權，本申請案之揭示內容以引用之方式藉此併入本文中。
微電子裝置一般包含通常稱作一晶粒或一半導體晶片之一半導體材料(諸如矽或砷化鎵)之一薄板。半導體晶片通常係以個別的預封裝單元形式提供。在一些單元設計中，半導體晶片安裝至一基板或晶片載體，該基板或晶片載體又安裝於一電路面板(諸如一印刷電路板)上。
主動電路製造於半導體晶片之一第一面(例如，一前表面)中。為促進至主動電路的電連接，晶片在同一面上具備接合墊。接合墊一般係由厚約0.5 μm之一導電金屬(諸如銅或鋁)製成。該等接合墊可包括一單個金屬層或多個金屬層。接合墊之大小將隨裝置類型而變化但通常將在一側上量測為數十或數百微米。
微電子裝置通常安裝於包括一介電元件之封裝中，該介電元件上具有一組導電元件(諸如端子或其他導電墊)。一經封裝晶片或在一些情形中一裸晶片可安裝至一電路面板之導電墊並與其電互連。傳統上，此介電元件或電路面板上之導電墊可係藉由光柵掃描或光微影而形成。此等製程 可涉及缺點。藉由光柵掃描雷射形成導電墊可產生具有不均勻平面之墊，此乃因每一連續經光柵掃描之段與先前段部分地重疊。特別係對於小生產數量而言，光微影可效率低下，此乃因設計、測試並校正針對一特定應用或系統最佳化之一遮罩可係繁重的。
尺寸在任何晶片實體配置中皆係一重要考慮因素。對於更緊湊的實體晶片配置之需求已隨著可攜式電子裝置之迅速發展而變得更加強烈。僅藉助實例方式，通常稱作「智能電話」之裝置將一蜂巢式電話之功能與強大的資料處理器、記憶體及輔助裝置(諸如全球定位系統接收器、電子相機及局域網路連接)以及高解析度顯示器及相關聯之影像處理晶片整合在一起。此等裝置可將諸如全網際網路連接性、包括全解析度視訊之娛樂、導航、電子銀行業務及更多之能力全部提供於一袖珍型裝置中。複雜的可攜式裝置需要將眾多晶片封裝至一小空間中。此外，該等晶片中之一些晶片具有許多通常稱作「I/O」之輸入及輸出連接。此等I/O須與其他晶片之I/O互連。該等互連應較短且應具有低阻抗以最小化信號傳播延遲。形成該等互連之組件不應顯著增加該總成之尺寸。類似需要出現在其他應用中，如(例如)出現在諸如用於網際網路搜索引擎之資料伺服器之資料伺服器中。舉例而言，在複雜晶片之間提供眾多較短、低阻抗互連之結構增加搜索引擎之頻寬並減小其功率消耗。
儘管已在具有導電墊之組件之製造中做出或提出改進， 但仍可做出進一步改良。
本發明之一第一態樣係一種總成，其包括：一第一組件，其包括具有一經曝露表面之一介電區；一導電墊，其在該表面處從而准許該第一組件與一第二組件之電互連，該導電墊係由一導電元件界定，該導電元件具有在沿該表面之一振盪或螺旋路徑中之至少一者中延伸之至少一部分以使一理論直線與該路徑之至少三個段相交且該導電元件之至少兩個毗鄰段係由不被該導電元件覆蓋之該表面之一部分分離，該導電元件自該表面延伸至該表面上方之一高度處之一頂部表面且沿該表面具有至少十倍於該高度之一長度；及具有300℃以下的一熔化溫度之一導電結合材料，其接合至該導電墊且橋接該等至少兩個毗鄰段之間的該表面之該經曝露部分，其中該導電元件具有延伸遠離該頂部表面之邊緣表面且該導電結合材料接觸該導電元件之該等頂部及邊緣表面。
根據此第一態樣之某些實施例，該總成可進一步包括具有透過導電結合材料接合至導電墊的一端子之第二組件。該導電元件之路徑可不自身重疊或交叉。該導電元件之路徑可至少自身重疊或交叉。該導電元件可佔用小於由該墊之最外邊緣界定之一圓形邊界內之介電區之表面之一面積的75%。該第一組件可進一步包括具有一基板表面之一基板，該介電區至少部分地上覆於該基板表面上。該基板表面可係該基板之一頂部表面，該基板進一步具有遠離該頂 部表面之一底部表面，延伸於該頂部與底部表面之間之一開口及安置於該底部表面處之一第二導電元件，該墊透過該基板中之開口及該介電區中之一開口而電連接至該第二導電元件。
該介電區之表面可曝露於該第一組件之經曝露表面處，該第一組件進一步具有遠離該經曝露表面之一底部表面、延伸於該頂部與底部表面之間之一開口及安置於該底部表面處之一第二導電元件，該墊透過該第一組件中之開口及該介電區中之一開口而電連接至該第二導電元件。該經曝露表面可係一背面，且該第一組件可具有遠離該背面之一正面及延伸於正面與背面之間之一開口，且其中該導電元件曝露於該背面處且該導電元件之至少一部分沿該開口之一內表面延伸。該第一組件可在該正面處具有至少一個觸點，該至少一個觸點與該導電元件之間的電連接係透過該開口進行的。該第一組件可係具有毗鄰該正面之複數個主動半導體裝置之一微電子元件。
該第一組件可係具有表面處的複數個觸點之一微電子元件，且該總成可進一步包括電連接該導電墊與該複數個觸點中之至少一者之一跡線。該第一組件可係其上具有複數個跡線之一介電元件，其中該導電墊與該等跡線中之至少一者電連接。該表面可係一第一表面，該第一組件可係具有遠離該第一表面之一第二表面處的複數個觸點之一微電子元件，且該導電墊可與該複數個觸點中之至少一者電連接。該導電結合材料可係焊料。該墊可包括一表面層，該 表面層包括鎳或金中之至少一者，且導電結合材料接觸該表面層。一系統可包括如上文所闡述之一總成及電連接至該總成之一個或多個其他電子組件。該系統可進一步包括一外殼，該總成及該等其他電子組件安裝至該外殼。
本發明之一第二態樣係一種總成，其包括：一第一組件，其包括具有一經曝露表面之一介電區；一連續凹槽，其沿該表面延伸且具有沿該表面於一彎曲路徑中延伸之至少一部分，該凹槽具有安置於該表面下面之一底面；一導電墊，其曝露於該表面處從而准許該第一組件與一第二組件的電互連，該導電墊係由一導電元件界定，該導電元件具有由該凹槽至少部分地界定之剖面尺寸，自該凹槽之該底面延伸至該底面上方之一高度，且具有在沿該表面之一振盪或螺旋路徑中之至少一者中延伸之至少一部分以使一理論直線與該路徑之至少三個段相交，該導電元件具有由該介電區之該表面之一經曝露部分分離之至少兩個毗鄰段，且該導電元件具有沿該表面至少十倍於該高度之一長度；及具有300℃以下的一熔化溫度之一導電結合材料，其接合至該導電墊且橋接該等至少兩個毗鄰段之間的該表面之該經曝露部分。
根據此第二態樣之某些實施例，該第一組件可係具有其表面處的複數個觸點及毗鄰該表面之複數個主動半導體裝置之一微電子元件，且該總成可進一步包括電連接該導電墊與該複數個觸點中之至少一者之一跡線。該第一組件可係其上具有複數個跡線之一介電元件，其中該導電墊可與 該等跡線中之至少一者電連接。該表面可係一第一表面，該第一組件可係在遠離該第一表面之一第二表面處具有複數個觸點及毗鄰該第二表面之複數個主動半導體裝置之一微電子元件，且該導電墊可與該複數個觸點中之至少一者電連接。
該總成可進一步包括該第二組件，導電結合材料將該導電墊與該第二組件之一端子接合在一起。該導電結合材料可係焊料。該第一組件可包括延伸於該正面與該背面之間之一開口及沿該開口之一內表面延伸之導電元件之至少一部分，凹槽之至少一部分沿該內表面延伸，導電元件在該凹槽之該部分內延伸。該至少一個觸點與該導電元件之間的電連接係透過該開口進行的。該導電元件之高度可大於該介電區之底面與表面之間的一距離。該導電元件之高度可等於或小於該介電區之底面與表面之間的一距離。
該墊之最外邊緣可相對於該表面界定一圓形或正方形形狀的邊界。該導電元件之路徑可不自身重疊或交叉。該導電元件之路徑可至少自身重疊或交叉。該導電元件可佔用小於該邊界內之表面之表面積的75%。該導電元件之高度可大於該底面與該表面之間的一距離以使得該導電元件具有曝露於該介電區之表面處之頂部表面及遠離該頂部表面而延伸之邊緣表面，導電結合材料接觸該導電元件之頂部及邊緣表面。該墊可包括一表面層，該表面層包括鎳或金中之至少一者。
該介電區之表面可曝露於該第一組件之經曝露表面處， 該第一組件可進一步包括與該經曝露表面對置之一底部表面、延伸於該經曝露表面與底部表面之間之一開口及上覆於該底部表面上之一第二導電元件，該墊透過該第一組件中之開口及該介電區中之一開口而電連接至該第二導電元件。該介電區可包括一焊料遮罩。該介電區可係一聚合材料。該介電區可係一無機材料。該介電區可包括兩個或兩個以上介電材料堆疊層，其至少兩個毗鄰層包括不同材料。一系統可包括如上文所闡述之一總成及電連接至該總成之一個或多個其他電子組件。該系統可進一步包括一外殼，該總成及該等其他電子組件安裝至該外殼。
本發明之一第三態樣係一種在一第一組件上形成一導電結構之方法，其包括(a)藉由移除一第一組件之一介電區之一部分而形成沿該介電區之一經曝露表面延伸之一連續凹槽，該凹槽具有在一彎曲路徑中延伸之至少一部分，該凹槽具有安置於該表面下面之一底面；(b)形成曝露於該表面處從而准許該第一組件與一第二組件的電互連之一導電墊，該導電墊係由具有由該凹槽之該路徑至少部分地界定之剖面尺寸及一路徑且自該凹槽之該底面延伸至該底面上方之一高度之一導電元件界定，該導電元件具有在沿該表面之一振盪或螺旋路徑中之至少一者中延伸之至少一部分以使一理論直線與該路徑之至少三個段相交，該導電元件具有由該表面之一部分分離之至少兩個毗鄰段，該導電元件具有沿該表面至少十倍於該高度之一長度，該導電元件至少部分地嵌入於該凹槽中；及(c)執行以下操作中之一 者：將具有低於300℃之一熔化溫度之一導電結合材料施加至該導電墊，該導電結合材料橋接該至少兩個毗鄰段之間的該表面之該經曝露部分；或藉助將該導電墊接合至該第二組件之一導電墊之具有低於300℃之一熔化溫度之一導電結合材料來組裝該組件與該第二組件，該導電結合材料橋接該至少兩個毗鄰段之間的該介電區之該表面之該經曝露部分。
根據此第三態樣之某些實施例，該導電元件之該高度可大於該底面與該表面之間的一距離。該導電元件可包括平行於該介電區之表面之一經曝露頂部表面及延伸於其頂部表面與該介電區之該表面之間之經曝露垂直表面，導電結合材料與該導電元件之該等頂部及垂直表面接觸。該導電元件之高度可等於或小於該底面與該表面之間的一距離。該底面與該表面之間的一距離可大於該導電元件之一寬度。
步驟(b)可包括形成該導電元件以使其不自身重疊或交叉。步驟(b)可包括形成該導電元件以使其至少自身重疊或交叉。步驟(c)可包括形成上覆於該凹槽之至少該底面上之一觸媒層，且然後將一金屬選擇性地沈積至其中可存在該觸媒層之一區域上以形成該導電元件。該導電結合材料可至少延伸於該第一組件之該墊之最外邊緣之間。步驟(b)可包括鍍敷包括曝露於該第一組件之該墊之一表面處之鎳或金中之至少一者之一表面層。
該第一組件可包括一第二區，當執行步驟(a)及步驟(b) 時介電區上覆於該第二區上。該基板可具有與該頂部表面對置之一底部表面、延伸於該等頂部與底部表面之間之一開口及上覆於該下部表面上之一導電元件，該第一組件之墊透過該基板中之該開口及該介電區中之一毗鄰開口電連接至導電元件。
可藉由包括以下各項中之至少一者之處理來執行步驟(a)：朝向至少該表面引導一雷射以燒蝕該介電區之該部分、機械銑削(mechanical milling)或噴砂。步驟(b)可包括將一金屬模板定位成上覆於該介電區上，該金屬模板具有至少一個開口；且藉由噴砂來移除透過該至少一個開口而曝露之介電區之該部分。步驟(b)可包括藉由機械銑削來移除該介電區之一部分。步驟(b)可包括沈積上覆於該介電區之表面及該凹槽之至少一部分上之一導電材料，且移除上覆於該表面之至少一部分上之該導電材料以曝露該介電區之該表面。
步驟(c)可包括將該導電結合材料施加至該導電墊，該導電結合材料橋接該至少兩個毗鄰段之間的該表面之該經曝露部分。步驟(c)可包括藉助將該導電墊接合至該第二組件之一導電墊之一導電結合材料來組裝該組件與該第二組件，該導電結合材料橋接該至少兩個毗鄰段之間的該介電區之該表面之該經曝露部分。
本發明之一第四態樣係一種形成一第一組件總成之方法，該方法包括(a)將一導電墊鍍敷至一心軸之一平坦表面上，該導電墊係由沿該表面延伸且具有在沿該表面之一彎 曲路徑中延伸之至少一部分之一導電元件界定；(b)將該導電墊至少部分地嵌入至一介電材料中；(c)移除該心軸以形成具有一介電區及曝露於該介電區之一表面處以用於准許該組件與一第二組件的電互連之該導電墊之該第一組件，該導電墊之該導電元件具有在沿該介電區之該表面之一振盪或螺旋路徑中之至少一者中延伸之至少一部分以使一理論直線與該路徑之至少三個段相交，該導電元件具有由該介電區之該表面之一部分分離之其至少兩個毗鄰段，該介電區之該表面之至少一部分曝露於該至少兩個段之間，該導電元件具有沿該介電區之該表面至少十倍於該高度之一長度；及(d)執行以下操作中之一者：將具有低於300℃之一熔化溫度之一導電結合材料施加至該導電墊，該導電結合材料橋接該至少兩個毗鄰段之間的該表面之該經曝露部分；或藉助具有低於300℃之一熔化溫度將該導電墊接合至該第二組件之一導電墊之具有低於300℃之一熔化溫度之一導電結合材料來組裝該組件與該第二組件，該導電結合材料橋接該至少兩個毗鄰段之間的該介電區之該表面之該經曝露部分。
根據此第四態樣之某些實施例，該心軸可包括一金屬片，且步驟(c)可包括蝕刻該金屬片以曝露該第一組件之該墊。步驟(b)可包括將該第一組件之該導電墊嵌入至包括該介電材料之一至少部分固化之介電區中。步驟(b)可包括將該介電材料沈積為接觸該第一組件之該導電墊之至少一部分。步驟(d)可包括將該導電結合材料施加至該導電墊，該 導電結合材料橋接該至少兩個毗鄰段之間的該表面之該經曝露部分。步驟(d)可包括將該組件與具有該導電結合材料之該第二組件組裝在一起，該導電結合材料將該導電墊接合至該第二組件之一導電墊，該導電結合材料橋接該至少兩個毗鄰段之間的該介電區之該表面之該經曝露部分。
本發明之一第五態樣係一種形成一組件總成之方法，該方法包括(a)提供具有一導電墊之一引線框架，該導電墊係由沿該表面延伸且具有在沿該表面之一彎曲路徑中延伸之至少一部分之一導電元件界定；(b)將該引線框架至少部分地嵌入於一介電材料中，其中該導電墊可曝露於該介電材料之一表面處以用於准許該組件與一第二組件的電互連，該導電墊之該導電元件具有在沿該介電區之該表面之一振盪或螺旋路徑中之至少一者中延伸之至少一部分以使一理論直線與該路徑之至少三個段相交，該導電元件具有由該介電區之該表面之一部分分離之其至少兩個毗鄰段，該介電區之該表面之至少一部分曝露於該至少兩個段之間，該導電元件具有沿該介電區之該表面至少十倍於該高度之一長度；及(c)執行以下操作中之一者：將具有低於300℃之一熔化溫度之一導電結合材料施加至該導電墊，該導電結合材料橋接該至少兩個毗鄰段之間的該表面之該經曝露部分；藉助具有低於300℃之一熔化溫度將該導電墊接合至該第二組件之一導電墊之具有低於300℃之一熔化溫度之一導電結合材料來組裝該組件與該第二組件，該一導電結合材料橋接該至少兩個毗鄰段之間的該介電區之該表面之 該經曝露部分。
根據此第五態樣之某些實施例，步驟(c)可包括將該導電結合材料施加至該導電墊，該導電結合材料橋接該至少兩個毗鄰段之間的該表面之該經曝露部分。步驟(c)可包括藉助將該導電墊接合至該第二組件之一導電墊之一導電結合材料來組裝該組件與該第二組件，該導電結合材料橋接該至少兩個毗鄰段之間的該介電區之該表面之該經曝露部分。
如在本發明中所使用，一導電元件「曝露於」一介電元件之一表面處之一陳述指示該導電元件可供用於與一理論點接觸，該理論點在垂直於該介電元件之表面之一方向上自該介電元件外側朝該介電元件之該表面移動。因此，曝露於一介電元件之一表面處之一端子或其他導電元件可自此表面凸出；可與此表面齊平；或可相對於此表面凹入且透過該電介質中之一孔或凹坑而曝露。
將根據圖8及圖9中所展示之一總成100之一第一實施例之構建方法對其進行闡述。總成100包括(例如)圖1及圖2中所展示之一第一組件105。該組件包括至少一介電區120且亦可包括下伏於介電區120之一支撐元件(例如，一基板)。該第一組件可係(例如)欲製造至一晶片載體中之一介電元件、一封裝之其他組件或一電路面板。基板110可係組件105之一額外介電層或可係其他結構，如下文所進一步闡述。如圖1至2中所參見。具有一底面126之一連續凹槽124 經形成以沿該介電區之表面122延伸。底面126被定義為凹槽124之最低部分。凹槽124之至少一部分相對於表面122在一彎曲路徑中延伸。
可藉由移除介電區120之一部分來形成凹槽124，在一個實例中這可由藉由在表面122處指引一雷射之雷射燒蝕來完成。舉例而言，一系統(例如，一電腦)可用以將雷射所產生之一照明斑點移動至表面122之不同位置。雷射燒蝕或其他方式移除一犧牲層(若存在)之一部分及介電區120之一部分。繪示凹槽124具有彎曲或圓形底面126，但可有意地或由於使用一雷射之約束條件而形成其他剖面，諸如矩形。
雖然未繪示，但可在藉助雷射燒蝕之步驟之前上覆於介電區120之表面122上而提供該犧牲層。該犧牲層通常可係一聚合材料且具有符合表面122之一輪廓之一經曝露表面。可藉由噴塗、旋塗、浸漬或其他方法來施加該犧牲層。在一特定實施例中，可藉由化學手段(諸如藉由使用一蝕刻劑)來移除該犧牲層。在一項實施例中，可藉由剝落來移除該犧牲層。儘管可使用一犧牲層，但形成凹槽124不需要使用一犧牲層。
在形成凹槽之後，形成在沿表面122之凹槽之一方向上延伸之一導電元件。在一項實施例中，可上覆於介電區120之經曝露部分及/或犧牲層(若存在)上來形成觸媒層。該觸媒層至少上覆於凹槽124之底面126上且通常係由可催化一後續金屬沈積製程(例如用以於其上鍍敷金屬層之一 後續水沈積製程)之一金屬粒子薄層構成。在一個實例中，該觸媒層可包括鉑粒子。在一個實例中，可藉由將含有觸媒粒子之一液體提供至該犧牲層之經曝露表面(例如，藉由將該基板浸漬於含有觸媒粒子之浴盆中)來形成該觸媒層。該觸媒層通常均勻地塗佈第一組件105。自第一組件105移除該犧牲層(若存在)從而亦移除安置於該犧牲層上之該觸媒層。以此方式，在已移除該犧牲層之後，僅該觸媒層安置於凹槽124中。若不存在任何犧牲層，則可僅在欲經鍍敷以形成一導電元件之第一組件105之區域(例如，其僅可係凹槽124中之區域)中或沿該區域沈積該觸媒層。
然後可將一晶種層選擇性地沈積至該觸媒層上，且該製程可繼續沈積一個或多個金屬層(其可包括一黏合層、一障壁金屬層及一初級金屬層中之任一者或全部)。通常，藉由鍍敷來沈積此晶種層、黏合層、障壁金屬層或初級金屬層。一金屬選擇性地沈積至其中存在觸媒層之一區域上之此製程之結果係形成於凹槽124中之一導電元件132(如圖3及圖4中所參見)之形成。圖4中更清晰地展示，導電元件134之剖面尺寸(亦即，凹槽124之底面126上方之導電元件132之一寬度及一高度或厚度)至少部分地由凹槽124界定。將導電元件132繪示為具有一平坦頂部表面135，但實際上可出現某一程度之一「U」形狀之表面。導電元件132之高度可因此界定為自其最低點(亦即，凹槽124之最低點)延伸至其最高點。圖2中所展示之凹槽124之對應剖面尺 寸：一深度128及一寬度130幫助界定導電元件132。在介電區120之底面126與表面122之間量測深度128。該深度可大於該凹槽之寬度130，如在沿表面130之一垂直方向(其垂直於凹槽124之深度128及一縱向方向125)上所量測。此外，深度128可大於導電元件132之一寬度(其對應於寬度130)。以此方式，導電元件132可具有符合凹槽124之內表面之一輪廓且至少部分地嵌入於介電區120中之凹槽124內。在一項實施例中，導電元件132之高度可在沿該導電元件之段之其整個路徑中至少大致相同。
在上文所闡述之實施例之一變型中，可在沈積構成導電元件132之金屬層中之一者或多者之後移除犧牲層。舉例而言，在一項實施例中，可在沈積一晶種層、一黏合層、一障壁金屬層或在初級金屬層沈積之前所提供之其他金屬層中之任一者或全部之後移除該犧牲層。在此情形中，可(諸如)藉由蝕刻、剝落或其他方法在一「剝離」製程中自該介電區移除該犧牲層。然後，在移除該犧牲層之後，該金屬沈積可繼續沈積一個或多個後續金屬層(包括初級金屬層)以形成導電元件132。
如圖3至圖4中所參見，導電元件132形成曝露於介電區120之表面122處之一墊134。墊134可連接至一個或多個其他導電元件(未展示)(諸如一導電跡線)、其他導電墊或其他電路組件或以與其整合在一起之方式而形成。此其他導電元件可自導電元件134之一個或多個位置(諸如端139或路徑位置141)延伸或連接至該一個或多個位置。
墊134准許第一組件105與一第二組件107之電互連，如圖10中所展示。墊134係由導電元件132界定，該導電元件具有剖面尺寸及至少部分地由凹槽124之路徑界定之一路徑。導電元件132自凹槽124之底面126延伸至底面126上方之一高度。如圖4中所展示，導電元件132之高度大於底面126與表面122之間的一距離。然而，在圖5及圖6中所展示之本發明之替代性實施例中，該底面上方之導電元件之高度可分別等於或小於此距離。在圖5中，一導電元件232延伸至一底面226上方之等於一介電區220之底面226與一表面222之間的距離之一高度。在此情形中，導電元件232之頂部表面244可與介電區之表面222共面。圖6展示延伸至一底面326上方之小於一介電區320之底面326與一表面322之間的距離之一高度的一導電元件332。因此該導電元件之一頂部表面344安置於介電區之表面322下面。
如圖3中所展示，導電元件132包括由介電區120之一部分137分離之至少兩個毗鄰段136、138。因此，可認為一理論直線199與導電元件132之至少三個段136、138及150相交。導電元件132其整體上具有沿表面122至少十倍於如(例如)自底面126至頂部表面135而量測之其高度133之一長度。墊134可經構建以使導電元件132佔用小於一般由墊134之最外邊緣界定之一般係圓形形狀之一邊界146(如圖12中所展示)內之介電區120之表面122之一面積的約75%。在一較佳實施例中，根據本發明之一導電元件佔用此邊界內之一面積的10%至75%，且在某些實施例中，一導電元 件可佔用此邊界內之一面積的約25%。
以一種組態展示並闡述第一組件105，但可藉由本發明實現總成100及第一組件105之其他組態且下文將對其進行更全面闡述。舉例而言，第一組件105包括具有一螺旋路徑之導電元件132(如圖1及圖3中所展示)。在其他實例中，一第一組件505可包括在一表面522上具有一正弦曲線路徑之一導電元件532(如圖13中所展示)，或一第一組件605可包括在一表面622上具有一振盪路徑之一導電元件632(如圖14中所展示)。一正弦曲線路徑一般係波形狀，且一振盪路徑係沿自導電元件之開始至結束的方向一般以一左右搖擺方式延伸之路徑。一「振盪路徑」寬泛地闡述一導電元件之組態之一陣列，包括一正弦曲線路徑。此外，一振盪路徑無需如圖14中所展示而均勻。導電元件632可形成形成一墊之一部分的一振盪路徑，其中一個或多個部分以其他方式組態。舉例而言，一墊可包括形成一振盪路徑之一部分及與該振盪路徑交叉但不可特徵化為任一特定類型之形狀的另一部分。一振盪路徑可(例如)係三角波形狀、一「Z」字形圖案或任一其他類似圖案。沒必要使振盪路徑具有均勻長度之段636或使路徑反轉方向在段之間具有相同角634。該路徑之至少一些毗鄰段可不在其兩端處接合在一起。而是在一些情形中，導電元件可具有在為一導電墊所設定之一預定區域內「蜿蜒」之一振盪路徑，其中該路徑之段可具有變化的長度且可在段之間具有變化的角。在導電元件532及632之情形中，每一者可佔用小於一 般分別由導電元件532及632之最外邊緣界定之一般係圓形形狀之一邊界內之其各別表面522、622之一面積的約75%。根據本發明，可實現一導電元件之任一其他期望形狀或組態以形成一墊。本發明之一個優點係藉助安置於一般外邊界內之一導電元件之任一圖案界定一墊之該邊界之能力。因此，導電元件不需要一精確圖案，但由於其作為一墊之整體結構而有效。如圖3中所展示，導電元件132不沿其路徑自身重疊或交叉。在替代性實施例(諸如圖11中所繪示)中，一第一組件405之一導電元件432可在一表面422上於一個或多個區域中自身重疊或交叉。
在形成墊134之另一方法中，可沈積上覆於介電區120之表面122及凹槽124之至少一部分上之一導電材料。然後可移除上覆於表面122之至少一部分上之某些導電材料以曝露介電區120之表面122。
在形成墊134之後，可沈積至少部分地上覆於墊134上之一導電結合材料140，如圖8及圖9中所展示。較佳地具有低於300℃之一熔化溫度且可係一焊料材料之導電結合材料140可至少在墊134之最外邊緣之間延伸以便當自正交於表面122之一方向觀察時整體覆蓋墊134，如圖8中所展示。導電結合材料140接合至導電墊134以橋接導電元件132之段136、138之間的介電區120之部分137，如圖3中更清晰地展示。圖10中所展示之第二組件107包括透過結合材料140接合至墊134之一端子108。儘管可在將第一組件105與第二組件107組裝在一起之前將結合材料140直接施 加至墊132，但可將結合材料140替代性地僅施加至第二組件107之端子108或可在將該等組件組裝在一起之前將其單獨施加至墊132及端子108中之每一者。
如圖9中所展示，在導電元件132延伸至表面122上方之一高度之情形下，導電元件132包括曝露於介電區120之表面122上方之一經曝露頂部表面144及延伸於頂部表面144與表面122之間之經曝露「垂直表面」142。「垂直表面」142係遠離頂部表面144而延伸之邊緣表面，但其可或可不在相對於頂部表面144及介電區表面122之一垂直或正交方向上。結合材料140與頂部表面144及垂直表面142接觸。在替代性實施例(諸如圖5及圖6中所繪示之彼等實施例)中，結合材料以一不同方式接觸導電元件及表面。在圖5中，一頂部表面144與介電區220之表面222基本上齊平。因此，結合材料將具有與導電元件232之頂部表面244及表面222接觸之一基本上平坦表面。在圖6中，在導電元件332之一頂部表面344安置於表面322下面之情形下，結合材料亦接觸曝露於導電元件332之頂部表面344與介電區320之表面322之間的凹槽324之垂直表面348。將瞭解，可與結合材料接觸之表面積越多，結合材料與該第一組件之間的黏合就越大。此外，可鍍敷包括鎳、金或另一金屬之一表面層或使其以其他方式曝露於墊134之一個或多個表面處，諸如頂部及邊緣表面142、144處。
根據本發明，第一組件之實施例可係由一單個介電區構成，可包括下伏於一介電區之一基板或可包含以一堆疊構 形之多於一個之介電區或層。該介電區可包含介電材料之兩個或多個經堆疊層，其中其至少兩個毗鄰層包括不同材料。該介電區通常包括一個或多個介電材料(諸如以任一形式之二氧化矽)、其他矽介電化合物、一聚合材料或其他無機介電材料(諸如一陶瓷材料)以及其他材料。根據本發明之一基板通常基本上由一單晶質半導體材料(諸如，例如矽)、矽與另一材料之一合金、一個或多個III-V半導體化合物(諸如砷化鎵等材料)或一個或多個II-VI半導體化合物組成。在一特定實施例中，該基板可係一絕緣體上矽基板，其包括使一正面處之一主動半導體裝置與一背面處之一塊狀半導體區分離之一掩埋式氧化物(「BOX」)層。
在圖7中所展示之一實施例中，基板110包括延伸於背面112與正面114之間之一開口116，及安置於正面114處之複數個導電元件118。導電元件132藉由延伸透過基板110上之開口116及介電區120中之一毗鄰開口而將墊134電連接至導電元件118中之至少一者。凹槽124之至少一部分可沿開口116之一內表面延伸，且導電元件132可在凹槽124之該部分內延伸。
一第一組件705之另一實施例展示於圖15至圖18中，且包括一晶片710及上覆於晶片710之一上表面上之一鈍化層703。一結合墊750安置於鈍化層703之一經曝露表面704上，該鈍化層係具有一經曝露表面之一介電區。一導電墊734亦以上文所闡述之一方式形成於表面704上。一跡線752與晶片750電連接且沿表面704延伸以與墊734之一部分 電連接。跡線752可在如上文所概述之一製程期間結合墊734一起形成，或可在墊734已形成之後經形成以使晶片750與墊734電連接。複數個跡線亦可或替代性地定位於跡線752所安置之位置中，如圖15中所展示。
墊734允許晶片750與可接合至其的一外部組件之間的電連接，如(例如)上文參照圖10所闡述。在彼方面，如圖17中所展示，可(諸如)藉由使用一光微影方法沈積上覆於鈍化層703及跡線752上之一焊料遮罩756。墊132因此可保持曝露且可被一導電結合材料740覆蓋(圖18)。然後另一組件可以與圖10中所繪示之方式類似之一方式透過結合材料740電連接至晶片750。另一選擇為，具有其上有結合材料之一端子的一第二組件可接合至墊734以形成電連接。
圖19至圖22中繪示一進一步實施例，該等圖中展示形成根據本發明之一第一組件805之另一方法。在一心軸860或其他類型之引線框架之一平坦表面862上形成一導電墊834(圖19至圖20)。墊834形成為以如上文所論述之一類似組態之一經鍍敷導電元件。然後毗鄰一介電區820來定位心軸860以使墊834毗鄰介電區820之一表面822(圖21)。對心軸860施加力以使墊834嵌入至可至少部分地固化之介電區820中。然後移除心軸860，其中所得的第一組件805(圖22)類似於上文所闡述之實施例中之彼等第一組件。
在某些實施例中，心軸860可係由一個或多個金屬片構成，且可藉由蝕刻掉每一金屬片以曝露墊834來進行移除心軸860之步驟。在其他實施例中，可不預形成介電區 820，而是可使一介電材料沈積至心軸860之表面862上，且然後移除心軸860以形成第一組件805。
在本文所闡述之實施例中之任一或全部實施例中，如上文所闡述而具有一心軸或振盪路徑導電墊或根據上文所闡述之一技術而形成之一第一組件可接合或電連接至具有一導電結合材料之一第二組件，該導電結合材料以上文所闡述之一方式接觸該導電墊之表面且接觸該第二組件之一端子。該結合材料橋接該導電墊之至少兩個毗鄰段之間的介電區之表面之部分。可在將第一組件與第二組件組裝在一起之前將該結合材料施加至此導電墊，在此情形中該導電墊上之該結合材料將形成該第一與第二組件之間的接合或導電性連接之部分。另一選擇為，在將該第一與第二組件組裝在一起之前可將該結合材料施加至該第二組件之一端子而不施加至此導電墊。在該組裝步驟期間，來自該第二組件之端子的該結合材料將流動至該導電墊之表面上且然後將橋接該至少兩個毗鄰段之間的該介電區之表面之部分。在一個實例中，可藉由將一結合金屬(諸如焊料)加熱至足以致使該結合金屬流動之一溫度而形成一導電接合，然後該結合金屬接觸此墊之表面及與其並列之第二組件之一端子。然後該結合金屬再一次重新固化以形成該導電接合。在另一實例中，可將一結合材料單獨施加至此導電墊及一第二組件之一端子，這之後可將第一與第二組件拼在一起並如上文所闡述而接合。
根據本發明之一第一組件可係具有毗鄰該介電區之表面 的複數個主動半導體裝置之一微電子元件。在替代性實施例中，該第一組件可係具有其表面處的複數個觸點之一微電子元件，且可進一步包括使導電墊與該複數個觸點中之至少一者電連接之一跡線。在另外其他實施例中，該第一組件可係具有表面處的複數個觸點之一微電子元件，且該導電墊與該複數個觸點中之至少一者電連接。
在本發明之某些實施例中，一基板基本上係由單晶質半導體材料組成，且上覆於該基板上之一介電區包括符合該基板之一傾斜表面之一輪廓的一介電材料層。在替代性實施例中，該基板可基本上係由介電材料組成，或可包括基本上係由導電材料組成之一區，其中一介電區上覆於該導電材料區上。
作為光微影之一替代性方案而使用一雷射來形成導電元件可准許更輕易地改變該等元件之佈局。藉助目前方法，改變該佈局可僅需要對控制雷射之移動的一電腦程式進行改變，此乃因雷射之移動決定導電元件之形狀及尺寸。這與產生並驗證用以藉由光微影形成跡線之一光遮罩所需之時間及花費形成對比。
上文所闡述之實施例可包括(諸如)藉由(例如)使用一雷射之一直接寫入方法而形成之凹槽及孔口以界定一路徑。然而，可使用其他方法來形成根據本發明之此等特徵。可利用機械銑削，其中可稱作一錘子之一小直徑元件反覆擊打犧牲層(若存在)及介電區以鬆動並移除此材料以形成一凹槽或孔口。可利用之另一方法係與一金屬模板一起之一 噴砂技術，該金屬模板經定位以上覆於犧牲層及/或介電區上且包括根據導電元件之一期望最終圖案而成形之開口。藉由在一方向上於介電區處指引一基於砂之材料以使該基於砂之材料將在透過該等開口而曝露之區域中擊打犧牲層/或介電區而運用一噴砂技術。一個或多個凹槽藉此形成於該介電區中。可認為機械銑削及噴砂之此等特定技術係「非光微影技術」，此乃因其並非主要依賴使用一光阻劑透過一光遮罩之曝光而圖案化。在於2010年7月23日提出申請之共同擁有之美國申請案第12/842,669號中找到對此等圖案化技術及可隨其形成之其他結構之說明，該美國申請案之揭示內容以引用方式併入本文中。構建根據本發明之一結構之方法之剩餘步驟係如上文所陳述。
在一項實施例中，本文所揭示之方法可達成具有比藉由現有方法(諸如光柵掃描)而形成之彼等墊大的平面度之一墊之一頂部表面。由於根據本發明之墊通常包括由空隙分離之段，因此該頂部表面之平面度可係藉由共面或大致界定一單個平面之毗鄰段之頂部表面達成。
注意，移除犧牲層之某些方法需要該犧牲層生性較易碎。舉例而言，在一較易碎犧牲層之情形下更有效實施上文所闡述之噴砂技術，以便基於砂之材料不會嵌入於該犧牲層中而是破壞並移除該犧牲層。
在上文所論述之特定實施例中，所得總成可係或包括具有主動電路元件(例如，電晶體、二極體或其中的其他微電子或微電機裝置以及其他主動電路元件)之一微電子單 元，且可具有藉由如上文所闡述之該等技術中之一者或多者(例如，甚至非光微影技術)而形成之跡線。而且在上文所論述之某些實施例中，所得總成可係或包括具有半導體或介電材料中之至少一者之一基板的一插入物結構，該插入物結構具有如上文所闡述而形成之跡線但沒有其中的主動電路元件。根據此等實施例之一插入物結構或組件可具有曝露於正面及背面中之一者或多者處之導電元件以用於與一個或多個外部組件(諸如，例如一微電子元件、基板或電路面板)互連。
在上文所論述之特定實施例中，所得總成可係或包括具有主動電路元件(例如，電晶體、二極體或其中的其他微電子或微電機裝置以及其他主動電路元件)之一微電子單元，且可具有藉由如上文所闡述之該等方法中之一者或多者而形成之跡線。而且在上文所論述之某些實施例中，所得總成可係或包括具有半導體或介電材料中之至少一者之一基板的一插入物結構，該插入物結構具有藉由上文所闡述之方法中之一者或多者而形成之跡線但沒有其中的主動電路元件。根據此等實施例之一插入物結構或組件可具有曝露於正面及背面中之一者或多者處之導電元件以用於與一個或多個外部組件(諸如，例如一微電子元件、基板或電路面板)互連。
上文所論述之結構提供傑出的三維互連能力。此等能力可用於任一類型之晶片。僅僅藉助實例方式，以下晶片組合可包括於如上文所論述之結構中：(i)一處理器及用於該 處理器之記憶體；(ii)同一類型之多數個記憶體晶片；(iii)不同類型(諸如DRAM及SRAM)之多數個記憶體晶片；(iv)一影像感測器及用於處理來自該感測器之影像之一影像處理器；(v)一專用積體電路(「ASIC」)及記憶體。上文所論述之結構可用於構建不同電子系統。舉例而言，根據本發明之一另外實施例之一系統900包括如上文結合其他電子組件908及910所闡述之一結構906。在所繪示之實例中，組件908係一半導體晶片而組件910係一顯示螢幕，但可使用任何其他組件。當然，雖然為清楚說明起見圖23中僅繪示兩個額外組件，但該系統可包括任一數目個此類組件。如上文所論述之結構906可係(例如)一複合晶片或併入多個晶片之一結構。在一另外變體中，可提供該兩者，且可使用任一數目個此等結構。結構906和組件908及910安裝於以虛線示意性地繪示之一共同外殼901中，且視需要彼此電互連以形成期望電路。在所展示之實例性系統中，該系統包括諸如一撓性印刷電路板之一電路面板902，且該電路面板包括將該等組件彼此互連之眾多導體904(其中圖23中僅繪示一者)。然而，此僅係實例性的；可使用任一適合結構來進行電連接。外殼901繪示為(例如)可用於一蜂巢式電話或個人數位助理之類型之一可攜式外殼，且螢幕910曝露於該外殼之表面處。在結構906包括諸如一成像晶片之一感光元件之情形下，亦可提供一透鏡911或其他光學裝置以將光路由至該結構。再次，圖23中所展示之簡化系統僅係實例性的；可使用上文所論述之結構來製作其他 系統，包括通常被視為固定結構之系統，諸如桌上型電腦、路由器及諸如此類。
雖然本文已參照特定實施例闡述了本發明，但應理解，此等實施例僅圖解說明本發明之原理及應用。因此應理解，可對說明性實施例進行眾多改變並可設想出其他配置，而不背離隨附申請專利範圍所界定之本發明之精神及範疇。
100‧‧‧總成
105‧‧‧第一組件
107‧‧‧第二組件
108‧‧‧端子
110‧‧‧基板
112‧‧‧背面
114‧‧‧正面
116‧‧‧開口
118‧‧‧導電元件
120‧‧‧介電區
122‧‧‧表面
124‧‧‧凹槽
125‧‧‧縱向方向
126‧‧‧底面
128‧‧‧深度
130‧‧‧寬度
132‧‧‧導電元件
133‧‧‧高度
134‧‧‧墊
135‧‧‧頂部表面
136‧‧‧段
137‧‧‧部分
138‧‧‧段
139‧‧‧端
140‧‧‧結合材料
141‧‧‧路徑位置
142‧‧‧垂直表面
144‧‧‧頂部表面
146‧‧‧邊界
150‧‧‧段
199‧‧‧直線
220‧‧‧介電區
222‧‧‧表面
226‧‧‧底面
232‧‧‧導電元件
244‧‧‧頂部表面
320‧‧‧介電區
322‧‧‧表面
324‧‧‧凹槽
326‧‧‧底面
332‧‧‧導電元件
344‧‧‧頂部表面
348‧‧‧垂直表面
405‧‧‧第一組件
422‧‧‧表面
432‧‧‧導電元件
505‧‧‧第一組件
522‧‧‧表面
532‧‧‧導電元件
605‧‧‧第一組件
622‧‧‧表面
632‧‧‧導電元件
634‧‧‧角
636‧‧‧段
703‧‧‧鈍化層
704‧‧‧經曝露表面
705‧‧‧第一組件
710‧‧‧晶片
734‧‧‧導電墊
740‧‧‧導電結合材料
750‧‧‧結合墊
752‧‧‧跡線
756‧‧‧焊料遮罩
805‧‧‧第一組件
820‧‧‧介電區
822‧‧‧表面
834‧‧‧墊
860‧‧‧心軸
862‧‧‧表面
900‧‧‧系統
901‧‧‧共同外殼
902‧‧‧電路面板
904‧‧‧導體
906‧‧‧結構
908‧‧‧電子組件
910‧‧‧電子組件
911‧‧‧透鏡
圖1係根據本發明之具有一凹槽之一基板之一俯視平面圖；圖2係沿線A-A截取之圖1之基板之一剖面側視圖；圖3係具有一墊之圖1之該基板之一俯視平面圖；圖4係沿線B-B截取之圖3之該基板之一剖面側視圖；圖5至圖7係圖3之該基板及墊之替代性實施例之剖面側視圖；圖8係具有一結合材料之圖3之該基板及墊之一俯視平面圖；圖9係沿線C-C截取之圖8之該基板及結合材料之一剖面側視圖；圖10係附接至一第二組件之圖8之該基板、墊及結合材料之一剖面側視圖；圖11係具有一墊之圖1之該基板之一俯視平面圖；圖12係展示為定位於一邊界內之圖3之該墊之一俯視平面圖； 圖13及圖14係根據本發明之具有一墊之一基板之替代性實施例之俯視平面圖；圖15係根據本發明之具有與一晶片電連接之一墊之一基板之一俯視透視圖；圖16係沿線E-E截取之圖15之該基板之一剖面側視圖；圖17係圖15之該基板及墊之一替代性實施例之一剖面側視圖；圖18係具有一結合材料之圖17之該基板及墊之一剖面側視圖；圖19係根據本發明之其上形成有一墊之一心軸之一俯視透視圖；圖20係沿線F-F截取之圖15之該心軸及墊之一剖面側視圖；圖21及圖22係展示嵌入至一介電區中之圖19之該墊之剖面側視圖；及圖23係對根據本發明之一項實施例之一系統之一示意性繪示。
703‧‧‧鈍化層
704‧‧‧經曝露表面
705‧‧‧第一組件
710‧‧‧晶片
734‧‧‧墊
750‧‧‧晶片
752‧‧‧跡線

Claims (51)

  1. 一種微電子裝置，其包含：一第一組件，其包括具有一經曝露表面之一介電區；一連續凹槽，其沿該表面以一路徑延伸，該凹槽具有安置於該表面下面之一底面；一導電墊，其曝露於該表面處以允許該第一組件與一第二組件的電互連，該導電墊由一導電元件界定，該導電元件具有由該凹槽至少部分地界定之剖面尺寸、自該凹槽之該底面延伸至該底面上方之一高度，且具有沿該表面以一振盪或螺旋路徑中之至少一者延伸之至少一部分，該路徑係形成以沿著該表面與一直線相交至少三次，該導電元件具有藉由該介電區之該表面之一部分分離之至少兩個毗鄰部分，且該導電元件具有沿該表面至少十倍於該高度之一長度；及一導電結合材料，其具有低於300℃之一熔化溫度，接合至該導電墊且橋接該導電元件之該至少兩個毗鄰部分之間的該表面之該部分。
  2. 如請求項1之微電子裝置，其進一步包含該第二組件，該結合材料藉由該第二組件之一終端接合該導電墊。
  3. 如請求項1之微電子裝置，其中該第一組件係具有該第一組件之一表面處之複數個觸點及毗鄰該第一組件之該表面之複數個主動半導體裝置之一微電子元件，該微電子裝置進一步包含電連接該導電墊與該複數個觸點中之至少一者之一跡線。
  4. 如請求項3之微電子裝置，其進一步包含該第二組件，該結合材料藉由該第二組件之一終端接合該導電墊。
  5. 如請求項1之微電子裝置其中該第一組件係其上具有複數個跡線之一介電元件，其中該導電墊與該等跡線中之至少一者電連接。
  6. 如請求項5之微電子裝置，其進一步包含該第二組件，該結合材料藉由該第二組件之一終端接合該導電墊。
  7. 如請求項1之微電子裝置，其中該第一組件包含一第一表面，該第一組件係具有遠離該第一表面之一第二表面處之複數個觸點及毗鄰該第二表面之複數個主動半導體裝置之一微電子元件，且該導電墊與該複數個觸點中之至少一者電連接。
  8. 如請求項7之微電子裝置，其進一步包含該第二組件，該結合材料接合該導電墊與該第二組件之一端子。
  9. 如請求項1之微電子裝置，其中該結合材料係焊料。
  10. 如請求項1之微電子裝置，其中該第一組件包括一第一表面、遠離該第一表面之一第二表面及延伸於該第一表面與該第二表面之間的一開口及沿該開口之一內表面延伸的該導電元件之至少一部分，該凹槽之至少一部分沿該內表面延伸，該導電元件在該凹槽之該部分內延伸。
  11. 如請求項10之微電子裝置，其中該第一組件包含位於該第二表面之複數個觸點，該等複數個觸點之至少一個係透過該開口電連接至該導電元件。
  12. 如請求項1之微電子裝置，其中該導電元件之該高度大 於該底面與該介電區之該表面之間的一距離。
  13. 如請求項1之微電子裝置，其中該導電元件之該高度等於或小於該底面與該介電區之該表面之間的一距離。
  14. 如請求項1之微電子裝置，其中該墊之最外邊緣相對於該表面界定一圓形或正方形形狀的邊界。
  15. 如請求項14之微電子裝置，其中該導電元件之該路徑不自身重疊或交叉。
  16. 如請求項14之微電子裝置，其中該導電元件之該路徑確實係自身重疊或交叉中之至少一者。
  17. 如請求項14之微電子裝置，其中該導電元件佔用小於該邊界內的該表面之表面積的75%。
  18. 如請求項1之微電子裝置，其中該導電元件之該高度大於該底面與該表面之間的一距離，以使得該導電元件具有曝露於該介電區之該表面處之頂部表面及延伸遠離該頂部表面之側表面，該結合材料接觸該導電元件之該頂部表面及該等側表面。
  19. 如請求項1之微電子裝置，其中該墊包括一表面層，該表面層包括鎳或金中之至少一者。
  20. 如請求項1之微電子裝置，其中該介電區之該表面係曝露於該第一組件之一經曝露表面處，該第一組件進一步具有與該第一組件之該經曝露表面對置之一底部表面、延伸於該第一組件之該經曝露表面與底部表面之間的一開口及上覆於該底部表面上之一第二導電元件，該墊透過該第一組件中之該開口及該介電區中之一開口而電連 接至該第二導電元件。
  21. 如請求項1之微電子裝置，其中該介電區包括一焊料遮罩。
  22. 如請求項1之微電子裝置，其中該介電區係一聚合材料。
  23. 如請求項1之微電子裝置，其中該介電區係一無機材料。
  24. 如請求項1之微電子裝置，其中該介電區包含兩個或兩個以上介電材料堆疊層，其中的至少兩個毗鄰層包括不同材料。
  25. 一種包含如請求項1之一微電子裝置之系統。
  26. 如請求項25之系統，其進一步包含一外殼，該微電子裝置係安裝至該外殼。
  27. 一種製造微電子裝置之方法，其包含：(a)藉由移除一第一組件之一介電區之一部分而形成沿該介電區之一表面在一路徑上延伸之一連續凹槽，該凹槽具有安置於該表面下面之一底面；(b)形成曝露於該表面處以允許該第一組件與一第二組件的電互連之一導電墊，該導電墊由一導電元件界定，該導電元件具有由該凹槽之該路徑至少部分地界定之剖面尺寸及一路徑且自該凹槽之該底面延伸至該底面上方之一高度，該導電元件具有沿該表面以一振盪或螺旋路徑中之至少一者延伸之至少一部分，該導電元件之該路徑係形成以沿著該表面與一直線相交至少三次，該導電 元件具有藉由該表面之一部分分離之至少兩個毗鄰部分，該導電元件具有沿該表面至少十倍於該高度之一長度，該導電元件至少部分地嵌入於該凹槽中；及(c)執行以下其中一者：將具有低於300℃之一熔化溫度之一導電結合材料施加至該導電墊，該導電結合材料橋接該導電元件之該至少兩個毗鄰部分之間的該表面之該部分；或藉助將該導電墊接合至該第二組件之一導電墊之具有低於300℃之一熔化溫度之一導電結合材料來組裝該第一組件與該第二組件，該導電結合材料橋接該導電元件之該至少兩個毗鄰部分之間的該介電區之該表面之該部分。
  28. 如請求項27之方法，其中該導電元件之該高度大於該底面與該表面之間的一距離。
  29. 如請求項28之方法，其中該導電元件包括平行於該介電區之該表面之一經曝露頂部表面及延伸於該導電元件之該頂部表面與該介電區之該表面之間的經曝露垂直表面，該結合材料與該導電元件之該頂部表面及垂直表面接觸。
  30. 如請求項27之方法，其中該導電元件之該高度等於或小於該底面與該表面之間的一距離。
  31. 如請求項27之方法，其中該底面與該表面之間的一距離大於該導電元件之一寬度。
  32. 如請求項27之方法，其中步驟(b)包括形成該導電元件以 使得其不自身重疊或交叉。
  33. 如請求項27之方法，其中步驟(b)包括形成該導電元件以使得其確實係自身重疊或交叉中之至少一者。
  34. 如請求項27之方法，其中步驟(b)包括形成上覆於該凹槽之至少該底面上之一觸媒層，且然後將一金屬選擇性地沈積至其中存在該觸媒層之一區域上以形成該導電元件。
  35. 如請求項27之方法，其中該結合材料至少延伸於該第一組件之該墊之最外邊緣之間。
  36. 如請求項27之方法，其中步驟(b)包括鍍敷曝露於該第一組件之該墊之一表面處包括鎳或金中之至少一者之一表面層。
  37. 如請求項27之方法，其中該第一組件包括一第二區，當執行步驟(a)及步驟(b)時該介電區上覆於該第二區上。
  38. 如請求項37之方法，其中該第一組件進一步包含一基板，其具有一頂部表面及與該頂部表面對置之一底部表面、延伸於該頂部表面與底部表面之間的一開口及上覆於該底部表面上之一導電元件，該第一組件之該墊透過該基板中之該開口及該介電區中之一毗鄰開口而電連接至該基板之該導電元件。
  39. 如請求項27之方法，其中藉由包括以下各項中之至少一者之處理來執行步驟(a)：朝向至少該表面引導一雷射以燒蝕該介電區之該部分、機械銑削或噴砂。
  40. 如請求項27之方法，其中步驟(a)包括將一金屬模板定位 成上覆於該介電區上，該金屬模板具有至少一個開口，且藉由噴砂來移除透過該至少一個開口而曝露的該介電區之該部分。
  41. 如請求項27之方法，其中步驟(a)包括藉由機械銑削來移除該介電區之一部分。
  42. 如請求項27之方法，其中步驟(b)包括沈積上覆於該介電區之該表面及該凹槽之至少一部分上之一導電材料，且移除上覆於該表面之至少一部分上之該導電材料以曝露該介電區之該表面。
  43. 如請求項27之方法，其中步驟(c)包括將該結合材料施加至該導電墊，該結合材料橋接該導電元件之該至少兩個毗鄰部分之間的該表面之該經曝露部分。
  44. 如請求項27之方法，其中步驟(c)包括藉助將一導電墊接合至該第二組件之該導電墊之該結合材料來組裝該第一組件與該第二組件，該結合材料橋接該導電元件之該至少兩個毗鄰部分之間的該介電區之該表面之該部分。
  45. 一種製造微電子裝置之方法，該方法包含：(a)將一導電墊鍍敷至一心軸之一平坦表面上，該導電墊由沿該表面延伸以一路徑延伸之一導電元件界定；(b)將該導電墊至少部分地嵌入至一介電材料中以形成一第一組件；(c)移除該心軸以形成具有一介電區及曝露於該介電區之一表面處以准許該第一組件與一第二組件的電互連之該導電墊之該第一組件，該導電墊之該導電元件具有 沿該介電區之該表面以一振盪或螺旋路徑中之至少一者延伸之至少一部分，該路徑係形成以沿著該表面與一直線相交至少三次，該導電元件具有藉由該介電區之該表面之一部分分離之至少兩個毗鄰部分，該導電元件具有沿該介電區之該表面之一長度，該長度至少大於該介電區之該表面上之該導電元件之一高度十倍；及(d)執行以下其中一者：將具有低於300℃之一熔化溫度之一導電結合材料施加至該導電墊，該導電結合材料橋接該導電元件之該至少兩個毗鄰部分之間的該表面之該部分；或藉助將該導電墊接合至該第二組件之一導電墊之具有低於300℃之一熔化溫度之一導電結合材料來組裝該第一組件與該第二組件，該導電結合材料橋接該導電元件之該至少兩個毗鄰部分之間的該介電區之該表面之該部分。
  46. 如請求項45之方法，其中該心軸包括一金屬片，且步驟(c)包括蝕刻該金屬片以曝露該第一組件之該墊。
  47. 如請求項45之方法，其中步驟(b)包括將該第一組件之該導電墊嵌入至包括該介電材料之一經至少部分固化之介電區中。
  48. 如請求項45之方法，其中步驟(b)包括將該介電材料沈積為接觸該第一組件之該導電墊之至少一部分。
  49. 如請求項45之方法，其中步驟(d)包括藉助將該導電墊接合至該第二組件之一導電墊之該結合材料來組裝該第一 組件與該第二組件。
  50. 一種製造微電子裝置之方法，該方法包含：(a)提供具有一導電墊之一引線框架，該導電墊由沿該引線框架之一表面在一路徑上延伸；(b)將該引線框架至少部分地嵌入於一介電材料中以形成一第一組件，其中該導電墊係曝露於該介電材料之一表面處以允許該第一組件與一第二組件的電互連，該導電墊之該導電元件具有沿該介電區之該表面以一振盪或螺旋路徑中之至少一者延伸之至少一部分，該路徑係形成以沿著該表面與一直線相交至少三次，該導電元件具有至少兩個毗鄰部分，其係藉由位於該導電元件之至少兩部分之間之該介電區之該表面之一部分來分離，，該導電元件具有沿該介電區之該表面之一長度，該長度至少大於該介電區之該表面上之該導電元件之一高度十倍；及(c)執行以下其中一者：將具有低於300℃之一熔化溫度之一導電接合材料施加至該導電墊，該導電接合材料橋接該導電元件之該至少兩個毗鄰部分之間的該表面之該部分；或藉助將該導電墊接合至該第二組件之一導電墊之具有低於300℃之一熔化溫度之一導電結合材料來組裝該第一組件與該第二組件，該導電結合材料橋接該導電元件之該至少兩個毗鄰部分之間的該介電區之該表面之該部分。
  51. 如請求項50之方法，其中該步驟(c)包含組合該第一組件與該第二組件，該結合材料將該導電墊接合至該第二組件之一導電墊。
TW101144063A 2010-11-15 2011-04-19 藉由嵌入跡線界定之導電墊 TWI482255B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100113272A KR101059490B1 (ko) 2010-11-15 2010-11-15 임베드된 트레이스에 의해 구성된 전도성 패드
US12/963,938 US8432045B2 (en) 2010-11-15 2010-12-09 Conductive pads defined by embedded traces

Publications (2)

Publication Number Publication Date
TW201312720A true TW201312720A (zh) 2013-03-16
TWI482255B TWI482255B (zh) 2015-04-21

Family

ID=44933774

Family Applications (2)

Application Number Title Priority Date Filing Date
TW101144063A TWI482255B (zh) 2010-11-15 2011-04-19 藉由嵌入跡線界定之導電墊
TW100113585A TWI401781B (zh) 2010-11-15 2011-04-19 藉由嵌入跡線界定之導電墊

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW100113585A TWI401781B (zh) 2010-11-15 2011-04-19 藉由嵌入跡線界定之導電墊

Country Status (6)

Country Link
US (2) US8432045B2 (zh)
JP (1) JP2014503992A (zh)
KR (1) KR101059490B1 (zh)
CN (1) CN103299419B (zh)
TW (2) TWI482255B (zh)
WO (1) WO2012067992A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI736093B (zh) * 2019-12-31 2021-08-11 財團法人工業技術研究院 封裝結構

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009018434B4 (de) * 2009-04-22 2023-11-30 Ev Group Gmbh Aufnahmeeinrichtung zur Aufnahme von Halbleitersubstraten
US9653419B2 (en) * 2015-04-08 2017-05-16 Intel Corporation Microelectronic substrate having embedded trace layers with integral attachment structures
CN104752443B (zh) * 2015-04-20 2016-03-02 京东方科技集团股份有限公司 衬底载板、柔性显示面板及相应的制作方法、柔性显示装置
US10080290B2 (en) * 2015-11-17 2018-09-18 Intel Corporation Stretchable embedded electronic package
EP3252873B1 (en) * 2016-06-02 2019-07-24 TE Connectivity Germany GmbH Lubricated contact element and method for production thereof

Family Cites Families (139)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160645A (ja) 1984-02-01 1985-08-22 Hitachi Ltd 積層半導体集積回路装置
NL8403613A (nl) 1984-11-28 1986-06-16 Philips Nv Elektronenbundelinrichting en halfgeleiderinrichting voor een dergelijke inrichting.
US4765864A (en) 1987-07-15 1988-08-23 Sri International Etching method for producing an electrochemical cell in a crystalline substrate
JPH03285338A (ja) * 1990-04-02 1991-12-16 Toshiba Corp ボンディングパッド
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
IL110261A0 (en) 1994-07-10 1994-10-21 Schellcase Ltd Packaged integrated circuit
GB2292015B (en) * 1994-07-29 1998-07-22 Plessey Semiconductors Ltd Trimmable inductor structure
US5703408A (en) * 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof
US6013948A (en) 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US5686762A (en) * 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
JP2904086B2 (ja) * 1995-12-27 1999-06-14 日本電気株式会社 半導体装置およびその製造方法
TW343210B (en) 1996-01-12 1998-10-21 Matsushita Electric Works Ltd Process for impregnating a substrate, impregnated substrate and products thereof
JP3699237B2 (ja) * 1996-03-13 2005-09-28 セイコーインスツル株式会社 半導体集積回路
US5808874A (en) 1996-05-02 1998-09-15 Tessera, Inc. Microelectronic connections with liquid conductive elements
US5700735A (en) * 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process
JP3620936B2 (ja) 1996-10-11 2005-02-16 浜松ホトニクス株式会社 裏面照射型受光デバイスおよびその製造方法
US5791911A (en) * 1996-10-25 1998-08-11 International Business Machines Corporation Coaxial interconnect devices and methods of making the same
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
US6136458A (en) * 1997-09-13 2000-10-24 Kabushiki Kaisha Toshiba Ferrite magnetic film structure having magnetic anisotropy
US6573609B2 (en) 1997-11-25 2003-06-03 Tessera, Inc. Microelectronic component with rigid interposer
EP0926723B1 (en) 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6879049B1 (en) * 1998-01-23 2005-04-12 Rohm Co., Ltd. Damascene interconnection and semiconductor device
US6982475B1 (en) 1998-03-20 2006-01-03 Mcsp, Llc Hermetic wafer scale integrated circuit structure
US5986343A (en) 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
US6492201B1 (en) 1998-07-10 2002-12-10 Tessera, Inc. Forming microelectronic connection components by electrophoretic deposition
US6555913B1 (en) * 1998-07-17 2003-04-29 Murata Manufacturing Co., Ltd. Electronic component having a coil conductor with photosensitive conductive paste
TW386279B (en) * 1998-08-07 2000-04-01 Winbond Electronics Corp Inductor structure with air gap and method of manufacturing thereof
US6103552A (en) 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6261865B1 (en) 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
JP2000195896A (ja) * 1998-12-25 2000-07-14 Nec Corp 半導体装置
US6181016B1 (en) * 1999-06-08 2001-01-30 Winbond Electronics Corp Bond-pad with a single anchoring structure
US6368410B1 (en) 1999-06-28 2002-04-09 General Electric Company Semiconductor processing article
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
US6277669B1 (en) 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
JP3684978B2 (ja) 2000-02-03 2005-08-17 セイコーエプソン株式会社 半導体装置およびその製造方法ならびに電子機器
US6498387B1 (en) 2000-02-15 2002-12-24 Wen-Ken Yang Wafer level package and the process of the same
US6586955B2 (en) 2000-03-13 2003-07-01 Tessera, Inc. Methods and structures for electronic probing arrays
JP3879816B2 (ja) 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
US6472247B1 (en) 2000-06-26 2002-10-29 Ricoh Company, Ltd. Solid-state imaging device and method of production of the same
US6693358B2 (en) 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
EP1207015A3 (en) 2000-11-17 2003-07-30 Keltech Engineering, Inc. Raised island abrasive, method of use and lapping apparatus
US20020098620A1 (en) 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
KR100352236B1 (ko) 2001-01-30 2002-09-12 삼성전자 주식회사 접지 금속층을 갖는 웨이퍼 레벨 패키지
US6867123B2 (en) 2001-02-08 2005-03-15 Renesas Technology Corp. Semiconductor integrated circuit device and its manufacturing method
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
JP2002270718A (ja) 2001-03-07 2002-09-20 Seiko Epson Corp 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
US6531384B1 (en) * 2001-09-14 2003-03-11 Motorola, Inc. Method of forming a bond pad and structure thereof
US20030059976A1 (en) 2001-09-24 2003-03-27 Nathan Richard J. Integrated package and methods for making same
US6727576B2 (en) 2001-10-31 2004-04-27 Infineon Technologies Ag Transfer wafer level packaging
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW517361B (en) 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
US6743660B2 (en) 2002-01-12 2004-06-01 Taiwan Semiconductor Manufacturing Co., Ltd Method of making a wafer level chip scale package
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
JP2003318178A (ja) 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US6903442B2 (en) 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US7030010B2 (en) 2002-08-29 2006-04-18 Micron Technology, Inc. Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures
US7329563B2 (en) 2002-09-03 2008-02-12 Industrial Technology Research Institute Method for fabrication of wafer level package incorporating dual compliant layers
US20040104454A1 (en) 2002-10-10 2004-06-03 Rohm Co., Ltd. Semiconductor device and method of producing the same
TW569395B (en) 2002-10-30 2004-01-01 Intelligent Sources Dev Corp Method of forming a stacked-gate cell structure and its NAND-type flash memory array
US20050012225A1 (en) 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
JP4072677B2 (ja) 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
SG137651A1 (en) 2003-03-14 2007-12-28 Micron Technology Inc Microelectronic devices and methods for packaging microelectronic devices
JP3680839B2 (ja) 2003-03-18 2005-08-10 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
EP1519410A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
JP4373695B2 (ja) 2003-04-16 2009-11-25 浜松ホトニクス株式会社 裏面照射型光検出装置の製造方法
DE10319538B4 (de) 2003-04-30 2008-01-17 Qimonda Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
EP1482553A3 (en) 2003-05-26 2007-03-28 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
WO2004114397A1 (en) 2003-06-20 2004-12-29 Koninklijke Philips Electronics N.V. Electronic device, assembly and methods of manufacturing an electronic device
JP4499386B2 (ja) 2003-07-29 2010-07-07 浜松ホトニクス株式会社 裏面入射型光検出素子の製造方法
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7180149B2 (en) 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
JP2005093486A (ja) 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
US7068139B2 (en) * 2003-09-30 2006-06-27 Agere Systems Inc. Inductor formed in an integrated circuit
TWI259564B (en) 2003-10-15 2006-08-01 Infineon Technologies Ag Wafer level packages for chips with sawn edge protection
TWI234244B (en) 2003-12-26 2005-06-11 Intelligent Sources Dev Corp Paired stack-gate flash cell structure and its contactless NAND-type flash memory arrays
US20050156330A1 (en) 2004-01-21 2005-07-21 Harris James M. Through-wafer contact to bonding pad
US7026175B2 (en) 2004-03-29 2006-04-11 Applied Materials, Inc. High throughput measurement of via defects in interconnects
US7368695B2 (en) 2004-05-03 2008-05-06 Tessera, Inc. Image sensor package and fabrication method
JP2005347442A (ja) * 2004-06-02 2005-12-15 Sanyo Electric Co Ltd 半導体装置
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
KR100605314B1 (ko) 2004-07-22 2006-07-28 삼성전자주식회사 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지의 제조 방법
US7750487B2 (en) 2004-08-11 2010-07-06 Intel Corporation Metal-metal bonding of compliant interconnect
US7378342B2 (en) 2004-08-27 2008-05-27 Micron Technology, Inc. Methods for forming vias varying lateral dimensions
US7129567B2 (en) 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
KR100604049B1 (ko) 2004-09-01 2006-07-24 동부일렉트로닉스 주식회사 반도체 칩 패키지 및 그 제조방법
JP4139803B2 (ja) 2004-09-28 2008-08-27 シャープ株式会社 半導体装置の製造方法
TWI273682B (en) 2004-10-08 2007-02-11 Epworks Co Ltd Method for manufacturing wafer level chip scale package using redistribution substrate
US7081408B2 (en) 2004-10-28 2006-07-25 Intel Corporation Method of creating a tapered via using a receding mask and resulting structure
JP4873517B2 (ja) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
KR20060087273A (ko) 2005-01-28 2006-08-02 삼성전기주식회사 반도체 패키지및 그 제조방법
US7675153B2 (en) 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US7538032B2 (en) 2005-06-23 2009-05-26 Teledyne Scientific & Imaging, Llc Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method
TWI244186B (en) 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI264807B (en) 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US20060264029A1 (en) 2005-05-23 2006-11-23 Intel Corporation Low inductance via structures
JP4694305B2 (ja) 2005-08-16 2011-06-08 ルネサスエレクトロニクス株式会社 半導体ウエハの製造方法
US20070049470A1 (en) 2005-08-29 2007-03-01 Johnson Health Tech Co., Ltd. Rapid circuit training machine with dual resistance
US20070052050A1 (en) 2005-09-07 2007-03-08 Bart Dierickx Backside thinned image sensor with integrated lens stack
JP2007157844A (ja) 2005-12-01 2007-06-21 Sharp Corp 半導体装置、および半導体装置の製造方法
US7456479B2 (en) * 2005-12-15 2008-11-25 United Microelectronics Corp. Method for fabricating a probing pad of an integrated circuit chip
US20080002460A1 (en) 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
KR100837269B1 (ko) 2006-05-22 2008-06-11 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조 방법
KR100764055B1 (ko) * 2006-09-07 2007-10-08 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 칩 스케일 패키지의 제조방법
JP2008091632A (ja) 2006-10-02 2008-04-17 Manabu Bonshihara 半導体装置の外部回路接続部の構造及びその形成方法
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US7719121B2 (en) 2006-10-17 2010-05-18 Tessera, Inc. Microelectronic packages and methods therefor
US7807508B2 (en) 2006-10-31 2010-10-05 Tessera Technologies Hungary Kft. Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US20080136038A1 (en) 2006-12-06 2008-06-12 Sergey Savastiouk Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate
JP2008147601A (ja) * 2006-12-13 2008-06-26 Yoshihiro Shimada フリップチップ接合方法及び半導体装置の製造方法
FR2911006A1 (fr) * 2007-01-03 2008-07-04 St Microelectronics Sa Puce de circuit electronique integre comprenant une inductance
JP2008177249A (ja) 2007-01-16 2008-07-31 Sharp Corp 半導体集積回路のボンディングパッド、その製造方法、半導体集積回路、並びに電子機器
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
JP2008258258A (ja) 2007-04-02 2008-10-23 Sanyo Electric Co Ltd 半導体装置
US20080284041A1 (en) 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
JP4937842B2 (ja) 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7767497B2 (en) 2007-07-12 2010-08-03 Tessera, Inc. Microelectronic package element and method of fabricating thereof
KR101588723B1 (ko) 2007-07-31 2016-01-26 인벤사스 코포레이션 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
KR101387701B1 (ko) 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
US7902069B2 (en) 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
KR100885924B1 (ko) 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
JP2009088201A (ja) 2007-09-28 2009-04-23 Nec Electronics Corp 半導体装置
US7446036B1 (en) 2007-12-18 2008-11-04 International Business Machines Corporation Gap free anchored conductor and dielectric structure and method for fabrication thereof
US20090212381A1 (en) 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US7842548B2 (en) * 2008-04-22 2010-11-30 Taiwan Semconductor Manufacturing Co., Ltd. Fixture for P-through silicon via assembly
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
JP5183340B2 (ja) 2008-07-23 2013-04-17 日本電波工業株式会社 表面実装型の発振器およびこの発振器を搭載した電子機器
US8932906B2 (en) * 2008-08-19 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via bonding structure
US7939926B2 (en) 2008-12-12 2011-05-10 Qualcomm Incorporated Via first plus via last technique for IC interconnects
TWI366890B (en) 2008-12-31 2012-06-21 Ind Tech Res Inst Method of manufacturing through-silicon-via and through-silicon-via structure
KR20100087566A (ko) 2009-01-28 2010-08-05 삼성전자주식회사 반도체 소자 패키지의 형성방법
US8697569B2 (en) 2010-07-23 2014-04-15 Tessera, Inc. Non-lithographic formation of three-dimensional conductive elements

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI736093B (zh) * 2019-12-31 2021-08-11 財團法人工業技術研究院 封裝結構
US11239146B2 (en) 2019-12-31 2022-02-01 Industrial Technology Research Institute Package structure

Also Published As

Publication number Publication date
US20120306092A1 (en) 2012-12-06
WO2012067992A2 (en) 2012-05-24
US8772908B2 (en) 2014-07-08
KR101059490B1 (ko) 2011-08-25
WO2012067992A3 (en) 2012-12-20
US20120119367A1 (en) 2012-05-17
CN103299419B (zh) 2016-05-18
TWI401781B (zh) 2013-07-11
CN103299419A (zh) 2013-09-11
TWI482255B (zh) 2015-04-21
TW201218346A (en) 2012-05-01
US8432045B2 (en) 2013-04-30
JP2014503992A (ja) 2014-02-13

Similar Documents

Publication Publication Date Title
JP6431967B2 (ja) 積層可能なモールディングされたマイクロ電子パッケージ
US9355901B2 (en) Non-lithographic formation of three-dimensional conductive elements
TWI482255B (zh) 藉由嵌入跡線界定之導電墊
EP1267402A2 (en) Semiconductor device and method of production of same
TWI497687B (zh) 半導體裝置及其製造方法
WO2012011932A1 (en) Methods of forming semiconductor elements using micro-abrasive particle stream
KR20100065151A (ko) 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
KR20070120449A (ko) 배선 기판, 그 제조 방법 및 반도체 장치
US20010028105A1 (en) Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
JP6595840B2 (ja) 半導体装置およびその製造方法
CN110890320A (zh) 半导体封装件及其制造方法
JP2007115774A (ja) 半導体装置の製造方法
JP7201296B2 (ja) 半導体装置およびその製造方法
JP7025948B2 (ja) 半導体装置および半導体装置の製造方法
TWI591780B (zh) 使用微影圖案化聚合物基板之無載體矽中介層
US10651374B2 (en) Semiconductor device, and method for manufacturing the same
JP2007123578A (ja) 半導体装置及びその製造方法
JP6120964B2 (ja) 半導体装置およびその製造方法
JPS63186457A (ja) 半導体装置及びその製造方法
JP3639265B2 (ja) 半導体装置及びその製造方法
JP7252386B2 (ja) 半導体装置および半導体装置の製造方法
JP2004165376A (ja) 電子回路装置、半導体装置および実装基板
JP2008112838A (ja) 配線基板およびその製造方法ならびに半導体装置およびその製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees