CN108257945B - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN108257945B CN108257945B CN201711461536.3A CN201711461536A CN108257945B CN 108257945 B CN108257945 B CN 108257945B CN 201711461536 A CN201711461536 A CN 201711461536A CN 108257945 B CN108257945 B CN 108257945B
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- electrode
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- terminal
- conductive path
- semiconductor device
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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Abstract
一种改进了可靠性的半导体器件。该半导体器件包括:布线衬底,具有第一表面和与第一表面相对的第二表面;芯片电容器,置于布线衬底中,具有第一电极和第二电极;第一端子和第二端子,设置在第一表面上;以及第三端子,设置在第二表面上。该半导体器件还包括:第一传导路径,用于耦合第一端子和第三端子;第二传导路径,用于耦合第一端子和第一电极;第三传导路径,用于耦合第三端子和第一电极;以及第四传导路径,用于耦合第二端子和第一电极。
Description
相关申请的交叉参考
2016年12月28日提交的日本专利申请第2016-254827号的包括说明书、附图和摘要的公开结合于此作为参考。
技术领域
本发明涉及一种半导体器件,其中,半导体芯片利用内置芯片电容器(condenser)例如安装在布线衬底上方。
背景技术
日本未审查专利申请公开第2015-18851号描述了一种半导体器件,其中,半导体芯片利用内置电子部件安装在衬底上方,其中芯片电容器是内置的。
发明内容
在日本未审查专利申请公开第2015-18851号中,图8示出了芯片电容器40内置于核心布线衬底2的开口2a中。如图8所示,芯片电容器40的一个耦合端子42耦合至衬底1的上表面侧上的第三布线层24,内置电子部件和第三布线层24位于衬底的下表面侧上。具体地,上表面侧上的第三布线层24通过一个耦合端子42(称为“传导路径1”)耦合至下表面侧上的第三布线层24。此外,上表面侧上的第三布线层24通过设置在核心布线衬底2中的过孔镀层20a(称为“传导路径2”)耦合至下表面侧上的第三布线层24。简而言之,上表面侧上的第三布线层24和下表面侧上的第三布线层24通过传导路径1和2并联耦合。
从本发明的发明人对上述结构的研究中发现,如果在传导路径1中发生耦合故障,则难以检测到故障并且不能够保证芯片电容器40的耦合可靠性。具体地,即使进行检查上表面侧上的第三布线层24与下表面侧上的第三布线层24之间的连续测试,也会由于传导路径2的存在而不能检测到传导路径1中的耦合故障。更具体地,如果上表面侧上的第三布线层24与耦合端子42之间以及下表面侧上的第三布线层24与耦合端子42之间均断开,芯片电容器40不能工作,从而引起具有利用内置电子部件安装在衬底1上方的半导体芯片60的半导体器件的可靠性的下降。
用于检测芯片电容器40中的耦合故障的一种方法是测量上表面侧上的第三布线层24与下表面侧上的第三布线层24之间的电容值。然而,在去耦电容器的情况下,许多(例如,10个)芯片电容器(例如,一个具有1μF的电容值)并联耦合在电源电压布线和参考电压布线之间,并且电容值在对应的芯片电容器之间改变(例如,±0.2μF)。由于许多芯片电容器的总电容值(10±0.2μF)的变化范围(±0.2μF)大于每个芯片电容器的电容值(1μF),所以难以检测例如在一个芯片电容器中的耦合故障。
因此,需要其中半导体芯片利用内置芯片电容器(上面提到的芯片电容器)安装在布线衬底上方的半导体器件的可靠性的改进。
本发明的上述和其他目的和新颖特征将从以下本说明书和附图的详细描述中变得更加明显。
根据本发明的一个方面,提供了一种半导体器件,包括:布线衬底,具有第一表面和与第一表面相对的第二表面;半导体芯片,具有第一芯片电极和第二芯片电极,并且安装在布线衬底上方;芯片电容器,内置于布线衬底中,具有第一电极和第二电极;第一端子和第二端子,设置在第一表面上;以及第三端子,设置在第二表面上。该半导体器件还包括:第一传导路径,用于耦合第一端子和第三端子;第二传导路径,用于耦合第一端子和第一电极;第三传导路径,用于耦合第三端子和第一电极;以及第四传导路径,用于耦合第二端子和第一电极。
根据本发明,可以改进半导体器件的可靠性。
附图说明
图1示出了根据本发明一个实施例的半导体器件的电路配置的示例;
图2是根据该实施例的半导体器件的顶视图;
图3是图2所示半导体器件的底视图;
图4是图2所示半导体器件的上表面的透视平面图;
图5是沿着图4中的线A-A截取的截面图;
图6是示出芯片电容器中的一个的平面图;
图7是沿着图6中的线B-B截取的截面图;
图8是示出用于制造根据该实施例的半导体器件的处理的处理流程图;
图9是在作为用于制造根据该实施例的半导体器件的处理中的过程的布线衬底的截面图;
图10是图9所示布线衬底的布线层的布局图(平面图);
图11是图9所示布线衬底的布线层的布局图(平面图);
图12是图9所示布线衬底的布线层的布局图(平面图);
图13是图9所示布线衬底的布线层的布局图(平面图);
图14是图9所示布线衬底的布线层的布局图(平面图);
图15是图9所示布线衬底的布线层的布局图(平面图);
图16是图9所示布线衬底的布线层的布局图(平面图);
图17是图9所示布线衬底的等效电路图;
图18是用于电容器耦合测试步骤中的良好/损坏判断的表格;
图19是示出用于制造根据该实施例的半导体器件的处理中的步骤的截面图;
图20是示出用于制造根据该实施例的半导体器件的处理中的步骤的截面图;
图21是示出用于制造根据该实施例的半导体器件的处理中的步骤的截面图;
图22是示出用于制造根据该实施例的布线衬底的处理的处理流程图;
图23是示出用于制造布线衬底的处理中的步骤的截面图;
图24是示出用于制造布线衬底的处理中的步骤的截面图;
图25是示出用于制造布线衬底的处理中的步骤的截面图;
图26是示出用于制造布线衬底的处理中的步骤的截面图;
图27是示出用于制造布线衬底的处理中的步骤的截面图;
图28是示出用于制造布线衬底的处理中的步骤的截面图;
图29是示出用于制造布线衬底的处理中的步骤的截面图;
图30是根据变形例1的半导体器件的截面图;
图31是根据变形例2的布线衬底的布线层的布局;以及
图32是根据变形例3的电子设备的截面图。
具体实施方式
说明书中的描述规则
本发明的优选实施例可以根据需要或者为了方便在不同的部分中分别进行描述,但是如此描述的实施例不是相互独立的,除非明确指定。不管它们被描述的顺序如何,一个实施例都是可以部分为另一个的详细形式,或者一个实施例可以整体或部分为另一个的变形。基本上,相同元件或事物的描述不进行重复。在优选实施例中,当针对一个元件指出具体数值时,该数值不是对于该元件是必须的,除非另有明确指定或者除非理论上限于该数值或者除非上下文明显要求该元件限于该数值。
在本发明实施例的材料或组成的描述中,表述“X包括A”或者“包括A的X”不排除除A之外的元素的材料或组成,除非另有明确指定或者除非上下文明显要求排除另一种元素。如果表述涉及到一种组成,这表示“X包含A作为主要组成”。明显地,例如,术语“硅件”不仅表示由纯硅制成的件,而且还表示由SiGe(硅锗)、合金或者另一种类型的多组成合金(包含硅作为主要组成)或基于硅的件(其包含另一种添加物)等制成的件。类似地,术语“金镀层”、“Cu层”或“镍镀层”不仅表示纯金、Cu或镍的件,而且还分别表示包含金、Cu和镍作为主要组成的件。
此外,即使当针对一个元件指出具体数值或量时,该元件的数值或量可以大于或小于具体的数值或量,除非另有明确指定或者除非理论上限于具体值或量或者除非上下文要求限于具体值或量。
在示出优选实施例的所有附图中,相同或相似的元件由相同或相似的参考符号或数字来表示,并且不再重复其基本描述。
关于附图,如果剖面线会使得附图看起来复杂或者容易将所关注的区域与间隙或空隙区分,则即使在截面图中也可以省略剖面线等。关于此,如果孔的轮廓根据解释明确,则即使对于平面封闭的孔也可以省略背景轮廓线。此外,即使附图没有示出截面,也可以添加剖面线或点图案以清楚表示所关注区域不是间隙或空隙或者清楚地示出区域的边界。
第一实施例
<半导体器件>
图1示出了根据该实施例的半导体器件的电路配置的示例。图2是图2所示半导体器件的顶视图。图3是图2所示半导体器件的底视图。图4是图2所示半导体器件的上表面的透视平面图。图5是沿着图4中的线A-A截取的截面图。图6是示出一个芯片电容器的平面图。图7是沿着图6中的线B-B截取的截面图。
如图1所示,根据该实施例的半导体器件PKG包括布线衬底2和安装在布线衬底2上方的半导体芯片1。
半导体芯片1包括多个供应有电源电压(例如,Vdd=3V)的端子Vd1、供应有参考电压(例如,Vss=0V)的端子Vs1以及用于信号的端子SG1。半导体芯片1的端子Vd1、Vs1和SG1对应于图5所示的焊盘电极PD。
如图5所示,布线衬底2包括主面2a和背面2b以及设置在主面2a上的端子(内端子)Vd21、Vs21、Tpd、Tps和SG21。此外,在背面2b上设置端子(外端子)Vd22、Vs22和SG22。端子Vd21、Vs21、Tpd、Tps和SG21对应于从绝缘膜(阻焊层)SR1露出的区域中的布线1W,并且端子Vd22、Vs22和SG22对应于在从绝缘膜(阻焊层)SR2露出的区域中的布线6W。仅在图1中示出端子SG21和SG22。
如图1所示,端子Vd21、Vs21、Tpd、Tps和SG21分别耦合至对应的端子Vd1、Vs1、Vd1、Vs1和SG1。如图5所示,端子Vd21、Vs21、Tpd和Tps通过凸块电极BP耦合至对应的端子Vd1、Vs1、Vd1和Vs1。此外,如图1所示,端子Vd22、Vs22和SG22分别耦合至端子Vd21、Vs21和SG21。耦合端子Vd22和Vd1的路径可以称为电源布线,并且耦合端子Vs22和Vs1的路径可以称为接地布线。
芯片电容器3包括电极31和32。电极31耦合至端子Vd21和Vd22,并且电极32耦合至端子Vs21和Vs22。简而言之,芯片电容器3是去耦电容器(或者用于电源的旁路电容器,简称为“passcon”),其防止电源电压中的波动或噪声。此外,电极31耦合至端子Tpd,并且电极32耦合至端子Tps。尽管图1仅示出了一个芯片电容器3,但实际上在布线衬底2中内置有具有图1所示电路耦合模式的多个芯片电容器(参见图4)。
如图2所示,在平面图中,在矩形布线衬底的主面2a的中心放置热辐射板(散热器、构件)4。如图20所示,半导体芯片1通过粘合层43耦合至热辐射板4,这将在稍后进行解释。热辐射板4具有将由半导体芯片1生成的热量扩散到半导体器件PKG的外部的功能。
如图3所示,多个焊球(焊料件、外部端子、电极、外部电极)SB以矩阵图案(阵列图案)布置在布线衬底2的背面2b上。例如,如果半导体器件PKG安装在安装板(母板、中继板)上方,则焊球SB是耦合形成在安装板(母板、中继板)上的端子以及半导体器件PKG的端子Vd22、Vs22和SG22的导电件。
如图4所示,在布线衬底2中内置多个芯片电容器3。在平面图中,芯片电容器3被定位在与半导体芯片1重叠的区域中,即在半导体芯片1下方。为了减小耦合至芯片电容器3的电源布线的阻抗,期望将芯片电容器3放置在与半导体芯片1重叠的区域中,并缩短电源布线;然而,代替地,芯片电容器3可位于不与半导体芯片1重叠的区域中。
如图4所示,在半导体芯片1周围设置底部填充树脂层(绝缘层、绝缘树脂)12。底部填充树脂层12接触半导体芯片1,并且连续地环绕半导体芯片1。如图5所示,通过底部填充树脂层12来填充半导体芯片1与布线衬底2的主面2a之间的空间。底部填充树脂层12接触并环绕凸块电极BP。相邻凸块电极BP之间的底部填充树脂层12接触相邻的凸块电极BP,并且还接触布线衬底2的主面2a和半导体芯片1的主面1a上的绝缘层SR1。
如图5所示,布线衬底2包括绝缘层(核心材料、核心绝缘层)2C、绝缘层IL12、IL23、IL45和IL56、绝缘膜SR1和SR2以及布线1W、2W、3W、4W、5W和6W。绝缘层2C具有隐埋芯片电容器3的开口(过孔)CBT以及过孔21。贯通孔布线2TW形成在过孔21中,并且贯通孔布线2TW耦合形成在绝缘层2C的上表面(半导体芯片1侧)上的布线3W和形成在下表面(焊球SB侧)上的布线4W。形成在绝缘层2C的上表面上的多条布线3W统称为布线层WL3。形成在绝缘层2C的下表面上的多条布线4W被统称为布线层WL4。类似地,多条布线1W、2W、5W和6W被分别称为布线层WL1、WL2、WL5和WL6。布线1W形成在绝缘层IL12和SR1之间;布线2W形成在绝缘层IL12和IL23之间;布线3W形成在绝缘层IL23和2C之间;布线4W形成在绝缘层2C和IL45之间;布线5W形成在绝缘层IL45和IL56之间;以及布线6W形成在绝缘层IL56和SR2之间。
这里,绝缘层2C由作为树脂浸渍玻璃纤维的预浸材料制成。布线层WL1、WL2、WL5和WL6是通过累积(build-up)法制成的微布线。绝缘层IL12、IL23、IL45和IL56例如由包含填充剂(诸如二氧化硅(SiO2))的环氧树脂或聚酰亚胺树脂制成。布线层WL1、WL2、WL3、WL4、WL5和WL6均是基于铜(Cu)的导电膜。
芯片电容器3在其两端具有电极31和32,并且隐埋在绝缘层2C中制成的开口CBT中。
绝缘层2C、布线层WL3以及芯片电容器3的上电极31a和32a的上表面被绝缘层IL23覆盖,并且多个过孔电极V23被隐埋在绝缘层IL23中。过孔电极V23将形成在绝缘层IL23上方的布线2W电耦合至布线2W或者上电极31a或32a。布线层WL2和绝缘层IL23被绝缘层IL12覆盖,并且多个过孔电极V12被隐埋在绝缘层IL12中。过孔电极V12将形成在绝缘层IL12上方的布线1W电耦合至布线2W。布线1W和绝缘层IL12被绝缘层SR1覆盖,并且绝缘层SR1具有多个开口H1。布线1W被开口H1露出的部分是端子Vd21、Tpd、Tps和Vs21。端子Vd21、Tpd、Tps和Vs21通过凸块电极BP耦合至形成在半导体芯片1的主面1a上的焊盘电极PD。
绝缘层2C、布线层WL4以及芯片电容器3的下电极31b和32b的下表面被绝缘层IL45覆盖,并且多个过孔电极V45被隐埋在绝缘层IL45中。过孔电极V45将形成在绝缘层IL45下方的布线5W电耦合至布线4W或者下电极31b或32b。布线层WL5和绝缘层IL45被绝缘层IL56覆盖,并且多个过孔电极V56被隐埋在绝缘层IL56中。过孔电极V56将形成在绝缘层IL56下方的布线6W电耦合至布线5W。布线6W和绝缘层IL56被绝缘层SR2覆盖,并且绝缘层SR2具有多个开口H2。布线6W被开口H2露出的部分是端子Vd22和Vs22,并且焊球SB通过导电层22耦合至端子Vd22和Vs22。在一些情况下,布线层WL4、WL5和WL6、绝缘层IL45、IL56和SR2以及焊球SB可以垂直相反的方式或者上下颠倒的方式来描述,其中,图5中的向下方向被认为是向上方向。在这种情况下,例如,布线层WL5可以被描述为形成在绝缘层IL45上方。此外,在图5(以及稍后将提到的图30)中,导电层22例如是合金层,其包含形成在布线层WL6上的镍(Ni)膜、布线层WL6的铜(Cu)和焊球的焊料。代替地,焊球SB可以直接安装在布线层WL6上,并且如果是这种情况的话,导电层22是铜(Cu)和形成在界面中的焊料的合金层。图9和图29(稍后进行描述)示出了形成焊球SB之前的状态,所以在这些附图中,导电层22在形成上述合金层之前是镍(Ni)膜。
这里,电极31和32、布线层WL1、WL2、WL3、WL4、WL5和WL6、贯通孔布线2TW、插塞电极V12、V23、V45和V56、凸块电极BP、焊盘电极PD、导电层22以及焊球SB是导电件。另一方面,绝缘层2C、绝缘层IL12、Il23、IL45和IL56、绝缘层SR1和SR12以及底部填充树脂层12是绝缘件。
如图5所示,芯片电容器3的一个电极31耦合至端子Vd21和Vd22,并且端子Vd21通过贯通孔布线2TW耦合至端子Vd22。如稍后描述的图17所示,端子Vd21(A)和端子Vd22(B)通过包括传导路径Ps1、贯通孔布线2TW和传导路径Ps2的传导路径1以及包括传导路径Ps3、电极31和传导路径Ps4的传导路径2耦合。在该实施例中,由于提供了通过传导路径Ps5电耦合至电极31的端子Tpd,所以可以确认传导路径Ps3或Ps4与传导路径Ps5之间的电耦合,使得可以改进半导体器件PKG的可靠性。稍后将描述测试方法。
对于芯片电容器3的另一电极32,由于提供了端子Tps,所以可以以与上述相同的方式在芯片电容器3上进行耦合测试。
此外,耦合至芯片电容器3的一个电极31的端子Tpd以及耦合至另一电极32的端子Tps被定位为彼此相邻并且通过两个相邻的凸块电极BP耦合至半导体芯片1的两个相邻的焊盘电极PD(即,端子Vd1和Vs1),使得减小了电源布线的阻抗,并且降低了电源电压的波动和噪声。这里,“两个相邻的”端子、凸块电极或焊盘电极表示在它们之间没有其他端子、凸块电极或焊盘电极。
此外,由于检测芯片电容器3中的断开的端子Tpd和Tps定位在布线衬底2的主面2a侧上(即,在安装半导体芯片1的表面上),所以布线衬底2的尺寸不需要加大。这是因为焊球SB的直径(宽度)大于凸块电极BP的直径(宽度),并且在布线衬底2的背面上具有的空位小于其主面上的空位。
此外,由于端子Tpd和Tps通过凸块电极BP耦合至半导体芯片1的端子Vd1和Vs1,所以可以防止底部填充树脂层12中空隙的生成。如果凸块电极BP没有设置在端子Tpd和Tps上方,则会存在定位端子Tpd和Tps但没有凸块电极BP的区域。换句话说,在定位端子Tpd和Tps的区域中,凸块电极BP之间的间距(间隔)大于凸块电极BP以规则间距布置的区域中的间距。如果存在凸块电极BP之间的间距不同的区域,则在底部填充树脂层12的填充期间会容易生成空隙。
如图6所示,芯片电容器3在平面图中是四边形(矩形)的。芯片电容器3具有两个长边(长侧面)3LS和两个短边(短侧面)3SS。在长边3LS延伸的方向上,芯片电容器3具有定位在相对端处的电极31和32。芯片电容器3还具有位于电极31和32之间的主体部3BD。例如,如图7所示,主体部3BD具有通过绝缘层(介电层)3IL堆叠的多个导电层3CL,并且每个导电层3CL都耦合至电极31或电极32中的一个。电极31具有形成在芯片电容器3的上表面3a上的上电极31a、形成在下表面3b上的下电极31b以及耦合上电极31a和下电极31b的侧电极31s。类似地,电极32具有形成在芯片电容器3的上表面3a上的上电极32a、形成在下表面3b上的下电极32b以及耦合上电极32a和下电极32b的侧电极32s。尽管芯片电容器3的上电极3a和下电极3b不同,但为了方便,如图5所示更接近半导体芯片1的表面(上表面3a)被称为主面3a。
<半导体器件制造方法>
图8是示出用于制造根据该实施例的半导体器件的处理的处理流程图。图9是作为用于制造根据该实施例的半导体器件的处理中的过程的布线衬底的截面图。图10至图16是图9所示布线衬底的布线层的布局图(平面图)。图17是图9所示布线衬底的等效电路图。图18是用于电容器耦合测试步骤处的良好/损坏判断的表格。图19至图21是示出用于制造根据该实施例的半导体器件的处理中的各个步骤的截面图。
首先,执行图8所示“提供具有内置电容器的布线衬底”的步骤(步骤S1)。具体地,如图9所示提供包含芯片电容器3的布线衬底2。布线衬底2与上面参照图5所述相同,除了还没有形成图5所示的半导体芯片1、凸块电极BP和焊球SB。然而,导电层23形成在端子Vd21、Vs21、Tpd和Tps上方。与焊球SB的材料(稍后将进行描述)相同种类的焊料材料可被用于导电层23。
如图9所示,端子Tpd(图中的C)和Vd21(图中的A)耦合至芯片电容器3的上电极31a,并且端子Vd22(图中的B)耦合至下电极31b。端子A和B通过贯通孔布线2TW相互耦合。具体地,图17所示的传导路径Ps1包括端子A、布线1W、过孔电极V12、布线2W、过孔电极V23、布线3W和贯通孔布线2TW;传导路径Ps2包括贯通孔布线2TW、布线4W、过孔电极V45、布线5W、过孔电极V56、布线6W和端子B;传导路径Ps3包括端子A、布线1W、过孔电极V12、布线2W、过孔电极V23和电极31;以及传导路径Ps4包括端子B、布线W6、过孔电极V56、布线W5、过孔电极V45和电极31。传导路径1包括端子A、传导路径Ps1、贯通孔布线2TW、传导路径Ps2和端子B。传导路径2包括端子A、传导路径Ps3、电极31、传导路径Ps4和端子B。电极31耦合至端子C,组成传导路径Ps5。传导路径Ps5包括端子C、布线1W、过孔电极V12、布线2W、过孔电极V23和电极31。
芯片电容器3的另一电极32具有与上面相同的结构,这里省略其描述。
接下来,执行图8所示的“电容器耦合测试”步骤(步骤S2)。为了检查端子A或B与芯片电容器3的电极31之间的耦合,在端子A或B与端子C之间进行连续测试。具体地,测试传导路径Ps3和Ps5之间或者传导路径Ps4和Ps5之间的连续性。端子A和B都不需要耦合至芯片电容器3的电极31,并且当这些端子中的任一个耦合至它时,芯片电容器3工作。
在图18的表格中,标记X表示传导路径Ps3、Ps4或Ps5具有耦合故障(断开),并且标记o表示其不具有耦合故障。
如图18所示,如果判定是“通过”(即,良好),则表示传导路径Ps3和Ps5或者传导路径Ps4和Ps5是导通的(情况1、3和5)。如果判断是“失败”(即,缺陷),则表示传导路径Ps3和Ps5或传导路径Ps4和Ps5不传导(情况2、4、6、7和8)。如果传导路径Ps5具有耦合故障(断开)(情况2、4、7和8),则判断为“失败”(缺陷),即使传导路径Ps3或Ps4是导通的。
还对芯片电容器3的电极32进行与上面相同的耦合测试。可以同时对电极31和32进行耦合测试。此外,可以同时对另一芯片电容器3进行耦合测试。由于可以仅在布线衬底2的主面上使探针与端子A和C接触进行耦合测试,所以期望测试端子A和C之间的连续性。
接下来,执行图8所示“安装半导体芯片”的步骤(步骤S3)。
如图19所示,半导体芯片1被安装在布线衬底2上方,在上面的耦合测试中判断布线衬底2是良好的,并且半导体芯片1和布线衬底2通过多个凸块电极BP耦合。例如,无铅焊料可用于凸块电极BP。此外,可以在凸块电极BP和焊盘电极PD之间设置底层金属(包括诸如钛(Ti)、铜(Cu)和镍(Ni)的金属的层压膜)(参见图5)。
接下来,执行图8所示的“密封”步骤(步骤S4)。
首先,如图20所示,以填充布线衬底2和半导体芯片1之间的空间的方式来隐埋底部填充树脂层12。如图5所示,在上述空间中,底部填充树脂层12连续地从布线衬底2的主面2a延伸到半导体芯片1的主面1a,并且接触凸块电极BP的侧壁并完全地覆盖侧壁。可以通过以这种方式利用底部填充树脂12覆盖凸块电极BP与端子Vd21、Vs21、Tpd和Tps之间的结以及凸块电极BP与焊盘电极PD之间的结来减小在半导体芯片1和布线衬底2之间的电耦合部处生成的应力。此外,可以减小在半导体芯片1的焊盘电极PD与凸块电极BP之间的结处生成的应力。例如,底部填充树脂层12是环氧树脂等的绝缘树脂膜。底部填充数值层12延伸到半导体芯片1的主面外,并且扩展到半导体芯片1的侧面。其部分地覆盖侧面。
如图20所示,在半导体芯片1周围固定用于支持热辐射板4的支持框(加强环)41。热辐射板4通过粘合层43和42粘附性地固定至半导体芯片1的背面1b和支持框41。可以通过在半导体芯片1周围固定金属支持框42来抑制布线衬底2的翘曲或变形,这在安装可靠性的改进角度来说是优选的。此外,由于热辐射板4粘附性地固定至环绕半导体芯片1的支持框41,所以可以增加热辐射板4的平面面积。不总是需要提供热辐射板4和支持框41。
接下来,执行图8所示“形成焊球”的步骤(步骤S5)。
如图21所示,多个焊球SB形成在布线衬底2的背面2b上。如图5所示,在绝缘层SR2中制成的开口H2露出的区域中,焊球SB通过导电层22耦合至布线6W。焊球SB是由含铅(Pb)Sn-Pb或无铅焊料(其基本不包含Pb并且是所谓的无铅焊料)制成的焊料件。无铅焊料的示例是仅包含锡(Sn)、锡-铋(Sn-Bi)、锡-铜-银(Sn-Cu-Ag)、锡-铜(Sn-Cu)等的焊料。
接下来,将参照图10至图16解释配置布线衬底2的布线层WL1至WL6的布局。图10至图16分别是布线层WL1至WL6的断续图,并且示出了芯片电容器3及其周围区域的布局。
首先,图10是布线层WL1的布局。在X方向上交替地布置沿Y方向延伸的用于电源电压1W(Vd21)的布线以及用于参考电压(Vs21)的布线1W。多个开口H1(标记o)被设置在布线1W(Vd21)和布线1W(Vs21)上方,并且如图5所示,凸块电极BP耦合至开口H1。由于用于电源电压1W(Vd21)的布线和用于参考电压1W(Vs21)的布线被交替且均匀地布置,所以电源电压和参考电压可以均匀地提供给半导体芯片1。多个开口H1在Y方向上以规则的间距P1布置在用于电源电压1W(Vd21)的每条布线上方。此外,多个开口H1在Y方向上以规则的间距P1布置在用于参考电压1W(Vs21)的每条布线上方。在X方向上的相同位置中定位用于电源电压1W(Vd21)的布线上方的开口H1以及用于参考电压1W(Vs21)的布线上方的开口H1。换句话说,在X方向上,用于参考电压1W(Vs21)的布线上方的开口H1被定位为与用于电源电压1W(Vd21)的布线上方的开口H1相邻。
备选地,在X方向上,布线1W(Vs21)上方的开口H1可以相对于布线1W(Vs21)上方的开口H1偏离半个间距(P1x 1/2)。
在图10的中心,定位用于端子Tpd的布线1W和用于端子Tps的布线,并且用于端子Tpd的布线1W和用于端子Tps的布线1W与用于电源电压1W(Vd21)的布线和用于参考电压1W(Vs21)的布线隔离。用于端子Tpd的布线1W和用于端子Tps的布线1W彼此相邻,并且在它们之间不存在布线。
图11示出了布线层WL2的布局。布线层WL2主要是用于电源电压的平面。在图11的中心中定位类似于狗骨头的两条布线2W,并且以环绕狗骨头状布线2W的方式来定位用于电源电压的布线2W。图10所示用于端子Tpd的布线1W和用于Tps的布线1W通过过孔电极V12耦合至狗骨头状布线2W。
图12示出了布线层WL3的布局。布线层WL3主要是用于参考电压的平面。在图12的中心中定位用于放置芯片电容器3的矩形开口CBT,并且在开口CBT周围定位布线3W。用于参考电压的布线3W具有环绕矩形开口CBT的三侧的形状,并且布线3W沿着这三侧的边缘3WE比开口CBT更加远离芯片电容器3。在开口CBT的另一侧,耦合至贯通孔布线2TW的用于电源电压的布线3W被定位为远离用于参考电压的布线3W。耦合至贯通孔布线2TW的用于电源电压的布线3W还被定位为远离开口CBT。简而言之,开口CBT被用于参考电压的布线3W以及耦合至贯通孔布线2W的用于电源电压的布线3W所环绕。这里,表述“环绕”暗示:如图12(或图13)所示,可以在用于电源电压的布线3W和用于参考电压的布线3W之间存在间隙(距离)。如图5所示,用于参考电压的布线3W以及耦合至贯通孔布线2TW的用于电源电压的布线3W朝向与芯片电容器3相对的方向从开口CBT缩回。简而言之,在用于参考电压的布线3W和耦合至贯通孔布线2TW的用于电源电压的布线3W的开口CBT侧上露出绝缘层2C的上表面,并且在该区域不存在布线3W。
芯片电容器3的上电极31a耦合至两个过孔电极V23:一个(右边的)过孔电极V23耦合至图11所示的狗骨头状布线2W,另一个(左边的)耦合至用于电源电压的布线2W。上电极32a耦合至两个过孔电极V23:一个(左边的)过孔电极V23耦合至图11所示狗骨头状的布线2W,另一个(右边的)耦合至用于参考电压的T状布线2W。耦合至上电极31a的两个过孔电极V23沿X方向(图6中的长边3LS延伸的方向)布置并且平行于图6所示的长边3LS。耦合至上电极32a的两个过孔电极V23以与上述相同的方式布置。
图13示出了布线层WL4的布局。布线层WL4基本是用于参考电压的平面。布线层WL4具有与布线层WL3相同的布局,并且这里省略其布局的描述。
图14示出了布线层WL5的布局,以及图15示出了布线层WL6的布局。如图15所示,布线层WL6包括用于端子Vd22的布线6W和用于端子Vs22的布线6W。图13所示芯片电容器3的下电极31b通过过孔电极V45以及图14所示的布线5W和过孔电极V56耦合至用于端子Vd22的布线6W。用于端子Vd22的布线6W具有两个开口H2,并且从这些开口H2露出的区域是与图5所示焊球SB耦合的端子Vd22。用于端子Vss22的布线6W具有两个开口H2,并且从这些开口H2露出的区域是与图5所示焊球SB耦合的端子Vs22。
图16示出了配置用于电源电压的平面的布线2W和配置用于参考电压的平面的布线3W。在图16中,这些布线重叠的区域用阴影示出。由于如图5所示在它们之间存在用于电源电压的布线2W和用于参考电压的布线3W与绝缘层IL23重叠的宽区域,所以可以减小电源布线的阻抗。
如上所述,在半导体器件制造方法中,通过进行电容器耦合测试来改进半导体器件的可靠性。此外,由于耦合内置芯片电容器3而没有断开,所以改进了半导体器件的性能。
<用于制造布线衬底的方法>
接下来,将描述用于制造具有内置芯片电容器的布线衬底的方法。图22是示出用于制造根据该实施例的布线衬底的处理的处理流程图。图23至图29是示出用于制造布线衬底的处理中的各个步骤的截面图。
首先,执行图22所示“提供基础材料”的步骤(步骤S11)。如图23所示,提供树脂浸渍玻璃纤维的绝缘层2C。绝缘层2C在其厚度方向上具有贯通孔21,并且在每个贯通孔21中形成贯通孔布线2TW。布线3W形成在绝缘层2C的上表面(图23中的上侧)上,并且布线4W形成在绝缘层2C的下表面(图23中的下侧)上。布线3W和4W耦合至贯通孔布线2TW。在该实施例的描述中,假设布线衬底2具有绝缘层2C作为核心材料。然而,布线衬底可以是所谓的无核衬底,其不具有绝缘层2C并且仅包括绝缘层IL2至IL56。
接下来,执行图22所示的“制造开口CBT”的步骤(步骤S12)。如图24所示,在绝缘层2C中制造开口CBT。
接下来,执行图22所示的“粘合支持件5”的步骤(步骤S13)。如图25所示,在支持件5上方粘合具有开口CBT的绝缘层2C。此时,以布线3W接触支持件5的方式,在支持件5上粘合绝缘层2C的上表面(图25中的下侧)。在该步骤中,使用粘合剂等用于粘合工件不是必要的,而是它们可以机械地相互固定。
接下来,执行图22所示“安装电容器3”的步骤(步骤S14)。如图26所示,芯片电容器3被安装在绝缘层2C的开口CBT中。以芯片电容器3的上电极31a和32a接触支持件5的方式来进行安装。此外,重要的是绝缘层2C以及布线3W和4W的总厚度T1应该大于包括上电极31a和下电极31b的芯片电容器3的厚度T2。当该关系(T1>T2)保持时,可以防止芯片电容器3的击穿。原因在于如果芯片电容器3从绝缘层2C突出,则当稍后描述的绝缘层IL45和IL23被粘合然后在压力下经受热处理时,压力被局部地施加于芯片电容器3。此外,重要的是,布线3W在高度上应该等于上电极31a和32a。这使得芯片电容器3接近布线2的主面2a,从而改进布线衬底2的主面2a的平坦度。
接下来,执行图22所示“形成绝缘层IL45”的步骤(步骤S15)和“剥离支持件5”的步骤(步骤S16)。如图27所示,形成绝缘层IL45以覆盖芯片电容器3、绝缘层2C和布线4W。例如,期望进行以下过程:开口CBT的内侧涂有膏状环氧树脂,然后蒸发溶剂以硬化树脂,环氧树脂膜被层压在布线4W上方,然后其在压力下被热硬化以形成绝缘层IL45;以及布线层WL5形成在其上方,并且从绝缘层2C剥离支持件5。这是因为布线层WL5必须平坦化以增加布线层WL5的图案精度。为此,重要的是用膏状环氧树脂涂覆开口CBT的内侧,然后蒸发溶剂以硬化树脂。
布线4W环绕芯片电容器3和开口CBT,由此用作坝(dam),来防止膏状环氧树脂水平地流出。
备选地,只有膜状环氧树脂可用于隐埋芯片电容器3并填充开口CBT。在这种情况下,通过在布线4W上方层压片状环氧树脂并在压力下执行热硬化,利用环氧树脂填充开口CBT,同时形成绝缘层IL45并且布线层WL5在从绝缘层2C剥离支持件5之前形成在其上方。
在仅使用膜状环氧树脂的情况下,通过从开口CBT周围流入开口CBT的膜状环氧树脂,开口CBT填充有树脂。因此,如果隐埋的芯片电容器3之间的间隔较小,则布线层WL5的平坦度会由于树脂流入开口CBT而在一定程度上劣化。因此,如果只有膜状环氧树脂被用于填充开口CBT,则隐埋芯片电容器3的密度将下降。一般地,隐埋芯片电容器3之间的间隔必须为约500μm以上。
尽管由此限制了被隐埋的芯片电容器3的密度,但是该过程消除了对用膏状环氧树脂涂覆开口CBT的内侧并蒸发溶剂以硬化树脂的步骤,从而降低了处理成本。
接下来,执行图22所示“形成绝缘层IL23”的步骤(步骤S17)。如图28所示,形成绝缘层IL23以涂覆芯片电容器3、绝缘层2C和布线3W。例如,通过层压膜状环氧树脂并在压力下执行热硬化来形成绝缘层IL23,并且布线层WL2形成在其上方。此时,树脂被额外地填充到图22所示步骤S15中没有充分填充树脂的区域中。在步骤S15中,在一些情况下,如图27所示在支持件5和芯片电容器3或绝缘层2C之间生成间隙,但是在步骤S17中,在与图27所示层压相对的侧面上层压树脂来填充这种间隙,从而改进了质量。
如果芯片电容器3和开口CBT上方的绝缘层IL23的厚度小于其上区域上方的厚度,则布线衬底2的主面2a将会不平坦,并且例如在检查步骤中会产生问题。具体地,形成在芯片电容器3上方的布线1W和形成在另一区域上方(即,在开口CBT周围的绝缘层2C上方)的布线1W的高度将会不同,使得难以使用于检查的探针同时接触布线1W(端子Vd21、Vs21、Tpd和Tps等)。此外,会产生在通过光刻技术和蚀刻技术图案化布线层WL1和WL2的过程中不能实现高处理精度的问题。接下来,在绝缘层IL45上方形成布线层WL5。
绝缘层IL12、IL23、IL45和IL56还可以由作为树脂浸渍玻璃纤维的预制材料制成。如果包含芯片电容器3的绝缘层2C的上表面和下表面是由预制材料制成的绝缘层IL23和IL45,则例如防止了图5所示布线1W、2W、5W和6W的断开。具体地,由于绝缘层2C具有许多开口CBT以包含许多芯片电容器3,所以由于热波动而由布线衬底2的扩展或收缩生成的应力可以通过绝缘层2C的上表面和下表面上的作为树脂浸渍玻璃纤维的预制材料制成的绝缘层IL23和IL45而减小。
接下来,执行图22所示“形成布线层WL1、WL2、WL5和WL6”的步骤(步骤S18)和“露出端子”的步骤(步骤S19)。通过处理图28所示的布线层WL2和WL5,如图29所示形成布线2W和5W。尽管在图27和图28中未示出,但在形成布线层WL5和WL2之前,在绝缘层IL45和IL23中形成过孔电极V45和V23。此外,如图29所示,形成绝缘层IL12和IL56,并且形成过孔电极V12和V56以及布线层WL1和WL6。绝缘层IL12和IL56可由预制材料制成。
此外,形成绝缘层SR1和SR2以覆盖布线1W和6W并制造部分地露出布线1W和6W的开口H1和H2。开口H1和H2在平面图中是圆形的。如图29所示,开口H1的直径(宽度)W1小于开口H2的直径(宽度)W2(W1<W2)。然而,开口H1和H2不需要是圆形的。
此外,如图29所示,绝缘层2C以及布线3W和4W的总厚度T1大于包含上电极31a和下电极31b的芯片电容器3的厚度T2。例如,从布线4W的下表面开始,布线3W的上表面与上电极31a和32a的上表面的高度相同。因此,绝缘层2C以及布线3W和4W的总厚度T1与包括上电极31a和下电极31b的芯片电容器3的厚度T2之间的差值d等于下电极31b的下表面与布线4W的下表面相距的高度。这里,“上表面”表示图29中上侧的表面(即,更接近安装半导体芯片的侧面的表面),并且“下表面”表示下侧的表面(更接近耦合焊球的侧面的表面)。
变形例1
参考优选实施例具体解释了发明人做出的本发明。然而,本发明不限于此,并且明显地,在不背离本发明精神的情况下可以各种方式修改这些细节。
在上述实施例中,如图5所示,用于检查芯片电容器3的断开的端子Tpd和Tps被定位在布线衬底2的主面2a的一侧上(即,更接近安装半导体芯片1的一侧)。在变形例1中,端子Tpd1和Tps1被增加至布线衬底2的背面2b的一侧,以检查芯片电容器3中的断开。
图30是根据变形例1的半导体器件的截面图。如图30所示,两个过孔电极V45耦合至芯片电容器3的下电极31b;并且一个过孔电极V45耦合至端子Vd22且另一个过孔电极V45耦合至端子Tpd1。在之前参照图8解释的半导体器件制造处理中,在“形成焊球”的步骤(步骤S5)之后,可以通过进行图30所示端子Vd22和Tpd1之间的连续性的测试来检查芯片电容器3与用于电源电压的布线的耦合。换句话说,如果确认端子Vd22和Tpd1之间的连续性,则表示电源布线耦合至上电极31b或上电极31a中的任一个。
以与上述相同的方式,端子Tps1也设置在芯片电容器3的另一电极32的下电极32b上。因此,可以确认芯片电容器3与用于接地电位的布线的耦合。
从绝缘层SR2中制造的开口H3中露出端子Tpd1和Tps1。每个开口H3都是圆形的,并且其直径(宽度)W3小于图29所示开口H2的直径(宽度)W2(W3<W2)。由于在开口H3中没有形成凸块电极,所以其直径(宽度)W3可以小于开口H1的直径(宽度)W1(W3<W1)。
变形例2
变形例2不同于上述实施例的图12所示的布局。图31示出了根据变形例2的布线衬底的布线层的布局。如图31所示,两个过孔电极V23耦合至芯片电容器3的上电极31a。两个过孔电极V23相对于X方向(芯片电容器3的长边3LS延伸的方向)倾斜布置。具体地,两个过孔电极V23沿着X方向(芯片电容器3的长边3LS延伸的方向)布置,并且一个过孔电极V23更接近一个长边侧3LS,且另一个过孔电极V23更接近另一个长边侧3LS。
由于两个过孔电极V23的倾斜布置,所以电极31在X方向上的宽度可以小于当两个过孔电极V23沿着X方向并排布置时的宽度。此外,可以增加过孔电极V23的直径。
变形例3
变形例3是根据上述第一实施例的芯片电容器1的示例,其安装在电子设备上方。图32是根据变形例3的电子设备的截面图。
如图32所示,电子设备EVD包括母板MB、通过焊球SB耦合至母板MB的布线衬底IP以及通过凸块电极BP耦合至布线衬底IP的半导体芯片1X和1Y。
在布线衬底IP中内置三个芯片电容器3X1、3X2和3X3。尽管图中未示出,但三个芯片电容器3X1、3X2和3X3以与第一实施例相同的方式耦合在用于电源电压的布线和用于参考电压的布线之间。芯片电容器3X1被定位在半导体芯片1X下方,并且芯片电容器3X3被定位在半导体芯片1Y下方。芯片电容器3X2被定位在不与半导体芯片1X和1Y重叠的区域中,例如半导体芯片1X和1Y之间的区域。
此外,母板MB还包含芯片电容器3Y,其耦合在母板MB的电源电压布线和参考电压布线之间。
以与上面参照图5所述的实施例相同的方式,检查芯片电容器的耦合的端子Tpd和Tps耦合至芯片电容器3X1、3X2、3X3和3Y。
以下描述上述实施例的一些特征。
注解1
一种半导体器件制造方法包括以下步骤:
(a)提供布线衬底,其具有:第一表面;第二表面,与第一表面相对;芯片电容器,置于第一表面和第二表面之间,具有第一电极和第二电极;第一端子和第二端子,设置在第一表面上;第三端子,设置在第二表面上;第一传导路径,用于耦合第一端子和第三端子;第二传导路径,用于耦合第一端子和第一电极;第三传导路径,用于耦合第三端子和第一电极;以及第四传导路径,用于耦合第二端子和第一电极;
(b)在第二端子和第一端子之间或者在第二端子和第三端子之间进行连续性的测试;以及
(c)在第一表面上方安装具有第一芯片电极和第二芯片电极的半导体芯片,并且形成用于耦合第一端子和第一芯片电极的第一凸块电极和用于耦合第二端子和第二芯片电极的第二凸块电极。
注解2
在注解1中描述的半导体器件制造方法还包括以下步骤:
(d)覆盖第一凸块电极和第二凸块电极的外围,并且填充第一表面和半导体芯片之间的绝缘层。
注解3
一种布线衬底制造方法包括以下步骤:
(a)提供第一绝缘层,具有:第一表面;第二表面,与第一表面相对;第一布线,形成在第一表面上;第二布线,形成在第二表面上;以及贯通孔,从第一表面穿透到第二表面;
(b)以支持件的主面接触第一布线的方式,在支持件上方放置第一绝缘层;
(c)提供芯片电容器,其具有:第三表面;第四表面,与第三表面相对;第一电极,形成在第三表面上;以及第二电极,形成在第四表面上;
(d)以第三表面上的第一电极接触支持件的主面的方式,将芯片电容器插入到贯通孔中;
(e)形成用于覆盖第一绝缘层的第二表面和芯片电容器的第四表面的第二绝缘层;
(f)去除支持件,并且形成用于覆盖第一绝缘层的第一表面和芯片电容器的第三表面的第三绝缘层;以及
(g)在第三绝缘层上方形成多条第三布线。
注解4
在注解3中描述的布线衬底制造方法,其中包括第一布线和第二布线的第一绝缘层的厚度大于包括第一电极和第二电极的芯片电容器的厚度。
注解5
在注解3中描述的布线衬底制造方法,其中,
在平面图中,贯通孔是具有四边的矩形;并且
第二布线具有沿着贯通孔的三侧环绕贯通孔的形状。
注解6
在注解5中描述的布线衬底制造方法,其中第一布线具有沿着贯通孔的三侧环绕贯通孔的形状。
注解7
在注解6中描述的布线衬底制造方法,其中在第一布线和贯通孔之间露出第一绝缘层的主面。
Claims (21)
1.一种半导体器件,包括:
布线衬底,具有第一表面和与所述第一表面相对的第二表面;
半导体芯片,具有第一芯片电极和第二芯片电极,并且被安装在所述布线衬底上方;
芯片电容器,置于所述布线衬底中,具有第一电极和第二电极;
第一端子和第二端子,设置在所述第一表面上;
第三端子,设置在所述第二表面上;
第一传导路径,用于耦合所述第一端子和所述第三端子;
第二传导路径,用于耦合所述第一端子和所述第一电极,并且包括耦合至所述第一电极的第一过孔电极;
第三传导路径,用于耦合所述第三端子和所述第一电极;以及
第四传导路径,用于耦合所述第二端子和所述第一电极,并且包括耦合至所述第一电极的第二过孔电极,
其中所述第四传导路径耦合至所述第一电极,与所述第一传导路径、所述第二传导路径和所述第三传导路径电独立,并且
其中在平面图中,所述芯片电容器具有矩形形状,所述矩形形状具有第一长边、第二长边、第一短边和第二短边,并且所述第一电极沿着所述第一短边形成。
2.根据权利要求1所述的半导体器件,
其中在平面图中,所述第一过孔电极和所述第二过孔电极被布置为平行于所述第一长边。
3.根据权利要求1所述的半导体器件,
其中在平面图中,所述第一过孔电极和所述第二过孔电极沿着所述第一长边布置,并且所述第一过孔电极比所述第二过孔电极更接近所述第一长边,并且所述第二过孔电极比所述第一过孔电极更接近所述第二长边。
4.根据权利要求1所述的半导体器件,还包括:
第一凸块电极,用于耦合所述第一端子和所述第一芯片电极;以及
第二凸块电极,用于耦合所述第二端子和所述第二芯片电极。
5.根据权利要求4所述的半导体器件,还包括:
第一绝缘层,覆盖所述第一凸块电极和所述第二凸块电极的外围,并且填充在所述布线衬底的所述第一表面和所述半导体芯片之间。
6.根据权利要求1所述的半导体器件,还包括:
第四端子,设置在所述第二表面上;以及
第五传导路径,用于耦合所述第四端子和所述第一电极。
7.根据权利要求6所述的半导体器件,还包括:
第二绝缘层,覆盖所述第二表面,并且具有露出所述第三端子的第一开口和露出所述第四端子的第二开口,
其中所述第二开口的直径小于所述第一开口的直径。
8.根据权利要求1所述的半导体器件,还包括:
第三绝缘层,覆盖所述第一表面,并且具有露出所述第一端子的第三开口和露出所述第二端子的第四开口,
其中所述第三开口的直径等于所述第四开口的直径。
9.根据权利要求1所述的半导体器件,
所述布线衬底还包括:
第四绝缘层,具有第三表面、与所述第三表面相对的第四表面、从所述第三表面穿透到所述第四表面的第一贯通孔和第二贯通孔;
第一布线,覆盖所述第二贯通孔并且形成在所述第三表面上;
第二布线,覆盖所述第二贯通孔并且形成在所述第四表面上;以及
贯通孔布线,形成在所述第二贯通孔中并且耦合至所述第一布线和所述第二布线,
其中所述芯片电容器具有上表面和与所述上表面相对的下表面;其中所述第一电极包括形成在所述上表面上的上电极以及形成在所述下表面上的下电极,并且
其中在截面图中,包括所述上电极和所述下电极的所述芯片电容器的厚度小于包括所述第一布线和所述第二布线的所述第四绝缘层的厚度。
10.根据权利要求9所述的半导体器件,还包括:
第五绝缘层,覆盖所述第一布线和所述上电极;
其中所述第四绝缘层和所述第五绝缘层是包含玻璃纤维的树脂层。
11.根据权利要求10所述的半导体器件,还包括:
第三布线,形成在所述第五绝缘层上方;以及
第六绝缘层,覆盖所述第三布线,
其中所述第六绝缘层由环氧树脂制成。
12.一种半导体器件,包括:
布线衬底,具有第一表面和与所述第一表面相对的第二表面;
半导体芯片,具有第一芯片电极和第二芯片电极,并且被安装在所述布线衬底上方;
芯片电容器,置于所述布线衬底中,具有第一电极和第二电极;
第一端子、第二端子、第三端子和第四端子,设置在所述第一表面上;
第五端子和第六端子,设置在所述第二表面上;
第一传导路径,用于耦合所述第一端子和所述第五端子;
第二传导路径,用于耦合所述第一端子和所述第一电极;
第三传导路径,用于耦合所述第五端子和所述第一电极;以及
第四传导路径,用于耦合所述第二端子和所述第一电极;
第五传导路径,用于耦合所述第三端子和所述第六端子;
第六传导路径,用于耦合所述第三端子和所述第二电极;
第七传导路径,用于耦合所述第六端子和所述第二电极;以及
第八传导路径,用于耦合所述第四端子和所述第二电极,
其中所述第四传导路径耦合至所述第一电极,与所述第一传导路径、所述第二传导路径和所述第三传导路径独立,并且
其中所述第八传导路径耦合至所述第二电极,与所述第五传导路径、所述第六传导路径和所述第七传导路径独立。
13.根据权利要求12所述的半导体器件,还包括:
第一凸块电极,用于耦合所述第二端子和所述第一芯片电极;以及
第二凸块电极,用于耦合所述第四端子和所述第二芯片电极。
14.根据权利要求13所述的半导体器件,其中所述第一凸块电极和所述第二凸块电极被定位为彼此相邻,其间没有另一凸块电极。
15.根据权利要求14所述的半导体器件,还包括:
第一焊球电极,耦合至所述第五端子;以及
第二焊球电极,耦合至所述第六端子。
16.根据权利要求12所述的半导体器件,还包括:
第一导电板,耦合至所述第四传导路径;
第二导电板,耦合至所述第八传导路径;以及
绝缘膜,定位在所述第一导电板和所述第二导电板之间,
其中在平面图中,所述第一导电板和所述第二导电板具有相互重叠的区域。
17.一种半导体器件,包括:
布线衬底,具有形成有多个第一外部电极的第一正面以及与所述第一正面相对的、形成有多个第二外部电极的第一背面;以及
半导体芯片,具有主面,并且以所述布线衬底的所述第一正面面对所述主面的方式安装在所述第一正面上方,
所述布线衬底包括:
核心衬底,在所述第一正面和所述第一背面之间具有面对所述第一正面的第二正面以及与所述第二正面相对且面对所述第一背面的第二背面;
第一电容器,在所述核心衬底的所述第二正面和所述第二背面之间具有面对所述第一正面的第一表面以及与所述第一表面相对且面对所述第一背面的第二表面;以及
多条布线,
其中所述第一外部电极包括第一电极和第二电极,
其中所述第二外部电极包括第三电极,
其中所述第一电容器具有多个电极,
其中所述布线包括第一布线、第二布线、第三布线和第四布线,其中所述第一布线的一端电耦合至所述第一正面上的所述第一电极,
其中所述第一布线的另一端电耦合至所述第一背面上的所述第三电极,
其中所述第二布线的一端电耦合至所述第一正面上的所述第一电极,
其中所述第二布线的另一端电耦合至所述第一电容器的电极中包括的第四电极,
其中所述第三布线的一端电耦合至所述第一正面上的所述第二电极,
其中所述第三布线的另一端电耦合至所述第一电容器的所述第四电极,
其中所述第四布线的一端电耦合至所述第一背面上的所述第三电极,
其中所述第四布线的另一端电耦合至所述第一电容器的所述第四电极,
其中所述第二布线和所述第三布线通过所述第四电极电耦合,并且
其中所述第三布线和所述第四布线通过所述第四电极电耦合。
18.根据权利要求17所述的半导体器件,其中从所述第一电容器的所述第一表面到所述布线衬底的所述第一正面的长度等于从所述核心衬底的所述第二正面到所述布线衬底的所述第一正面的长度。
19.根据权利要求17所述的半导体器件,
其中所述第一电容器的所述第四电极具有多个过孔,
其中所述第二布线的另一端通过所述过孔中包括的第一过孔电耦合至所述第一电容器的所述第四电极,
其中所述第三布线的另一端通过所述过孔中包括的第二过孔电耦合至所述第一电容器的所述第四电极,
其中在平面图中,所述第四电极具有第一侧、沿着所述第一侧延伸的第二侧以及与所述第一侧和所述第二侧相交的第三侧,
其中在平面图中,所述第一过孔沿着所述第一侧设置,
其中在平面图中,所述第二过孔沿着所述第二侧设置,并且
其中在平面图中,所述第一过孔比所述第二过孔更接近所述第一侧并且比所述第二过孔更接近所述第三侧。
20.根据权利要求17所述的半导体器件,
其中所述布线衬底的所述第一背面具有所述第二外部电极中包括的第五电极,
其中具有多个电极的第二电容器被定位在所述核心衬底的所述第二正面与所述第二背面之间,
其中所述第一电容器还具有所述电极中包括的第六电极,
其中所述第二电容器具有所述电极中包括的第七电极和第八电极,
其中所述布线还包括第五布线、第六布线和第七布线,
其中所述第五布线的一端电耦合至所述第一电容器上的所述第六电极,
其中所述第五布线的另一端电耦合至所述第一背面上的所述第五电极,
其中所述第六布线的一端电耦合至所述第一正面上的所述第一电极,
其中所述第六布线的另一端电耦合至所述第二电容器的所述第七电极,
其中所述第七布线的一端电耦合至所述第二电容器的所述第八电极,
其中所述第七布线的另一端电耦合至所述第一背面上的所述第五电极,并且
其中所述第一电容器的容量小于所述第二电容器的容量。
21.根据权利要求19所述的半导体器件,其中所述布线衬底具有第三过孔,所述第三过孔被定位为通过所述第一侧与所述第一过孔相邻。
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KR102098592B1 (ko) * | 2018-07-05 | 2020-04-08 | 삼성전자주식회사 | 반도체 패키지 |
KR102163059B1 (ko) * | 2018-09-07 | 2020-10-08 | 삼성전기주식회사 | 연결구조체 내장기판 |
CN109300882A (zh) * | 2018-09-20 | 2019-02-01 | 蔡亲佳 | 堆叠嵌入式封装结构及其制作方法 |
CN113497014B (zh) * | 2020-03-21 | 2022-06-07 | 华中科技大学 | 一种多芯片并联的功率模块的封装结构及封装方法 |
US11605581B2 (en) | 2021-01-08 | 2023-03-14 | Renesas Electronics Corporation | Semiconductor device having conductive patterns with mesh pattern and differential signal wirings |
KR20220116922A (ko) * | 2021-02-16 | 2022-08-23 | 삼성전자주식회사 | 열 통로를 갖는 반도체 패키지 |
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JP5342154B2 (ja) * | 2008-02-25 | 2013-11-13 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5509362B1 (ja) | 2013-03-22 | 2014-06-04 | 太陽誘電株式会社 | 部品内蔵回路基板及びその検査方法 |
JP6266908B2 (ja) | 2013-07-09 | 2018-01-24 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
US20160183379A1 (en) * | 2014-12-22 | 2016-06-23 | Qualcomm Incorporated | Substrate comprising an embedded capacitor |
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US6370013B1 (en) * | 1999-11-30 | 2002-04-09 | Kyocera Corporation | Electric element incorporating wiring board |
CN1945816A (zh) * | 2005-10-05 | 2007-04-11 | 索尼株式会社 | 半导体器件及其制造方法 |
CN102118919A (zh) * | 2009-12-21 | 2011-07-06 | 瑞萨电子株式会社 | 电子器件和电子器件的制造方法 |
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CN108257945A (zh) | 2018-07-06 |
EP3343594A2 (en) | 2018-07-04 |
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US20180182700A1 (en) | 2018-06-28 |
KR20180077046A (ko) | 2018-07-06 |
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