TWI230103B - Semiconductor module and circuit substrate connecting to semiconductor device - Google Patents
Semiconductor module and circuit substrate connecting to semiconductor device Download PDFInfo
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- TWI230103B TWI230103B TW090107100A TW90107100A TWI230103B TW I230103 B TWI230103 B TW I230103B TW 090107100 A TW090107100 A TW 090107100A TW 90107100 A TW90107100 A TW 90107100A TW I230103 B TWI230103 B TW I230103B
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- solder
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- mass
- semiconductor device
- free solder
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12708—Sn-base component
- Y10T428/12715—Next to Group IB metal-base component
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
1230103 A7 B7 五、發明説明(1 -) (發明之背景) 本發明有關於安裝半導體裝置之技術。 按 BGA、CSP'WPP,倒裝片(fUp chip )等 等’外部電極上具有凸起體(凸起接點)(bump )(下面 稱、、凸起體〃)之半導體裝置之需要正增大中。這些外部 電極上備有凸起體之半導體裝置乃,例如在銅(C u )之 表面施予鎳一金(Ni/Au),鎳一鈀—金(Ni/ P d / A u )電鍍之電極圖樣上,以印刷塗上焊劑(nu}C ),而該上面將焊錫球載置於各電極上,施予回流加熱來 形成凸起體。 又’這些半導體裝置之安裝乃,對於基板之電極圖樣 以印刷來塗佈由焊錫粒子及焊劑所構成之焊錫膏材料,將 半導體裝置之凸起體對準位置地載置於基板之電極圖樣, 施予回流加熱而完成。 通常凸起體或安裝用所使用之材料乃,S η - 3 8 mass%P b之所謂S η — P b共晶焊錫。 近年來無鉛焊錫之實用化之要求很殷切。 以往即所使用之S η - P b共晶焊錫之融點係1 8 3 °C。而相對的無鉛焊錫之材料,例如S η - A g - C u係 焊錫之融點爲2 1 6 °C〜2 2 7 °C之範圍,與以往之S η 一 P b共晶焊錫比較時高。 另一方面經發明人之硏究查明。當將B GA等具有焊 錫凸起體之半導體安裝於基板時,與其他之安裝零件比較 時該焊錫凸起體係不容易熔融之事實。這是由於半導體裝 本紙张尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 請 先 閲 讀 背 面 之 注 意, 事 項 再
頁 訂 經濟部智慈財產局S工消費合作社印製 -4 1230103 A7 五、發明説明& ·) 置與基板之間之溫度(焊錫凸起體週邊之溫度)乃低於基 板或半導體裝置主體之溫度1 5 °C〜2 0 °C之緣故(經發 明硏究所查明),所以以可溶融這些無鉛焊錫凸起體地設 定回流溫度時,即基板或半導體裝置主體之溫度乃較半導 體裝置與基,板之間之溫度(焊錫凸起體週邊之溫度)而高 15〜2〇°C,成爲240°〜260°該基板或安裝於 基板之其他電子零件(電解電容器)之耐熱性將成爲問題 請 閲 讀 背 面 5 意 事 項 再 頁 (發明之槪說) 本發明之目的乃在於實現了考慮電路基板或電子零件 之耐熱性之高可靠性之錫焊連接者。 爲了達成上述目的而如申請專利範圍所述地構成者。 發明人乃注目於,當對於基板上安裝B GA等具有焊 錫凸起體之半導體裝置時,對於基板側供給焊錫膏,而由 所供給之焊錫膏與焊錫凸起體來形成連接部份之點 以往 般來說焊錫膏與焊錫凸起體係以同 經濟部智葸財產局員工消費合作社印製 構成,分別使之完全熔 焊錫凸起體視做用於錫 藉由焊錫膏而連接於該 並且積極的不要使焊錫 體之融點高於焊錫膏之 錫凸起體周圍之溫度很 錫凸起體容易熔融因此 融而實施錫焊連接。本發明 焊用材料,而視爲單純之電 電極(焊錫凸起體)地予以 凸起體完全熔融地,採用焊 融點之材料來構成。如上所 容易低於回流溫度,惟焊錫 確保焊錫連接係+很:容易也。 材料來 係f將 極,而 構成。 錫凸起 述,焊 膏比焊 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐〉 -5 1230103 A7 ________ B7_ 五、發明説明(3 / ) (請先閲讀背面之注意事項再填寫本頁) 所以焊錫凸起體之不會成爲完全熔融狀態之回流溫度 之狀態下,如果焊錫膏能熔融而形成連接部份時,就可以 實現考慮了電路基板及電子零件之耐熱性之高可靠性之錫 焊連接也。 例如使用安裝用焊錫膏而將外部電極爲焊錫凸起體之 半導體裝置安裝於基板時,該焊錫凸起體係使用S η -C u系或S η - A g - C u系之較以往之有鉛焊錫而融點 高之系列。而在基板安裝用焊錫即使用較上述焊錫凸起體 而融點低之組成,而以考慮了基板或電子零件等之耐熱性 之溫度之上實施回流(加熱)時,雖然該焊錫凸起體乃不 會完全地被熔融而會留下凸起體之形狀,惟在於焊錫凸起 體與熔融之安裝用之焊錫膏之間會形成混合層,由而高可 靠性的可以連接半導體裝置與電路基板也。再者在於考慮 形成混合層時不致於引起難以預料之中間組成物起見,即 焊錫凸起體及安裝用焊錫乃以使用同一種類之焊錫組成爲 合宜。 經濟部智慧財產局員工消費合作社印製 再者,採用S n — Ag — Cu系時,由Ag之含有量 而會發生針狀結晶之生成,及由它所引起之轉移或短絡等 問題。因此在於形成於半導體裝置與電路基板之間之焊錫 接合部之A g之含有量乃以少量爲宜。惟在本構造中,安 裝用焊錫乃須要使之成爲在於回流溫度就會熔融之組成比 才行。該組成比乃隨著回流(加熱)溫度所決定,因此可 以減少安裝用焊錫之A g量有限度。於是本案乃以設法減 少從焊錫凸起體而A g之漏入於安裝用焊錫中之量本身, 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -6 - 1230103 A7 B7_ 五、發明説明(4 ) 以資在於錫焊接合部中之A g之含有量不會增加地構成爲 宜。換言之焊錫凸起體之A g含量少於安裝用焊錫爲宜。 例如焊錫球係S η - C u系之焊錫亦可以。 再者安裝用焊錫系隨應於回流溫度由而決定組成,惟 以 Sn —約(2 · 0 〜3 · 5) mass%Ag — 約(〇· 3 〜0 · 8 ) mass % C u乃以連接之可靠性之點而言很合宜 ’於是焊錫球即以S η -約(〇 . 2〜2 . 0 ) mass % Ag —約(0 . 3 〜0 . 8%) mass%Cu 爲宜。 (合宜之實施形態之詳細說明) 下面使用附圖說明本發明之實施形態。 第1圖係本實施例所使用之B G A樣品之槪略。封包 尺寸係3 0 X 3 0 m m,內部中之晶片2之大小係1〇X 1〇111111。焊錫凸起體5係0〇.76 111111,又:6〇八基 板3之電極墊4係· 6mm墊材質係Cu,而其上面 之金屬敷層係採用N i ( 1 〇〜2 5 A m ) / A u電鍍( 〇·5 〜1.2/zm) 〇 另一方面,安裝基板9係厚度1mm之FR - 4基板 。基板之電極墊8係·6mm。材料Cu之上面之金 屬敷層係Ni (2Am)/Au (〇·〇3#m)。 安裝係在基板9之墊8之上使用印刷用遮蔽罩而將由 焊錫粒子與焊劑所構成之焊錫膏1 7而轉印於電極墊8。 對合焊錫凸起體5與基板9之電極墊8,而在基板9載置 於B G A施予回流加熱而可以實施。 ^紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) " (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慈財產局8工消費合作社印製 1230103 Α7 Β7 五、發明説明(5 ‘) 請 閲 讀 背 之 注 意 事 項 再 安裝時之回流加熱係在於空氣環境中可實施。惟本實 施例乃在於氮氣環境中實施。而該時之溫度乃做爲焊鍚連 接部之溫度,而實際地對於凸起體5與安裝基板墊7之間 放入熱電偶而測定了溫度而予以決定。 如本發明,使焊錫凸起體5與安裝用焊錫7之材料不 相同(與焊錫凸起體5比較而使安裝用焊錫之融點低·), 及兩者之材料之組合,體積比例。由回流加熱溫度而最終 的連接部分之形狀,以及組成乃會改變。 首先,將回流加熱溫度設於焊錫凸起體5之融點以上 之情形時,焊錫凸起體5與安裝用焊錫7乃完全融合在一 起而成爲如第2圖所示之ώ起體1 0之形狀,而焊錫即呈 顯均一組成。如果基板或其他電子零件之耐熱性充分足夠 時,如此地將·焊錫凸起體5與安裝基板墊7之間之溫度設 定於焊錫凸起體5之融點以上地設定回流加熱溫度亦可行 ,惟此時之焊錫連接部份係與先前技術之連接構造大致相 同,連接可靠性亦得於確保而並無問題。 經濟部智慈財產局員工消費合作社印¾ 接著說明在於上述對象構造中,以焊錫凸起體5之融 點與安裝用焊錫7之融點之間而實施回流加熱之情形。 此時由回流加熱溫度而安裝後之凸起體形狀(最終的 連接構造)就會改變。例如第3圖所示,安裝後之凸起體 形狀係與第2圖相同,惟組成並非均一,如由形成於 B GA基板3之凸起體5之組織及對它而安裝用焊錫所擴 散之混合層1 1之二層所形成或如第4圖所示混合層1 1 薄而基板側形成有由安裝用焊錫7所成之塡片等。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -8- 1230103 A7 __一 _ B7 五、發明説明(6 ) 再者,關於第4圖所示之混合層1 1 ,安裝用焊錫7 乃由安裝用焊錫之添加元素之分佈狀況而可以判斷。例如 第5圖所示,如果有比本來之安裝用焊錫7而添加元素之 it率低之領域1 1存在時,即該領域1 1可以判斷爲凸起 體5與安裝用焊錫7之混合層。如果與安裝用焊錫7所含 之組成大致相同就可以判斷爲那是安裝用焊錫。 又凸起體之安裝後之焊錫凸起體形狀,組織乃當然受 安裝當時之回流加熱溫度而改變,當然亦受焊錫凸起體材 料及安裝用焊錫凸起體之融點差,濕濡性,體積比例而改 變。 再者,如安裝用焊錫之比例高時,即如第7圖所示, 上述之混合層11 ,安裝用焊錫7係不只是存在於基板週 邊,連B G A用之凸起體5之側面也繞入,而呈顯安裝用 焊錫7之圍繞凸起體5之形狀。 例如凸起體,墊徑爲0 · 3 m m,安裝用焊錫印刷用 遮蔽罩之徑爲0 · 3mm,厚度爲〇 . 1 5mm時,凸起 體5之體積爲0 · 0 1 4mm3安裝用焊錫之體積爲 0 · 0 0 6 4mm3,而凸起體與安裝用焊錫之體積比例成 爲約2 : 1。安裝用銲錫之一部份係繞入於凸起體5之側 面,而成爲近乎第7圖之凸起體之構造之形態。以此形狀 乃在於5 5〜1 2 5 t之溫度週期試驗上完全無問題。 倒是由於凸起體5與安裝用焊錫7之接續面積增加, 由而可以提高可靠性。 如上所述’以第3、 4、 5、 7圖所示之構造’使安 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 請 先 閲 讀 背 面 之 注 意 事 項 再 } 經濟部智毪財產局員工消費合作社印災 1230103 A7 ____B7 _ 五、發明説明(7 ) 裝用焊錫5之融點低於焊錫凸起體之融點,而以焊錫凸起 體5之融點與安裝用焊錫之融點之間之溫度而實施回流加 熱所形成之連接構造時,雖然焊錫凸起體並不完全熔融而 會殘留惟藉由安裝用焊錫膏及混合層而可以高可靠性的連 接半導體裝置及電路基板。由此結果與先前技術之須完全 的熔解焊錫凸起體之做法而是得以考慮了基板或電子零件 之耐熱性之溫度而實施回流加熱也。 並且考慮第2圖所示之構造時,至少將回流加熱溫度 設於安裝用焊錫膏之會熔融之溫度時,就可以以上述其中 之一之連接形態地高可靠性的將半導體裝置與基板連接在 一起。按以往乃採用完全的令焊錫凸起體及焊錫膏熔融而 連接,因此在於組裝具有焊錫凸起體之半導體裝置時,該 基板及電子零件之耐熱性係構成一問題。惟如上述地,焊 錫凸起體並不一定有熔融之必要時,該問題很容易解決也 0 按如上述’以安裝用焊錫爲主的使之熔融連接時,在 於該安裝用焊錫上使用低融點(1 3 7 °C )之S η -1 A g - 5 7 B i焊錫而可能做到維修可能之搆造。 按對於安裝B G A等之半導體裝置之電路基板之一部 份供給低溫之無鉛焊錫,而在其外之領域供給通常之高融 點之S η - A g - C u示之無鉛焊錫時,就可以將半導體 裝置之凸起體連接合加熱至1 3 7°C以上就可以卸下具有 上述凸起構造之電子構件,於是以低溫就可以實施修理。 因此關於有需要修理之必要時即將回流加熱溫度設於 本紙張尺度適用中國國家標準(CNS ) Α4規格(2丨0Χ297公釐) 請 閲 讀 背 之 注 意 事 項 再 頁 經濟部智慈財產局員工消費合作社印製 -10 1230103 A7 B7 五、發明説明 經濟部智慧財產局員工消費合作社印製 1 6 0 °C ’形成低溫焊錫之塡片爲宜。又,使用於安裝用 焊錫之組成並不限定爲S η — 1 a g — 5 7 B i ,只要低 於焊錫凸起體之融點就可以。當然愈低愈在低溫之下可以 修理’惟當然須要在於通常動作狀態之下不致於熔融之程 度之溫度才可。 下面說明’使安裝用焊錫膏了之融點低於焊錫凸起體 5之融點’而以焊錫凸起體5之融點與安裝用焊錫7之融 點之間之溫度實施回流加熱所形成之連接構造之可靠性。 第6圖係,做爲焊錫凸起體而使用S η - A g — C u (Sn-3.5Ag-0.75Cu),而以較它更低融 點之各種安裝用焊錫膏安裝後—5 5〜1 2 5 °C 1〇0 0週期後之評鑑結果。 實驗所使用之樣品即凸起體徑(球徑0 . 7 6 m m ) ,墊徑爲0·60mm時,焊錫凸起體之體積係〇.23 m m 3,安裝用焊錫(印刷遮蔽罩):〇 · 7 6 m m徑,t 二0 . 1mm,假定溶劑成分10%)。係〇 · 〇4mm3 。凸起體與安裝用焊錫之體積比乃約6:1。通常此體積 比乃由凸起體徑,墊徑,印刷遮蔽罩之徑及厚度而改變, 如凸起體,墊變小換言之狹節距化時安裝焊錫之比率將變 尚。 安裝後之凸起體形狀乃安裝用焊錫7之於S η - 3Ag — 5Bi ,Sn — 3Ag — 3 之狀態下,由加 熱溫度而安裝後之凸起體之形狀係會微妙的改變。均於 2 1 5 °C呈第3圖之凸起體形狀,於2 1 0 t即呈第4圖 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 請 先 閲 讀 背· Sj 之 注 意· 事 項 μ 訂 ml· 11 - 1230103 A7 B7 五、發明説明(9 ) 之凸起體形狀,在2 0 5 t即呈安裝用焊錫之一部份熔融 不良。再者在這二種之焊錫時,於2 1 5 °C、2 1 〇 °C再 者均在於1 0 0 0週期後均看不出有成問題之龜裂。發生 龜裂之梢數,最大龜裂長度乃與2 2 0 °C安裝之S η — 3 A g — 0 . 7 C u,或以往之S η — P b共晶焊錫大致 同等,因此雖然加熱溫度雖高於S η - P b焊錫,惟較 S η — 3 A g — 〇 . 7 C u可以將降低加溫溫度1〇°C程 度。 以近於S η — P b共晶焊錫之同一溫度所安裝之S η 一 9Zn,Sn — 8Ζη - 3Β 1之安裝體也看不出有成 問題之龜裂,惟由於Ζ η係活性強之金屬,與熔劑之反應 性高,因此對於基板之印刷性或長期之保存安定性係成爲 問題。而以與S η — P b共晶焊錫大致同一溫度就可以安 裝之Sn — 2 · 8Ag— 15Bi_焊錫時,在很多之凸起 體查出有龜裂,而在於1 0 0 0週期之試驗時發生了超過 超徑4長度之龜裂,未並沒有到達至斷線剝離之狀態’屬於 低溫焊錫之S η — 1 A g - 5 7 B 1焊錫也在多數之凸起 體上發生龜裂,惟沒有嚴重至全面剝離之形狀。 安裝用焊錫7係S η — Ζ η係,S η — A g -15Bi ,Sn — lAg — 57Bi時’均呈第3圖所不 之凸起體組織。而將回流加熱溫度更靠近於安裝用焊錫7 之溫度即凸起體形狀將變至如第4圖之形狀。例如以S η —1 A g — 5 7 Β 1爲安裝用焊錫,以1 6 5 °C實施回流 加熱時,上述焊錫之一部份係擴散至焊錫凸起體,形成混 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 請 先 閲 ik 背· 面 之 注, 意 事 項
經濟部智慧財產局P'工消費合作社印製 -12- 1230103 A7 _;_B7 五、發明説明(ίο Ί 合層1 1,惟大部份係在於安裝基板側之電極上形成S η 一 1 A g - 5 7 Β 1之塡片。再者,將回流加熱溫度降到 近乎Sn - lAg — 57B 1之焊錫之融點之1 5 0°C時 ,雖然確認不出有混合層1 1 ,惟會形成如第4圖所示之 塡片。雖然不形成有擴散相時,可靠性上並沒有問題,惟 回流加熱溫度係靠近於安裝用焊錫之融點,所以如果封包 內之溫度有很大之偏差時,溫度低之凸起體時有安裝用焊 錫7之不會熔融因此需要注意。 S η — 1 A g — 5 7 B i焊錫融點係1 3 7 °C。所以 具有形成塡片之凸起體構造之安裝體,在於- 5 5 °C〜 1 2 5 °C地實施溫度週期試驗時塡片部份會軟化。在於 〇°〜90°C之溫度週期即在於10 〇〇週期後也沒有看 出有龜裂發生。由於形成上述之焊錫組成之塡片部份由而 在於此塡片部份會熔融,因此將凸起體接合部加熱至 1 3 7°C以下就可以拆卸具有上述凸起體構造之電子零件 於是得在於低溫就可實施修理。須要實施修理時即以回流 加熱溫度爲1 6 0 °C程度,而形成低溫焊錫之塡片係必要 者。 如上所述以焊錫凸起體之融點以下之溫度來回流加熱 時均得於確保了連接之可靠性者。 如上所述,將與以往之S η - P b之共晶焊錫而融點 高之無鉛焊錫凸起體之半導體裝置安裝於基板時,使用較 上述焊錫凸起體之融點低之焊錫,而在於凸起體基體內形 成焊錫凸起體及安裝用焊錫之混合層,由而可以獲得具有 本紙伕尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 請 先 閲 讀 背 面 之 注 意 事 項 再 頁 經濟部智慧財產局員工消費合作社印¾ -13- 經濟部智慧財產局員工消費合作社印製 1230103 Α7 Β7 五、發明説明(η ) 與以往者同可靠性水平之無鉛之凸起體構造之半導體裝置 也。 下面說明將此基本構成適用於多片模組(半導體模組 )之例子。 對於半導體之高積體化,半導體裝置之小型化,高密 度安裝之要求而將記憶體,A S I C,C P U等之各種半 導體集合於一模組或滙集於封裝之多片模組(M C Μ )或 多片封裝乃已被開發。 第8圖顯示其一例,這是將上述說明之焊錫連接構造 使用於多片模組內之例子。 圖中,在於中間基板2 5之上面,多數地載置對於 W P P ( Wafcn Process Package ),或 Waferlevel CSP 之砍 晶片2 0施予配線’而在晶片2 0之電極2 1上形成焊錫 2 2之封裝(以後稱W P P )之W P P。形成於此中間基 板25之凸起體27之徑爲·76節距爲1.27 mm,而中間基板上之WP P之凸起體2 1之徑爲0 . 3 mm,節距爲〇 · 5mm,又中間基板2 5上面之WPP 係載置之後,在於凸起體連接部份施予不滿料部份2 4。 又凸起體2 2係半導體裝置之外部電極,凸起體2 7即成 爲多片模組之外部連接端子,下述之實施例也同樣。 第9圖表示於中間基板上載置了WP P之槪略。圖中 ,在於中間基板2 5上印刷了焊錫膏2 8之後,將中間基 板2 5與W P P予以對準位置之後實施回流加熱之接合。 使用於W P P側之焊錫2 2係S η - 〇 · 7 5 C u,另一 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) : ' • 14-
1230103 A7 B7 五、發明説明(12 ') 方面印刷於中間基板之焊錫膏2 8係3:1 — 3八2 — 0 · 5 C u。換言之做成較焊錫膏2 8之融點而焊錫2 2 之融點高之組成。而中間基板2 5之凸起體2 7係使用與 WPP之安裝之焊錫膏28相同之Sn — 3Ag — 〇 . 5 C u 〇 第1 0圖表示將該多片模組接合於安裝基板後之斷面 形狀。 中間基板2 5側之安裝後之W P P之凸起體係並不形 成爲均一之焊鍚組成,而成爲由原來之焊錫組成之部份 3 0,及WPP凸起體之Sn — 〇 . 75Cu,及安裝用 焊錫之S η - 3 A g - 0 · 5 C u之混合層3 1所構成。 按在於S η —六2 — (:11系之焊錫中,如果含厶2達 3 %以上時會發生所謂 ''威斯卡〃之金屬之針狀之結晶, 而由它之到達至鄰接之凸起體,致使發生短絡,於是本實 施例乃爲了防止該威斯卡所致之短絡,在於W Ρ Ρ使用不 含Ag之S n — C u之焊錫又凸起體2 7雖然使用了 S η 一 3 A g — 〇 . 5 C u焊錫,惟在於回流加熱後之凸起體 之混合層中,由於A g組成低於3 %所以不會發生威斯卡 (針狀組織)。使用於W P P凸起體之焊錫組成而言使用 Ag組成係1%之Sn — lAg — 0 · 5Cu也沒有問題 。上述S η — C u焊錫之融點之差僅有1 °C。如上所述安 裝於中間基板2 5上之半導體裝置乃如考慮到對於安裝基 板4 1上之多片模組而更爲.狹節距化之情形來說’在於中 間基板2 5上之安裝上,使用A g組成少之焊錫乃在於可 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) : (請先閲讀背面之注意事項再填寫本頁) 衣 訂 經濟部智恶財1局員工消費合作社印製 -15 - 1230103 A7 五、發明説明(13 ) 以抑制由發生威斯卡所致之端子間之短絡之點很合宜。 如果中間基板2 5之具有足夠之耐熱性時,W P P, B G A之凸起體2 2或焊錫膏2 8可使用A g組成少之焊 錫,而於安裝基板上可以使用比它融點低,所謂標準組成 之焊錫。當然在多片模組之對於安裝用基板4 1之安裝上 得採用上述之本發明之構造。 下面說明,前面所述之錫焊連接構造使用於將多片模 組安裝於電路基板上所使用之例子。 第11圖表示,將半導體裝置之凸起體2 2及多片模 組之凸起體27均使用Sn-0·75Cu或Sn— lAg — 〇 · 5Cu,而將該多片模組之凸起體使用比上 述者之融點低之焊錫3 5,例如S η - 3 A g — 〇 . 5 C u而安裝於基板時之載置之槪要。第1 2圖即表示基板 安裝後之斷面形狀。安裝後之多片模組之連接構造乃由本 來之凸起體組成部份5 0及凸起體與安裝用焊錫之混合層 5 1所構成。 在於多片模組中,有時候於安裝於中間基板之半導體 裝置等之焊錫連接,與多片模組之外部連接端子(焊錫球 )之間,需要有溫度階層連接。這是爲了將多片模組錫焊 連接於電路基板時,在於多片模組內已經被連接之半導體 裝置與中間基板之焊錫連接之不會再熔接,確保該高可靠 性之連接之緣故。 而依上述構造時,在於熔融安裝用之焊錫3 5而連接 之回流溫度中,可選定具有半導體裝置之凸起體2 2 ’多 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 請 先 閲 讀 背 之 注 意 事 項 頁 經濟部智慧財產局8工消費合作社印奴 16- 1230103 A7 B7 五、發明説明(14 ) 請 先 閱 讀 背 & 之 注 意 事 項 片模組之凸起體2 7地各個本身之大致不熔融之融點之組 成。因此在於多片模組內不實施溫度階層連接之下,仍然 可能實現高可靠性之連接。又,焊錫3 5熔融時,在其接 觸部份而多片模組之凸起體2 7也一部份成熔融狀態,而 會形成混合層5 1。當然欲更抑制多片模組內之再熔融時 ,即將使用於半導體之凸起體2 2之焊錫選用較多片模組 之凸起體2 7所用之焊錫材料之融點高者就可以。又兩者 之情形中,中間基扳乃需要使用較安裝用基板更具有耐熱 性者爲宜。 經濟部智慧財產局員工消費合作社印製 按W P P係對於矽晶片2 0施予配線而在晶片狀之電 極2 1上形成凸起體2 2之封裝。所以直接安裝於印刷基 板時,由矽晶片2 0與印刷基板(中間基板2 5 )之物性 (特別是熱膨脹)之不同所發生之應力之影響而凸起體 2 2有剝離之虞。因此在於晶片2 0與中間基板2 5之間 注入不滿材部2 4 ( unden fUl )而做凸起體之補強,除了 注入不滿材部之外,如第1 3圖,第1 4圖所示在於晶片 與凸起體之間設置樹脂材料所成之應力緩和層。此時即不 需不滿材部。又第1 3圖係對應於第1 0圖之構造者。第 1 4圖係對應於第1 2圖之構造者。 接著第1 5圖乃將使用玻璃,或矽基板之半導體裝置 安裝於基板4 1之例子。上述基板係在該周圍拉繞配線 7 2,於週邊配置有應力緩和層7 1。而在該下面形成有 凸起體5 0、5 1。另一方面在於矽基板7 0之中心附近 ,於基板之下面有朝向安裝基板4 1側地以凸起體2 2安 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) -17- 1230103 Α7 Β7
W 五、發明説明(15,) 裝W p p之矽晶片2 〇 P P及應力緩和層7 1之下側所使用之焊錫2
C
0係例如S η - 0 · 7 5 C S η 1 A g — 〇 · u 般之A g之組成少之焊錫,而安裝於基板4 1時係
般性之S η A g - C u焊錫係例如S η — 3 A g 0 · 5Cu。所以在基板41上之安裝後之凸起體構造中 有含有安裝焊錫之混合層5 1。矽基板7 0係與W P P之 晶片2 〇在物性上並沒有差異,所以W P P之晶片2 0與 石夕基板7 0間之凸起體接合部份可以不加入不滿材部。 如上所述,在於多片模組之構造中,W P P,或 β G A等之半導體裝置所具有之凸起體之無鉛焊錫乃採用 A g組成少之,例如S η —約(〇〜2 · 0 ) mass % A g 一約(Ό · 3〜Ο · 8 ) mass %Cu,而將這些半導體裝 置安裝於中間基板時之焊錫即採用較上述焊錫而融點低之 請 先 閲 讀 背 面 之 注 意 事 項
S 經濟部智慧財產局員工消費合作社印製 3 . 5) mass%Ag —約(〇 · 3 0 · 8 ) mass % C u由而可以防止威斯卡(針狀結晶)之 發生,可以對應於0 · 3 m m以下之狹節距之安裝。當然 這是對於多片模組所具有之凸柱體及使用於安裝基板側之 安裝用焊錫之關係也同樣。 再者安裝用之焊錫即只要焊錫凸起體之融點比較高即 上述 Sn —約(2 · 5 〜3 · 5) mass%Ag - 約( 〇· 3〜0 · 8 ) mass % C u以外之焊錫就任何者均可以 用,此時就可以考慮例如含有B i之焊錫,或S η - Ζ η 系之焊錫。 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) -18- 1230103 Α7 Β7 五、發明説明(16 · 依本發明時,可以實現考慮了電路基板或電子零件之 耐熱性之高可靠性之焊錫之連接(錫焊)也。 圖式之簡單說明 第1圖係表示本實施例所使用之B G A樣品之槪略圖 〇 第2圖係表示基板安裝後之B G A之槪略圖。 頁 第3圖係表示安裝後之凸起體組織乃由焊錫凸起體5 之組織及安裝用焊錫之混合層1 1之二相所形成之情形之 圖。 第4圖係表示混合層1 1薄,而在基板側有由安裝用 焊錫7所成之塡料所形成之凸起體之圖。 第5圖係說明區別混合層與安裝用焊錫層之方法之用 之圖。 第6圖係表示Sn — 3 . 5Ag — 〇 · 75Cu凸起 體BGA之以各種安裝用焊錫膏來安裝者之,5 5〜 1 2 5 °C,1 0 0週期後之評鑑結果之表。 經濟部智慧財產局員工消費合作社印製 第7圖係表示安裝用焊錫之一部份繞入於凸起體之側 面之凸起體構造之圖。 第8圖係表示多片組片(M C Μ )之一例之圖。 第9圖係表示WP Ρ之焊錫2 2與B GA基板之安裝 用焊錫2 8之不同時之載置槪略圖。 第1 0圖係表示WP Ρ之焊錫2 2與B GA基板之安 裝用焊錫2 8之不同時之安裝後之槪略圖。 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) -19- 1230103 A7 ____B7 五、發明説明W :> 第1 1圖係表示使用WPP之凸起體2 2及較bga 凸起體2 8而融點低之焊錫3 5而安裝於基板時之載置時 之槪略圖。 (請先閱讀背面之注意事項再填寫本頁) 第1 2圖係表示基板安裝後之槪略圖。 第1 3圖係表示載置備有應力緩和層之WP P之 M C Μ 者。 第1 4圖係表示載置備有應力緩和層之W Ρ Ρ之 M C Μ 者。 第1 5圖係表示將使用矽基板7 0之半導體裝置安裝 於基板之例子。 主要元件對照表 2 晶片 3 B G Α基板 4 電極墊 5 焊錫凸起體 7 安裝用焊錫(焊錫膏) 經濟部智慧財產局員工消費合作社印製 8 電極墊 9 安裝基板 10 凸起體 11 焊錫混合層 2 0 砂晶片 2 1 電極(凸起體) 22 焊錫凸起體 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) • 20 -
Claims (1)
- 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 第90 1 07 1 00號專利申請案 中文申請專利範圍修正本 民國9 2年11月5日修正 1 · 一種半導體模組,主要乃,於安裝了半導體裝置 之基板上,形成外部連接端子之半導體模組中,其特徵爲 以第1之無鉛焊錫所形成之焊錫凸起體來構成該半導 體裝置所具有之外部電極,而介著較第1無鉛焊錫低融點 之第2無鉛焊錫所形成之焊錫膏而連接該半導體裝置之外 部電極者。 2 .如申請專利範圍第1項所述之半導體模組,其中 上述第1 ,第2無鉛焊錫乃使用同一種類之無鉛焊錫 者。 3 .如申請專利範圍第2項所述之半導體模組,其中 上述第1 ,第2無錯焊錫乃以Sn—Ag—Cu系之 焊錫所構成者。 4 .如申請專利範圍第3項所述之半導體模組,其中 上述第1無鉛焊錫係S η -約(0〜2 _ 0 ) mass% Ag —約(0 · 3〜0 · 8)mass Cu ’而上述第2無 鉛焊錫係S η —約(2 · 5〜3 . 5 ) mass% A g -約( 0 .3〜0. 8)mass Cu 者。 5 . —種半導體模組,主要乃於安裝了半導體裝置之 基板上形成外部連接端子之半導體模組中,其特徵爲: 本^張尺度適用中國國家標準(CNS ) A4it格(210\ 297公釐1' 1 一 一 (請先閣讀背面之注意事項再填寫本頁)1230103 A8 B8 C8 D8 夂、申請專利範圍 C請先閱·#背面之注意事項再填寫本頁} 以Sn —約(〇 · 7〜〇.8)mass%Cu之第1無 錯焊錫所構成之焊錫凸起體而形成該半導體裝置所具有之 外部電極’而介著較第1無鉛焊錫爲低融點之s η -約( 2.〇〜3 · 5)mass%Ag —約(〇· 3 〜〇· 8) mass% C u之第2無鉛焊錫所形成之焊錫膏來連接該半導 體裝置之外部電極者。 6 ·如申請專利範圍第1項所述之半導體模組,其中 上述弟2無鈴焊錫係Sn — (〇 — 3)mass%Ag -(1 〜5 8)mass%Bi - (〇 — i)mass%Cu — (◦〜5 )mass% I η 者。 7 ·如申請專利範圍第1或2,3,4,5 ,6項之 任一項所述之半導體模組,其中上述焊錫凸起體之一部份 係不熔融地構成連接部者。 8 · —種電子電路基板,具備:外部電極係焊錫凸起 體之半導體裝置,以及介著焊錫膏而與該半導體裝置之外 部電極連接之電路基板,而以第1無鉛焊錫構成該焊錫凸 起體,而以較第1無鉛焊錫爲低融點之第2無鉛焊錫來構 成上述焊錫膏爲其特徵者。 ’ 經濟部智慧財產局員工消費合作社印製 9 .如申請專利範圍第8項所述之電子電路基板,其 中 上述第1 .,第2無鉛焊錫乃使用同一種類之無鉛焊錫 者。 1 〇 ·如申請專利範圍第9項所述之電子電路基板, 其中 本紙張尺度適用中國國家標準(CNS ) Α4規格(2丨0X297公釐) :rTz 1230103 A8 B8 C8 D8 申請專利範圍 上述第1 ’桌2之無船焊錫係,s 之焊錫所構成者。 II— Ag — Cu 系 •如申§胃㈣i Q項所述之電子電路基板 其中 上述第1無鉛焊錫係S η —約(〇〜2 . 〇 ) A g -約(〇 · 3〜0 · 8 ) mass% Cu,而上述第2無 鉛焊錫係S η —約(2 · 5〜3 · 5 ) mass% a g —約( Ο · 3 〜0 . 8)niass%Cu 者。 1 2 . —種電子電路基板, 凸起體之半導體裝置,及介著焊 外部電極連接之電路基板, 具備有該外部電極爲焊錫 錫膏而與該半導體裝置之 8)11^83%<:1:之第1無 鉛焊錫構成該焊錫凸起體,而以較該S n 一 C u系之無錯 以 S η —約(0 · 7 〇 焊錫爲低融點之S n -約(2 · —約(0 . 3 〜〇· 8 ) m a s s % 〇 〜3 · 5 ) mass%Ag C u之第2無錯焊錫來構 成該焊錫膏爲其特徵者。 1 3 ·如申請專利範圍第8項所述之電子電路基板, 經濟部智慧財產局員工消費合作社印製 其中 上述第2無鉛焊錫係S η -(1 〜5 8) mass%B i —(〇 〜5) mass% I η 者。 (◦〜3 ) mass% A 1 ) mass% C u g 〇 1 4 .如申請專利範圍第8項或9 ,1 0 ,1 l , 1 2’ 1 3項其中之一·項所述之電子電路基板,其中,上 述焊錫凸起體之一部份係不熔融地構成連接部者。 (請先閲脅背面之注意事項再填寫本頁)本紙張尺度適用中國國家禚準(CNS ) A4現^ ( 210X297公釐)
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2001
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- 2001-03-20 US US09/811,445 patent/US6486411B2/en not_active Expired - Lifetime
- 2001-03-26 TW TW090107100A patent/TWI230103B/zh not_active IP Right Cessation
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CN106030783A (zh) * | 2014-03-27 | 2016-10-12 | 英特尔公司 | 用于低温附接的混合互连 |
CN106030783B (zh) * | 2014-03-27 | 2019-06-18 | 英特尔公司 | 用于低温附接的混合互连 |
Also Published As
Publication number | Publication date |
---|---|
US7145236B2 (en) | 2006-12-05 |
KR100398716B1 (ko) | 2003-09-19 |
KR20010112057A (ko) | 2001-12-20 |
US20010050181A1 (en) | 2001-12-13 |
US6486411B2 (en) | 2002-11-26 |
US20030030149A1 (en) | 2003-02-13 |
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