JP5202233B2 - 実装構造体 - Google Patents
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- JP5202233B2 JP5202233B2 JP2008282666A JP2008282666A JP5202233B2 JP 5202233 B2 JP5202233 B2 JP 5202233B2 JP 2008282666 A JP2008282666 A JP 2008282666A JP 2008282666 A JP2008282666 A JP 2008282666A JP 5202233 B2 JP5202233 B2 JP 5202233B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/264—Bi as the principal constituent
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図4(a)は平面図、図4(b)は図4(a)のA−AA断面図であって、図4(b)では一部が拡大して図示されている。BGA(Ball Grid Array)/LGA(Land Grid Array)などの半導体パッケージ2や半導体パッケージ以外のチップ部品3は、半田5によって基板1に実装されている。
また、本発明の実装構造体は、基板に、融点が70〜138℃で、50〜70重量%のBi、10〜25重量%のIn、0.001〜0.1重量%のNi、残部Snを含んでなる半田によって、半導体素子が実装され、前記基板に、前記半田によって、前記半導体素子とは別のチップ部品が実装され、前記半導体素子と前記基板との間の第1空間と、前記チップ部品と前記基板との間の第2空間と、前記半導体素子と前記チップ部品との間の前記基板面上の第3空間とが、封止樹脂によって一体に封止されたことを特徴とする。
また、本発明の実装構造体は、基板に、融点が70〜99℃で、60〜70重量%のBi、15〜25重量%のIn、残部Snを含んでなる半田によって、半導体素子が実装され、前記基板に、前記半田によって、前記半導体素子とは別のチップ部品が実装され、前記半導体素子と前記基板との間の第1空間と、前記チップ部品と前記基板との間の第2空間と、前記半導体素子と前記チップ部品との間の前記基板面上の第3空間とが、封止樹脂によって一体に封止されたことを特徴とする。
(実施の形態1)
図1(a)(b)は本発明の実施の形態1を示す。
基板1の上には、半導体素子としての半導体パッケージ2a,2bと、半導体素子を除く電子部品としてのチップ部品3が実装されている。チップ部品3は隣接して配置された半導体パッケージ2a,2bの2つの間で、半導体パッケージ2a,2bの幅に入るように実装されている。これら半導体パッケージ2a,2bの2つと、チップ部品3の5つを封止するように、封止樹脂4が設けられている。半導体パッケージ2a,2bとチップ部品3は、半田5で基板1に実装されている。ここでは、チップ部品3が半導体パッケージ2a,2bの中間位置に実装されている。
実装に使用した半田5の組成を下記の表1に示す。残部はBal.として表記した。
また、半導体素子を除く電子部品として、抵抗器のチップ部品3を例に挙げて説明したが、コンデンサやコイルなどでもよい。
図2(a)が半導体素子が1つの場合の平面図、図2(b)がそのA−AAの断面図である。半導体素子としての半導体パッケージ2とチップ部品3が長方形になるように配置されている。その中央に封止樹脂4を塗布する位置を設定する。図1(a)(b)と同様に、均等に封止樹脂4が行きわたる。
本発明の第2の形態においては、図1(a)(b)の実施の形態において、その基板1の厚みの変化をさせて、温度サイクル寿命試験をした。温度サイクル寿命試験は、実施の形態1と同じである。その結果を、下記の表2に示す。この表2では、基板1の厚さが0.25〜0.80mmまで変更した場合の温度サイクル特性を示している。
実施の形態3は、図1(a)(b)における半導体パッケージ2a,2bの間の距離についての実施例である。
上記の各実施の形態では、封止樹脂4で半導体素子としての半導体パッケージ2a,2bの全体と、それ以外の電子部品としてのチップ部品3の全体を覆うことはしなかった。側面を封止するのみで十分強度が保てた。
2a,2b 半導体パッケージ(半導体素子)
3 チップ部品(半導体素子を除く電子部品)
4 封止樹脂
5 半田
Claims (4)
- 基板に、融点が70〜138℃で、50〜70重量%のBi、10〜25重量%のIn、0.001〜0.1重量%のGe、残部Snを含んでなる半田によって、半導体素子が実装され、
前記基板に、前記半田によって、前記半導体素子とは別のチップ部品が実装され、
前記半導体素子と前記基板との間の第1空間と、前記チップ部品と前記基板との間の第2空間と、前記半導体素子と前記チップ部品との間の前記基板面上の第3空間とが、封止樹脂によって一体に封止された
実装構造体。 - 基板に、融点が70〜138℃で、50〜70重量%のBi、10〜25重量%のIn、0.001〜0.1重量%のNi、残部Snを含んでなる半田によって、半導体素子が実装され、
前記基板に、前記半田によって、前記半導体素子とは別のチップ部品が実装され、
前記半導体素子と前記基板との間の第1空間と、前記チップ部品と前記基板との間の第2空間と、前記半導体素子と前記チップ部品との間の前記基板面上の第3空間とが、封止樹脂によって一体に封止された
実装構造体。 - 基板に、融点が70〜99℃で、60〜70重量%のBi、15〜25重量%のIn、残部Snを含んでなる半田によって、半導体素子が実装され、
前記基板に、前記半田によって、前記半導体素子とは別のチップ部品が実装され、
前記半導体素子と前記基板との間の第1空間と、前記チップ部品と前記基板との間の第2空間と、前記半導体素子と前記チップ部品との間の前記基板面上の第3空間とが、封止樹脂によって一体に封止された
実装構造体。 - 前記基板の厚さが,0.5mm以下である請求項1〜請求項3の何れかに記載の実装構造体。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008282666A JP5202233B2 (ja) | 2007-11-01 | 2008-11-04 | 実装構造体 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007284976 | 2007-11-01 | ||
JP2007284976 | 2007-11-01 | ||
JP2008282666A JP5202233B2 (ja) | 2007-11-01 | 2008-11-04 | 実装構造体 |
Publications (3)
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JP2009135479A JP2009135479A (ja) | 2009-06-18 |
JP2009135479A5 JP2009135479A5 (ja) | 2011-09-15 |
JP5202233B2 true JP5202233B2 (ja) | 2013-06-05 |
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JP2008282666A Active JP5202233B2 (ja) | 2007-11-01 | 2008-11-04 | 実装構造体 |
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US (1) | US8410377B2 (ja) |
JP (1) | JP5202233B2 (ja) |
KR (1) | KR101011199B1 (ja) |
CN (1) | CN101425511B (ja) |
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JP2011100718A (ja) * | 2009-10-05 | 2011-05-19 | Yazaki Corp | コネクタ |
JPWO2011114759A1 (ja) * | 2010-03-19 | 2013-06-27 | 株式会社安川電機 | 電子部品の実装方法および電子機器 |
JP5785760B2 (ja) * | 2011-04-11 | 2015-09-30 | 日本特殊陶業株式会社 | 部品実装基板 |
US10032692B2 (en) * | 2013-03-12 | 2018-07-24 | Nvidia Corporation | Semiconductor package structure |
EP3499554A1 (de) * | 2017-12-13 | 2019-06-19 | Heraeus Deutschland GmbH & Co. KG | Verfahren zur herstellung einer sandwichanordnung aus zwei bauelementen mit dazwischen befindlichem lot mittels heisspressens unterhalb der schmelztemperatur des lotmaterials einer lotvorform |
US20210283727A1 (en) * | 2018-10-24 | 2021-09-16 | Alpha Assembly Solutions Inc. | Low temperature soldering solutions for polymer substrates, printed circuit boards and other joining applications |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH02260592A (ja) * | 1989-03-31 | 1990-10-23 | Mitsumi Electric Co Ltd | 回路基板 |
JPH0327441A (ja) | 1989-06-23 | 1991-02-05 | Nippon Telegr & Teleph Corp <Ntt> | 知識情報処理システムにおけるデータベース利用方式 |
JP3027441B2 (ja) | 1991-07-08 | 2000-04-04 | 千住金属工業株式会社 | 高温はんだ |
US5520752A (en) | 1994-06-20 | 1996-05-28 | The United States Of America As Represented By The Secretary Of The Army | Composite solders |
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- 2008-10-23 KR KR1020080104081A patent/KR101011199B1/ko active IP Right Grant
- 2008-10-29 US US12/260,219 patent/US8410377B2/en active Active
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KR20090045016A (ko) | 2009-05-07 |
CN101425511B (zh) | 2014-10-29 |
US20090116205A1 (en) | 2009-05-07 |
CN101425511A (zh) | 2009-05-06 |
KR101011199B1 (ko) | 2011-01-26 |
US8410377B2 (en) | 2013-04-02 |
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