TW473945B - Semiconductor device and its manufacturing process - Google Patents
Semiconductor device and its manufacturing process Download PDFInfo
- Publication number
- TW473945B TW473945B TW89110099A TW89110099A TW473945B TW 473945 B TW473945 B TW 473945B TW 89110099 A TW89110099 A TW 89110099A TW 89110099 A TW89110099 A TW 89110099A TW 473945 B TW473945 B TW 473945B
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- Taiwan
- Prior art keywords
- substrate
- semiconductor wafer
- semiconductor
- semiconductor device
- wafer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 246
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000011347 resin Substances 0.000 claims abstract description 93
- 229920005989 resin Polymers 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 235000012431 wafers Nutrition 0.000 claims description 213
- 238000000227 grinding Methods 0.000 claims description 59
- 238000005520 cutting process Methods 0.000 claims description 36
- 238000007789 sealing Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 24
- 230000001681 protective effect Effects 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 11
- 230000002079 cooperative effect Effects 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 9
- 230000000875 corresponding effect Effects 0.000 description 7
- 239000007788 liquid Substances 0.000 description 6
- 238000005336 cracking Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 238000007639 printing Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000009941 weaving Methods 0.000 description 1
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Classifications
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Wire Bonding (AREA)
Description
473945 A7 Β7 五、發明說明(1 ) [發明所屬技術領域] (請先閱讀背面之注意事項再填寫本頁) 本發明係尤其有關一種對於薄型化有利之半導體裝置 及其製造方法。 [先行技術] 半導體裝置之典型裝配步驟係包括··將半導體晶圓切 割而製成個別半導體晶片之步驟,將半導體晶片晶粒黏接 於引線框之步驟’將半導體晶片之墊部與引線框予以引線 搭接之步驟以及’在將引線拉出於外部之狀態下進行樹脂 镑模之步驟。 為求半導體裝置整體之薄型化,需將半導體晶片本身 薄型化,。於是,有在將半導體晶圓切割(dicing)之前,先將 晶圓之非活性表面(背面)以研磨機研削之研削步驟。如 此,將磨薄到一定厚度之晶圓予以切割,而獲得個別半導 體晶片。 然而,將磨薄之半導體晶圓以切割機(dicingsaw)切割 時’難免產生晶圓破裂或晶片缺角等情事。因而,切割前 之晶圓之薄型化程度有其限度β 經濟部智慧財產局員工消費合作社印製 於疋,近來乃有先行切割,而後才研削晶圓背面之提 案。亦即,如第9Α圖所示,於晶圓1〇〇之活性表面1〇1 外露之狀態,在非活性表面102侧貼上切割膠帶ι〇5。在 此狀態下,進行半切割步驟,亦即,以切割機! 〇7在晶圓 100之活性表面101側,切割一條深度約50μπι之切割溝 槽103。接著,如第9Β圖所示,撕掉非活性表面1〇2側之 切割膠帶105,而在活性表面101側貼上切割膠帶1〇“在 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 1 311478 473945
經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 制 五、發明說明( 此狀態之下,以研磨機109研削非活性表面1〇2側,亦即 進行背面研削(back grinding)。此背面研削係進行至磨到切 割溝槽103為止。以背面研削到切割溝槽1〇3出現時,則 可獲得厚度約50μιη之半導體晶片之個片11〇(如第9(:圖所 示)。 如此,則可於切割時不致產生破裂或缺角,而可製成 薄型化之半導體晶片11〇。 如此製成之半導體晶片,之後將裝載到安裝基板上。 並經由與外部端子之連接及樹脂鑄模等步驟,即可完成半 導體裝置(集成電路元件)。 但·,經由薄复J匕之半導體晶片11〇,於搬運中,仍有 可能產生t裂巍^角。例如,對於安裝載,係以 機器人自動氣行之。然而,因為以機器器手把持時 等所施加之外力,可能使得薄型半導體晶片11〇產生破裂 或於角部容易形成缺角。 因此,上述之先行技術,雖可防止於切割時之晶片產 生破裂或缺角,另一方面,卻帶來於搬運中產生之破裂或 缺角之新問題。 [發明所欲解決之課題] 本發明之目的,在於提供一種半導體裝置,該裝置係 使半導體晶片於暮^過程中,不致產生缺角之構造。 本發明之另一目的,在於提供一種半導體裝置之製造 方法,使半導體晶片於製造過程中不致產生破裂或缺角。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 2 311478 -------------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂·
.P 473945 A7 五、發明說明(3 ) [用以解決課題之手段及其效果] 本發明之半導體裝置,按申請專利範圍第1項,係具 有··包括半導體晶片,及覆蓋住該半導體晶片之側壁並具 有與上述半導體晶片之活性表面相反倒之表面,亦即與非 活性表面形成位於同一平面之表鱼之保護榭脂者。 按上述之構成,則半導體晶片之彳蓋有保護樹 脂,而此保護樹脂則具有肖+導體晶片以活性表面形成 位於同一平面之表面。 如此之半導體晶片,可以經由包括如下兩步驟之製造Ιϊ 方法製造之。亦即:將半導體晶片以至少可覆蓋住該半導 體晶片夂側壁之保護樹脂予以密封之樹脂密封步驟,以及 將與上述半導體晶片之活性表面相反側之表面,亦即非活 性表面側與,覆蓋此半導體晶片之側壁之上述保護樹脂, 同時研削或研磨之步驟β 又,上述半導體裝置,更包含有,以電性連接於上述 半導體晶片之活馋表面,而具有露出於保護樹脂外之露出 部之外部連接端子為佳。 在此情形,外部連接端子,可為接合於配線基板之焊 球等球狀端子,亦可為介由搭接引線電性連接於半導體晶 片之引線框。 上述半導體裝置,更包含接合有上述半導體晶片之基 板亦可。 此構成半導體裝置可藉由在上述樹脂密封步驟之前, 追加將上述半導體晶片接合於基板之晶片接合步驟之製造 311478 I紙張尺度適財國國家標準(CNS)A4規格(21G χ 297公爱) 47394 A7 五、發明說明(4 ) 方法而製成。 在此情形,上述半導體晶片,係以活性表面面向上述 基板之狀態接合於該基板亦可。在此情形,於上述晶片接 σ步驟中’上述半導體晶片係以其活性表面面向上述基板 之狀態接合於該基板。以此構成時,半導體晶片,係形成 所謂面朝下之狀態接合於基板。因而,半導體晶片之活性 表面形成被基板保護之狀態。 再者’上述基板為引線框亦可。在此情形,於上述晶 片接合步驟中,上述半導體晶片,係以非活性表面面向上 述引線框之狀態接合於該引線框為佳。而且,上述方法, 係在上洚樹脂密封步驟之前,再追加將上述引線框之預定 處與上述半導體晶片之活性表面之預定處,以搭接引線連 接之連接步驟為佳。而於上述樹脂密封步驟之中,將上述 半導體晶片之活性表面及上述搭接引線一起加以樹脂密封 為佳。再者,於上述研削工程之中,在研削上述半導體晶 片之非活性表面側之前,先行研削上述引線框之位於上述 非活性表面側之部分為佳。在此情形,半導體晶片之活性 表面,形成被保護樹脂保護之狀態。 例如’於晶片接合步驟,係將較厚之半導體晶圓⑽ 如,300至700flm.)切割所獲得之半導體晶片之個片接合 於基板。由如此厚之半導體晶圓切割半導體晶片之個片: 係屬容易,且不致產生半導體晶片之破裂或缺角。而且, 由如此厚之半導體晶圓所取出之厚半導體晶片,在以機器 人等進行搬運時,不致產生破裂或缺角。 I紙張尺度適用中咖織格⑵〇 χ挪公爱) 4 311478 --------------裝--- (請先閱讀背面之注音?事項再填寫本頁) 訂· I— n- n flu , 473945
473945 A7 __B7 五、發明說明(6 曰曰 或,上述基板為另外之半導體晶片,而全體則形成母子 片構造(chip on chip)之半導體裝置亦可。 採用母子晶片構造時,係在成為基座之母晶片上面, 將複數個子晶片以面向下的方式與其接合,並對於該複數 個子片同時進行保護樹腊及非活性表面側之研削,而具 有可使子晶片之表面高度形成均一之優點。 又半導體片對於基板之接合,可透過例如金等之 隆起物進行亦可。 本發明之半導體裝置,按申請專利範圍第2項,係包 括·基板5,以其活性表面面向此基板之狀態而接合於該 基板,典路出與上述活性表面相反側之表面,亦即非活性 表面之半導體晶片者。 在此情形,設有覆蓋基板側壁之保護樹脂亦可,無如 此之保護樹脂亦可。於最終產品之形態中,基板之非活性 表面,係不為保護樹脂等所覆蓋,而係露出於外部。但, 形成於與基板相面向之活性表面側表層領域之元件,所可 能受到來自外部之影響則可不必考慮。活性表面因與基板 相面向而受到保護。然而,如有必要,可在活性表面與基 板之間填充樹脂填充劑,則形成於活性表面側表層領域之 元件,將可獲得充分之保護。 上述半導體晶片,經由對於非活性表面之研磨或研削 處理,而成為薄型化為佳(薄型化至1〇〇μπι至2〇〇μπι之厚 度為佳)。 如此之半導體裝置,係可以經由包括:在基板上將半 W尺細中_標準(CNS)A4規格⑽χ 297 € 6 3麵 47394 A7
導體晶片’以該半導體晶片之活性表面面向基板而接合之 五、發明說明(, 晶片接合步驟與,將與上述半導體晶片之活性表面相反侧 (請先閱讀背面之注意事項再填寫本頁) 之表面,亦即非活性表面側研削或研磨之研削步驟之製造 方法而製成者。 在此障形,有關半導體晶片之樹脂密封,可做亦可不 做。研削步驟,係於半導體晶片即使不進行樹脂密封之狀 態下,亦可無問題地實行。省卻樹脂密封步驟,可使製造 步驟顯著簡化,所以,可降低生產成本,並提昇生產效率。 但’為保護半導體晶片之活性表面,則再包含,在半 導體晶片之活性表面與基板間之空隙注入樹脂填充劑之步 驟為佳。 又’於上述晶片接合步驟中,係在上述基板接合複數 個半導體晶片,而於上述研削步驟中,係將上述複數之半 導體晶片同時進行研削亦可。 在此情形’於上述研削步驟之後,再追加將上述基板 切割’以切割出包括預定個數之半導體晶片之半導體裝置 個片之切割步驟為佳。 經濟部智慧財產局員工消費合作社印製 如此’則可一次製造出複數個半導體裝置。 本發明有關上述或再其他之目的、特徵及效果,可參 照添附圖面並以下述實施例之說明而更加明確。 [實施例] 第1A圖至第1E圖,係將本發明之第1實施例有關半 導體裝置之裝配步驟,按步驟次序顯示冬剖視圖。第1A 圖’係顯示半導體晶片接合步驟。於聚醯亞胺基板等做成 本紙張尺度辆中國國家標準(CNS)A4規格⑵〇 χ 297公爱) 7 311478 473945 A7 . - -- --~____ 五、發明說明(8 ) ' 之基板1上面,以例如銅箔刻蝕法等預先形成有電路圖 案。且該基板1上,有複數之半導體晶片C以面朝下的方 式與之接合。亦即,半導體晶片c係使電晶體或電阻等元 件所形成之活性表層領域側之表面,亦即活性表面u面向 基板1之狀態,並透過隆起物(bump)2接合於基板丨,電性 連接於形成在基板1之電路圖案。 接合於基板1之半導體晶片C,具有較厚之厚度,例 如,300至700μπι左右之厚度。如此之半導體晶片c,可 將300至700μιη厚之半導體晶圓(未圖示)以切割機(dicing saw)切割而獲得。如此夠厚之晶圓,於切割步驟中不致於 產生破裂或缺角。而且,經此切割步驟所獲得之厚半導體 片C’在其後之為接合於基板1之搬運中,亦無虞產生 破裂或缺角。 半導體晶片C接合於基板1之後,可按需要,在活性 表面11與基板1間之空隙,注入液狀樹脂3(底填充劑 (under fill)) ° 第1B圖顯示,緊接半導體晶片接合步驟之後進行之 樹脂密封步驟。在此樹脂密封步驟中,係使用形成有可一 併收容接合於基板1之複數個半導體晶片C之鑄模槽之模 具(未圖示)。使用此模具,可以樹脂5將基板1上之複數 半導體晶片C 一併予以密封。於是,各半導體晶片c之側 壁12與,活性表面11之相反側之非活性表面13會被樹脂 5所覆蓋。且,活性表面11與基板1間之空隙之側方,亦 為樹脂5所密封,如此而可保護活性表面丨i。 --------ill,裝 i — (請先閱讀背面之注意事項再填寫本頁) 訂* * 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐) 8 311478 473945 , A7
473945 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明(l〇 ) 在如此之基板1之背面側,可利用印刷將焊球7轉印 在孔16之位置。並按需要施以倒流,使構成焊球7之一部 分焊料熔流入孔1 6内,使之與導體圖案1 5及1 7相接合。 如此而可獲得,如第1E圖所示之球型柵陣列(Bau Grid Array,BGA)型半導體裝置。 由孔16之内壁直到基板1之背面所形成之導體圖案 1 7得以省略,即使無該導體圖案1 7,亦可形成接合於導體 圖案15之良好焊球7。 當然,如第1D圖所示’以無外部端子之台型柵陣列 (Land Grid Airay ’ LGA)型半導體裝置,做為完成品亦可。 如Λ所述,按本實施例,半導體晶片c係由厚晶圓分 割’而後’將厚半導體晶片C安裝於基板1,再施以樹脂 密封之後進行研削,使半導體晶片C薄型化。所以,無虞 於切割時產生破裂或缺角,或於搬運中產生破裂或缺角。 而且’切割成半導體裝置個片時,係於樹脂5保護住薄半 導體晶片C之狀態下進行’所以半導體晶片c於該切割步 驟亦不致於受到損傷。 而且,最後所獲得之半導體裝置,在半導體晶片C之 側壁之整個周圍均由樹脂5所覆蓋住。再者,半導體晶片 C之非活性表面13與樹脂5之表面係在同一平面上,且半 導體晶片C之角部不會外露。因而,即使於後來之搬運時, 亦可藉由樹脂5保護住半導體晶片c。如此,半導體晶片 C就不會產生破裂或缺角,而得以製造超薄型之半導體装 置。 ----------—.—裝— (請先閱讀背面之注意事項再填寫本頁) 訂· %· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 10 311478 47394; Α7 五、發明說明(Π ) s外’半導體晶片c之非活性表面13雖形成外露, 但半導體晶片C之活性表面u係面向基板卜且半導體晶 片c之側壁係由樹脂5覆蓋住,所以,半導體晶片c之活 性表層領域可獲得充分之保護。 第3A圖至帛3E圖,係將本發明之第2實施例有關半 導體裝置之裝配步驟’按步辣次序顯示之剖視圖。該第3八 圖至第3E圖之中,與上述第1A圖至第圖所示各部相 對應之各部,以與第1A圖至第1E圖相同之參照符號顯 示。 於上述實施例1,係將複數之半導體晶片c 一併加以 樹脂鑄樺(請參見第1A圖)。然而,本第2實施例,係以形 成有對應於各個半導體晶片C之鑄模槽21之複數模具 2〇,各別進行各個半導體晶片c之樹脂鑄模(第3八圖、第 3B圖此時之切割線D,係設定於各個樹脂鑄模體間之 位置。因而,鑄膜樹脂5並不會被切割,而係僅切割基板 * 經濟部智慧財產局員"工消•費合作社印製 樹脂密封步驟之後,係待樹脂5硬化後,在切割基板 1之前,先進行研削步驟(第3C圖)。亦即,使用研磨機等, 將樹脂及半導體晶片c之非活性表面丨3側,研削到研削 目標厚度τ為止(參照第3B圖)。 經切割步驟切割成個片之半導體裝置(第3D圖),可按 需要’施加外部端子形成步驟(第3Ε圖),以設置例如由焊 球7所形成之外部端子。 第4Α圖及第4Β圖,係將本發明之第3實施例有關半 本紙艾過用肀國國家標準(CNS)A4規格(21〇 χ 公釐) - JH478 473945 A7 B7 五、發明說明(I2 ) 導體裝置之裝配步驟,按步驟次序顯示之剖視圖。第4A 圖及第4B圖之中,與上述第1A圖至第1E圖所示各部相 對應之各部,以與第1A圖至第1E圖相同之參照符號顯 示0 本實施例,亦與顯示於第3A圖至第3E圖之第2實施 例之情形相同,係將各別之半導體晶片C,分別加以樹脂 密封。但,本實施例,係以黏度較高之液狀樹脂5,滴下 於各半導體晶片C之位置,並使之硬化以進行樹脂密封。 亦即,不需用到模具,而可完成樹脂密封步驟(第4A圖)。
樹脂密封後,係待樹脂5硬化後,如第4B圖所示, 將樹脂.5及半導體晶片c,以研磨機等同時研削到研削目 票厚度T為止(請參照第4A圖)。 其後之步驟,則與第3D圖及第3E圖之步驟相同。 第5A圖及第5B圖,係將本發明之第4實施例有關半 導體裝置之裝配步驟,以步驟次序顯示之剖視圖。第5a 圖及第5B圖中,與上述第4A圖及第4B圖所示各部相對 應之各部’以與第4A圖及第4B圖相同之參照符號顯示。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 本實施例,係於樹脂密封步驟(第5A圖),使液狀樹脂· 5僅附著於半導體晶片c之側壁12之部分並使之硬化。於 是,於後來之研削步驟中(第5B圖),將樹脂5及半導體晶 片C之非活性表面13同時研削時,因樹脂5之研削量減 少,而可縮短研削步驟所需之時間。 第1至第4實施例,皆係使半導體晶片c之至少側壁 部之整個周圍由樹脂5所密封,並同時研削該樹脂5與半 311478 -----------------β-裝—— (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國豕標準(CNS)A4規格(210 X 297公爱) 一 47394! B7 五、發明說明(I3 ) 導體曰曰片C之非活性表面側。因而可獲得一種半導體晶片 c與’覆蓋住該半導體曰Η Γ也丨辟 丁守膝曰曰片C側壁12之整個周圍之樹脂5 表面5a係形成位於同一平面之狀態之裝置。 第6A圖至第6C g ’係將本發明之第5實施例有關半 導體裝置之裝配步驟,按步驟次序所顯示之剖視圖。第6A 圖至第6C圖令’與上述第1A圖至第1E[g所示各部相對 應之各部,以相同之參照符號顯示,而省略重覆說明。 本實施例之中,係裝配所謂母子晶片構造之半導體裝 置。、亦即’於聚酿亞胺等所形成之基板i上面,晶粒黏接|賣 有成為基座之母半導艎晶片Cm。亦即,母半導體晶片匸爪, 係以非丨舌性表面32面向基板}之狀態與之接合。而預定個 數(1個亦可,複數個亦可)之子半導體晶片Cd,則係以面 朝下的方式接合於該母半導體晶片Cm之活性表面31。亦 P子半導體曰曰片Cd係以活性表面11面向母半導體晶片 Cm之活性表面31之狀態,接合於該母半導體晶片匸㈤。 更具體的說,母半導體晶片Cm及子半導體晶片Cd, 各具有晶片間連接用之墊部(未圖示)。此晶片間連接用塾 部之間’則係以金等耐氧化性金屬所形成之隆起物2互相 連接。如此之隆起物2,只要設置於母半導體晶片Cm或 子半導體晶片Cd之至少一方,即可接合Cm、Cd兩晶片。 於母半導體晶片Cm之活性表面31靠近邊緣部之位 置’又設置有外部連接用之墊部Pe。此墊部pe,係以搭接 引線35連接到形成於基板1上之電路圖案33。 311478 訂 線 如此,此母子晶片構造之半導體裝置係以在接合於基 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 4^3945
BQ 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(I4 ) 板1之母半導體晶片Cm上接合子半導體晶片Cd,且,母 半導體晶片Cm與基板丨以引線搭接而連接之狀態下,由 密封樹脂5所密封。該樹脂密封後之狀態,亦於第6 A圖。 該樹脂密封步驟之後,係待樹脂5硬化後,以研磨機 等研削樹脂5,使子半導體晶片cd之非活性表面13露出。 接著,再將樹脂5及子半導體晶片Cd之非活性表面13側 同時研削。如此,直至設定成不到搭接引線35之研削目標 厚度τ為止,以進行樹脂5及子半導體晶片Cd之研削(第 6B 圖)。 接著,以例如切割機,沿著切割線D ,切割出母子— 片構造冬半導體裝置之個片(第6(:圖)。隨後,可按需要, 在基板1之下面(與母半導體晶片Cm之接合面相反側之 面),進行連接嬋球7等外部端子之外部端子形成步驟。此 焊球7附近之構成,與顯示於第2圖之構造大致相同。 如上所述,於本實施例,係將子半導體晶片cd予以 樹脂密封,然後,將密封樹脂5與子半導體晶片cd之非 活性表面13側同時研削。如此可獲得一種由具有與子半導 體晶片Cd之非活性表面13位於同一平面之表面&之密 封樹脂5 ’將子半導體晶片Cd之侧壁12整個周圍覆蓋住 之狀態之半導趙裝置。且,於本實施例,安裝於母半導體 晶片Cm上之複數個子半導體晶片Cd係被共同研削。因 而,具有可使此等複數個子半導體晶片Cd之高度相等之 優點。 再者,於本實施例之母子晶片構造之半導體裝置之裝
木紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公t I 14 311478 (請先閱讀背面之注意事項再填寫本頁)
473945 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(15 ) 配,亦可適用上述第3A圖至第3E圖,第4A圖及第4β 圖或第5A圖及第5B圖所顯示之樹脂密封方法。 第7A圖至第7D圖,係將本發明之第6實施例有關半 導體裝置之裝配步驟,按步驟次序顯示之剖視圖。該第7A 圖至第7D圖中,與上述第1A圖至第1£圖所示各部相對 應之各部,以與第1A圖至第1E圖相同之符號顯示。 本實施例,係採用基板之另一形態之引線框5〇。引線 框50具有:為安置半導體晶片c之島部51及,為連接外 邛之導引部52(外部連接端子)。於第7A圖所示之晶片接 合步驟,係將半導體晶片C晶粒黏接於島部5丨。此時,使 半導體·晶片C之非活性表面丨3,面向島部5丨。其次,以 搭接引線55連接設在半導體晶片c之活性表面u之墊部 (未圖示)與導引部52。 ° 於此狀癌’如第7B圖所示(係將第7 A圖上下反轉之 圖),以密封樹脂5將半導體晶片c予以密封。此時,密封 樹脂5係將半導體晶片c之側壁12、活性表面u及搭接 引線55 —併予以密封,而僅露出引線框5〇之導引部 之一部分於外部。 接著,進行如第7C圖之研削步驟。亦即,以研磨機 研削到第7B圖所示之研削目標厚度τ為止。此研削步驟 之初期,係僅研削樹脂5。其次,同時研削樹脂5及弓I線 框50之島部51(面向半導體晶片c之非活性表面13側之 部分)。接著,將樹脂5、引線框5〇及半導體晶片c之非 活性表面側13同時研削。經如上所述之步驟,樹脂5會覆 +¾¾ (CNS)A4 ^ (210,297 ^ ) 15 311478 ^--------^---------線 (請先閱讀背面之注意事項再填寫本頁) 473945 A7 五、發明說明(16 ) 蓋住半導體晶片c之側壁12,且具有與該半導禮晶片c 之非活性表面13位於同一平面之表面5a。 接著,例如以切割機’沿著第7 C圖之切割線d,進 行切割樹脂5及引線框50之切割步驟,便可獲得第7〇圖 所示之半導體裝置之個片。 如上所述,按本實施例,係在半導體晶片不致產生破 裂或缺角之情況下,製成具有以引線框為外部連接端子之 薄型半導體裝置。 第8A圖至第8D圖,係將本發明之第7實施例有關半 導體裝置之裝配步驟,按步驟次序顯示之剖視圖。該第8八 圖至第.8D圖令,與上述第1A圖至第ιέ圖所示各部相對 應之部分,以相同符號顯示。 本實施例之特徵在於,省卻了利用樹脂5密封半導體 晶片C之步驟(參照第1A圖至第1E圖)之點。 亦即,如第8A圖所示,複數之半導體晶片c,係以 電晶體或電阻等元件所形成之活性表層領域側之表面,亦 即活性表面11面向基板1之狀態(亦即,面朝下之狀離), 透過隆起物2接合於基板丨,並以電性連接於形成在基板、 之電路圖案上。 在半導體晶片C接合於基板丨之後,於活性表面u 與基板1間之空間注入液狀樹脂3(底填充劑)。藉此,以保 護形成於活性表面11側之表層領域之元件。 接著,在未將半導體晶片c予以樹脂密封之狀態下, 對基板1上之複數半導體晶片c之非活性表面丨3進行研 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公楚) ' ........— 16 311478 ---------------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂: 經濟部智慧財產局員工消費合作社印製 A7 --------— B7__ 五、發明說明(Π )
削步驟。按本案發明者之研究得知即使未將半導體晶片C 予以樹知在封’亦可毫無問題地進行非活性表面〗3之研削 步驟。 於本研削步驟,係以研磨機,將半導體晶片c之非活 性表面13御!,研削到第8Affl中以二點虛線所示之研削目 標厚度T為止。研削目標厚度T係例如使研削後之半導體 晶片C之厚度t設定成為1〇〇至2〇〇μιη左右。 接著,例如以切割機,沿著設定於半導體晶片c彼此 間之切割線D切割基板J,則如第8C圖所示,切割出半 導體裝置之個片。 其後,可按需要,如第8D圖所示,基板丨之與半導 體晶片C側之相反侧形成焊球7。於此最終形態之半導體 晶片C,不但其非活性表面13,即連其側壁12, 樹脂密封。 如上所說,按本實施例,由於不需要進行半導體晶片 C之樹脂密封,所以可使半導體裝置之製造步驟顯著簡 化。於是,不但可降低生產成本,且可顯著提昇生產性。 經濟部智慧財產局員工消費合作社印製 以上,說明了本發明之7個實施例,但本發明亦可以 其他形態實施。例如,上述之第2、第3或第4之實施例, 係將各個半導體晶片C分別予以樹脂鑄模,但將半導體晶 片C分成2至3個為一組(亦即,預定之複數個分成_組), 再將各組之複數個半導體晶片一併予以樹脂鑄模亦可。 再者,以上述第2、第3或第4實施例之步驟,如第 3D圖中之符號60所示,基板1會突出於密封樹脂5之外。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 17 311478 47394: 五、發明說明(is ) (請先閱讀背面之注意事項再填寫本頁) 如此亦無太大問題’但如因基板i之突出而成問題時則 將切割線叫參照第3C圖)設定成通過樹脂5,然後沿著 此切割線D1將樹脂5及基板1切割即可。 而且,上述各實施例之研削步驟,均係進行利用研磨 機之機械式研削,但該研削步驟,亦可為使用刻姓液之化 學式研削步驟,或係如CMP(化學式機械式混合研磨)法之 化學式機械式混合研磨步驟亦可。然而,半導體晶片之非 活性表面側之研削或研磨,研削速度較研削精密度更受到 重視,所以上述3個方法之中,由提昇生產效率之觀點而 言,仍以使用研磨機之機械式研削方法為佳。 利·用研磨機之機械式研削法研削過之樹脂及半導體晶 片之非活性表面,或許存有一道道之研削痕跡,但此痕跡, 可按需要,以浸蝕等化學方法消除。 另,於上述之實施例,係於為切割出半導體裝置個片 之切割步驟中’使用切割機,但,採用例如以雷射光切割 等之其他切割方法亦可。 以上對於本發明之實施例做了詳細說明,但此等只不 過是為闡明本發明之技術内容所採用之具體例而已,本發 明並非僅限定於此等具體例以為解釋,而本發明之精神及 範圍’僅能以本案申請專利範圍而限定。 本申睛案,係根據1999年6月7曰向日本國特許廳所 申請之特願平11-160066號,及1999年8月31日同樣向 曰本國特許廳所申請之特願平1 1-245854號,並主張依條 約之優先權,而此等申請案之全部内容,以茲此引用而包 i 473945 經 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 五、發明說明(I9 括在内。 [圖面之簡單說明] 第1Α圖至第1Ε圖,係將本發明第i實施例有關半導 趙裝置之裝配步驟,按步驟次序所顯示之剖視圖。 第2圖,係將焊球附近之構成予以擴大顯示之剖視 圖。 第3 A圖至第3E圖,係將本發明第2實施例有關半導 體裝置之裝配步驟,按步驟次序所顯示之剖視圖。 第4A圖及第4B圖,係將本發明第3實施例有關半導 體裝置之裝配步驟,按步驟次序所顯示之剖視圖。 第·5A圖及第5B圖,係將本發明第4實施例有關半導 體裝置之裝配步驟,按步驟次序所顯示之剖視圖。 第6A圖至第6C圖,係將本發明第5實施例有關半導 體裝置之裝配步驟,按步驟次序所顯示之剖視圖。 第7 A圖至第7D圖,係將本發明第6實施例有關半導 體裝置之裝配步驟,按步驟次序所顯示之剖視圖。 第8A圖至第8D圖,係將本發明第7實施例有關半導 體裝置之裝配步驟,按步驟次序所顯示之剖視圖。 第9A圖至第9C圖,係為說明先行技術之薄型半導體 裝置之製造步驟之剖視圖。 [符號之說明] 1 基板 3 液狀樹脂 2 5 5a 表面 隆起物 鑄模樹脂 焊球
Μ--------^---------線 (請先閱讀背面之注意事項再填寫本頁) 473945 A7 B7 五、發明說明(20 ) 經濟部智慧財產局員工消費合作社印製 11 活性表面 12 側壁 13 非活性表面 15 導體圖案 16 孔 17 導體圖案 20 模具 21 鑄模槽 31 活性表面 32 非活性表面 33 電路圖案 35 搭接引線 50 引導框 51 島部 52 導引部 55 搭接引線 60 基板之突出部 100 晶圓 101 活性表面 102 非活性表面 103 切割溝槽 « 105 切割膠帶 106 切割膠帶 107 切割機 109 研磨機 110 半導體晶片個片 C 半導體晶片 Cd 子半導體晶片 Cm 母半導體晶片 D 切割線 D1 切割線 Pe 墊部 T 研削目標厚度 t 厚度 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 20 311478
Claims (1)
- 473945 六、申請專利範圍 導:體裝置’係包括:半導體晶片、及覆蓋住該半 導體S曰片之側壁,並具有與上述半導體晶片之 相反側之表面,亦即非活性表面形成 面之保護樹脂者。 表 2·如申請專利範圍第!項之半導體裝置,其中,: 電性連接於上述半導體S , … 牛導體曰曰片之活性表面,並具有露出於 0 上述保護樹脂外之露出部之外部連接端子。 3·如申請專利範圍第^項之半導體裝置,其中,復包括· 接合於上述半導體晶片之基板。 匕· (如申請專利範圍第3項之半導體裝置,其中,上述半導 體晶片,係以活性表面面向上述基板 甘 > 丨_ 孜之狀恶而接合於該 暴扳。 5. 一種半導體裝ft包括:基板、及以活性表面面向該基 板之狀^接_該基板,並露出與上述活性表面相反 側之表面,亦即非活性表面之半導體晶片者。 6·如申請專利範圍第3項至第5項任何一項之半導體裝 置,其中,上述基板係形成有電路圖案之配線基板。 7·如申請專利範圍第3項至第5項任何一項之半導體裝 置,其令,上述基板係其他半導體晶片,而全體則形成 母子晶片構成。 8. —種半導體裝置之製造方法,係包括··將半導體晶片, 以至少覆蓋住該半導體晶片之側壁之保護樹脂密封之 樹脂密封步驟;以及將與上述半導體晶片之活性表面相 1 &側之表面’亦即非活性表面側與,覆蓋住該半導體晶 311478 線 本紙張尺度適用中國國家標準(CNS)A4規格咖x 297公爱)_ 473945 A8 B8 C8 D8 六、申請專利範圍 片之側壁之上述保護樹脂,同時研削或研磨$,研削步 驟者。 9·如申請專利範圍第8項之半導體裝置之製造方法,其 中,在上述樹脂密封步驟之前,復包括,將上述半導體 晶片接合於基板之晶片接合步驟。 10.如申請專利範圍第9項之半導體裝置之製造方法,其 中’上述晶片接合步驟之中,上述半導體晶片係將其活 性表面以面向上述基板之狀態而接合於該基板。 11·如申請專利範圍第9項之半導體裝置之製造方法,其 中’上述基板為引線框; 上述晶片接合步驟中,上述半導體晶片係以非活性 表面面向上述引線框之狀態而接合於該引線框;在上述樹脂密封步驟之前,復包括丨,將上述引線框 之預定處與上述半導體晶片之活性表面〈之、預定處,以搭 接引線連接之連接步驟; 上述樹脂密封步驟之中,係將上述半導體晶片之活 性表面及上述搭接引線一併樹脂密封;以及 上述研削步驟之中,係於研削上述半導體晶片之非 活性表面側之前,先研削上述引線框之位於上述非活性 表面側之部分。 12.如申請專利範圍第9項至第丨丨項任何一項之半導體裝 置之製造方法,其中’上述晶片接合步驟之,,有複數 個半導體晶片接合於上述基板; __上述樹脂密封步驟之中,上述基板上之複數個丰導 ;張尺度樹嶋標準(CNS)A^7iI^fi^7 22 311478 (請先閱讀背面之注意事項再填寫本頁) ,裝 ----訂----- 、· n n < 經濟部智慧財產局員工消費合作社印製 473945 &8 C8 -----~_______ 六、申請專利範圍 ^—" —— - 體晶片’係為樹脂所密封; 上述研削步驟,係就上述複數之半導體晶片同時進 行;以及 在上述研削步驟之後,復包括,切割出含有預定個 數之半導體晶片之半導體裝置個片之切割步驟。 13.如申請專利範圍第12項之半導體裝置之製造方法,其 中,上述切割步驟包括,將上述保護樹脂與上述基板同 時切割之步驟。 14·-種半導體裝置之製造方法,係包括,在基板上,將半 導體晶片以該半導體晶片之活性表面面向上述基板之 狀二而接〇之阳片接合步驟,以及將與上述半導體晶片 之活性表面相反側之表面,亦即非活性表面側研削或研 磨之研削步驟者。 15·如申請專利範圍第14項之半導體裝置之製造方法,其 中,上述晶片接合步驟之中,有複數個半導體晶片接合 於上述基板; 上述研削步驟,係就上述複數之半導體晶片同時進 行;以及 在上述研削步驟之後,復包括,將由切割上述基 板,以切割出含有預定個數之半導體晶片之半導體裝置 個片之切割步驟。 ^--------^---------^ (請先閱讀背面之注意事項再填寫本頁)23 311478
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JP3882738B2 (ja) * | 2002-10-24 | 2007-02-21 | ソニー株式会社 | 複合チップモジュール及びその製造方法、並びに複合チップユニット及びその製造方法 |
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1999
- 1999-08-31 JP JP24585499A patent/JP3339838B2/ja not_active Expired - Fee Related
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2000
- 2000-05-25 TW TW89110099A patent/TW473945B/zh not_active IP Right Cessation
- 2000-06-02 KR KR20000030538A patent/KR100665777B1/ko not_active IP Right Cessation
- 2000-06-07 US US09/588,628 patent/US6870248B1/en not_active Expired - Lifetime
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2005
- 2005-02-10 US US11/053,892 patent/US7262490B2/en not_active Expired - Lifetime
- 2005-02-10 US US11/053,934 patent/US7138298B2/en not_active Expired - Lifetime
- 2005-02-10 US US11/053,933 patent/US7339264B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI426542B (zh) * | 2004-06-04 | 2014-02-11 | Kamiyacho Ip Holdings | 三維積層構造之半導體裝置及其製造方法 |
Also Published As
Publication number | Publication date |
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US20050146055A1 (en) | 2005-07-07 |
US20050146032A1 (en) | 2005-07-07 |
US20050146056A1 (en) | 2005-07-07 |
JP3339838B2 (ja) | 2002-10-28 |
JP2001057404A (ja) | 2001-02-27 |
US7262490B2 (en) | 2007-08-28 |
US7138298B2 (en) | 2006-11-21 |
KR100665777B1 (ko) | 2007-01-09 |
US6870248B1 (en) | 2005-03-22 |
US7339264B2 (en) | 2008-03-04 |
KR20010049481A (ko) | 2001-06-15 |
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