TWI634628B - 具有支撐構件之堆疊式半導體晶粒組件及相關之系統及方法 - Google Patents

具有支撐構件之堆疊式半導體晶粒組件及相關之系統及方法 Download PDF

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TWI634628B
TWI634628B TW104113105A TW104113105A TWI634628B TW I634628 B TWI634628 B TW I634628B TW 104113105 A TW104113105 A TW 104113105A TW 104113105 A TW104113105 A TW 104113105A TW I634628 B TWI634628 B TW I634628B
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die
semiconductor die
semiconductor
memory
package substrate
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TW104113105A
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TW201603211A (zh
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黃宏遠
勝錦 倪
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美光科技公司
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

本文揭示具有支撐構件之堆疊式半導體晶粒總成及相關之系統與方法。在一項實施例中，一半導體晶粒總成可包含一封裝基板、經附著至該封裝基板之一第一半導體晶粒及亦經附著至該封裝基板之複數個支撐構件。該複數個支撐構件可包含經安置於該第一半導體晶粒之相對側處之一第一支撐構件及一第二支撐構件，且一第二半導體晶粒可經耦合至該等支撐構件，使得該第二半導體晶粒之至少一部分係在該第一半導體晶粒上方。

Description

具有支撐構件之堆疊式半導體晶粒組件及相關之系統及方法
所揭示之實施例係關於半導體晶粒總成及支撐此等總成內之構件。在若干實施例中，本技術係關於可包含一控制器晶粒及承載於控制器晶粒上方之記憶體晶粒之晶粒總成。
封裝式半導體晶粒(包含記憶體晶片、微處理器晶片及成像器晶片)可包含安裝至一封裝基板上之半導體晶粒。半導體晶粒經圍封於一塑膠保護蓋中，且各晶粒包含功能特徵部，諸如記憶體單元、處理器電路及成像器裝置。晶粒上之焊墊在封裝基板上之功能特徵部與終端之間電連接，其等容許晶粒經連接至外部電路。
為增加一封裝內晶粒之密度，晶粒可在外殼內經堆疊於彼此上。然而，垂直堆疊式晶粒之一個挑戰在於晶粒可具有不同大小或覆蓋區。舉例而言，在一記憶體封裝中，一記憶體控制器晶粒可具有小於封裝內之記憶體晶粒之一覆蓋區。記憶體控制器晶粒可係更難線接合，因為其自記憶體晶粒偏移。同樣地，記憶體晶粒有時可當堆疊於更小之記憶體控制器晶粒上時傾斜。
100‧‧‧半導體晶粒總成
102‧‧‧封裝基板
103‧‧‧控制器晶粒
104‧‧‧電連接器
105a‧‧‧第一側
105b‧‧‧第二側
106‧‧‧記憶體晶粒
106a‧‧‧第一記憶體晶粒
106b‧‧‧第二記憶體晶粒
107‧‧‧覆蓋區
108a‧‧‧第一焊墊
108b‧‧‧第二焊墊
109a‧‧‧焊墊
109b‧‧‧焊墊
111a‧‧‧第一線接合
111b‧‧‧第二線接合
112‧‧‧線部分
113‧‧‧封裝接觸件
114‧‧‧互連線
115‧‧‧封裝外殼
116‧‧‧囊封劑
118‧‧‧腔
130‧‧‧支撐構件
130a‧‧‧第一支撐構件
130b‧‧‧第二支撐構件
140‧‧‧晶粒附著材料
141a‧‧‧晶粒附著材料
141b‧‧‧晶粒附著材料
142‧‧‧晶粒附著材料
143‧‧‧薄膜覆線材料
220‧‧‧半導體晶圓
221‧‧‧切割線
223‧‧‧邊緣部分
230‧‧‧支撐構件
240‧‧‧晶粒附著材料
400‧‧‧半導體晶粒總成
406‧‧‧記憶體晶粒
409‧‧‧焊墊
411‧‧‧線接合
440‧‧‧晶粒附著材料
500‧‧‧半導體晶粒總成
508‧‧‧焊墊
550‧‧‧電容器
600a‧‧‧半導體晶粒總成
600b‧‧‧半導體晶粒總成
630‧‧‧第三支撐構件
635‧‧‧支撐構件
700‧‧‧半導體晶粒總成
790‧‧‧系統
792‧‧‧電源
794‧‧‧驅動器
796‧‧‧處理器
798‧‧‧子系統或組件
G1‧‧‧間隙
G2‧‧‧間隙
圖1A係根據本技術之一實施例組態之一半導體晶粒總成之一橫 截面視圖，且圖1B係圖1A之總成之一俯視平面圖，其中一外殼及一半導體晶粒堆疊自總成移除。
圖2係根據本技術之一實施例已經分裂以形成半導體晶粒總成之支撐構件之一半導體晶圓之一俯視平面圖。
圖3A至圖3C係繪示根據本技術之一實施例在各種製造階段之圖1A之半導體晶粒總成之橫截面視圖。
圖4係根據本技術之另一實施例組態之一半導體晶粒總成之一橫截面視圖。
圖5係根據本技術之另一實施例組態之一半導體晶粒總成之一俯視平面圖。
圖6A及圖6B係繪示根據本技術之若干實施例組態之半導體晶粒總成之俯視平面圖。
圖7係包含根據本技術之實施例組態之一半導體晶粒總成之一系統之一示意性視圖。
下文描述具有間隔件支撐構件之堆疊式半導體晶粒總成及相關之系統及方法之若干實施例之特定細節。術語「半導體晶粒」大體指稱具有積體電路或組件、資料儲存元件、處理組件及/或在半導體基板上製造之其他特徵部之一晶粒。舉例而言，半導體晶粒可包含積體電路記憶體及/或邏輯電路。半導體晶粒及/或半導體晶粒封裝中之其他特徵部據說若兩個結構透過熱量交換能量時可彼此「熱接觸」。熟習相關技術者亦將理解，本技術可具有額外實施例，且可在無下文參考圖1至圖7描述之實施例之若干細節的情況下實踐本技術。
如本文使用，有鑒於圖中展示之定向，術語「垂直」、「側向」、「上部」及「下部」可指稱半導體晶粒總成中之特徵部之相對方向或位置。舉例而言，「上部」或「最上部」可指稱比另一特徵部定位更 靠近一頁之頂部之一特徵部。然而，此等術語應廣泛地理解以包含具有其他定向(諸如在其等側上翻轉或反相)之半導體裝置。
圖1A係根據本技術之一實施例組態之一半導體晶粒總成100(「總成100」)之一橫截面視圖。如展示，總成100包含承載一半導體晶粒(或控制器晶粒103)之一封裝基板102，及在控制器晶粒103之相對側上之第一支撐構件130a及第二支撐構件130b(統稱為「支撐構件130」)。支撐構件130承載在控制器晶粒103上方以一堆疊配置之半導體晶粒(或第一記憶體晶粒106a及第二記憶體晶粒106b(統稱為「記憶體晶粒106」))。封裝基板102包含在第一記憶體晶粒106a之覆蓋區內(例如，直接在其下方)之複數個第一焊墊108a及在第一記憶體晶粒106a之覆蓋區外側(例如，不直接在其下方)之複數個第二焊墊108b。第一焊墊108a係藉由第一線接合111a耦合至控制器晶粒103上之對應焊墊109a，且第二焊墊108b係藉由第二線接合111b耦合至記憶體晶粒106之各者上之對應焊墊109b。封裝基板102可包含(例如)一印刷電路板或具有電連接器104(示意性展示)(諸如金屬跡線、導通孔、或其他適當連接器)之其他適當基板。電連接器104可經由在封裝基板102之相對側處的封裝接觸件113及互連線114(例如，焊料凸塊)將第一焊墊108a及/或第二焊墊108b耦合至外部電路(未展示)。在若干實施例中，電連接器104亦可將個別第一焊墊108a與個別第二焊墊108b耦合，以將控制器晶粒103與記憶體晶粒106相互電耦合。
總成100進一步包含由一囊封劑116構成之一封裝外殼115，囊封劑116至少部分囊封控制器晶粒103、記憶體晶粒106及支撐構件130。在所繪示之實施例中，囊封劑116亦延伸至封裝基板102與第一記憶體晶粒106a之間之一腔118中，以至少部分充填第一記憶體晶粒106a下方未由控制器晶粒103及支撐構件佔用之區。在一些實施例中，腔118 中之囊封劑116的部分可強化支撐構件130且提供第一記憶體晶粒106a下方的進一步機械支撐。囊封劑116可包含(例如)一熱固材料、一環氧樹脂或提供機械支撐、與周圍環境之屏蔽(例如，屏蔽濕度)及/或電隔離(例如，線接合之間)的其他適當化合物。
控制器晶粒103及記憶體晶粒106各可自一半導體基板(諸如矽、絕緣體上矽、化合物半導體(例如，氮化鎵)或其他適當基板)形成。半導體基板可經切割或單粒化為具有各種積體電路組件或功能特徵部之任一者之半導體晶粒，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式之積體電路裝置(包含記憶體、處理電路、成像組件)及/或其他半導體裝置。在選定實施例中，總成100可經組態為一記憶體，其中記憶體晶粒106提供資料儲存(例如，NAND晶粒)且控制器晶粒103提供記憶體控制(例如，NAND控制)。在一些實施例中，總成100可包含除控制器晶粒103及/或記憶體晶粒106之一或多者外及/或替代其等之其他半導體晶粒。舉例而言，替代兩個記憶體晶粒，總成100可包含兩個以上記憶體晶粒(例如，四個晶粒、八個晶粒等等)或僅一單一記憶體晶粒。此外，在各種實施例中，總成100之晶粒可具有不同大小。舉例而言，在一些實施例中，記憶體晶粒106之一者或兩者可延伸超越一或多個側處的支撐構件130。
如在圖1A中進一步展示，控制器晶粒103藉由一晶粒附著材料140(例如，一晶粒附著薄膜)附著至封裝基板102。第一支撐構件130a藉由一晶粒附著材料141a附著至封裝基板102，且第二支撐構件130b藉由一晶粒附著材料141b附著至封裝基板102。繼而，記憶體晶粒106藉由一晶粒附著材料142附著至控制器晶粒103及支撐構件130，且藉由一薄膜覆線材料143附著至彼此。在若干實施例中，可自相同或類似材料形成晶粒附著材料140、141a至141b及142。 在一些實施例中，可自相同或類似材料140、141a至141b及142形成薄膜覆線材料143，但薄膜覆線材料143可具有一更大厚度來容納記憶體晶粒106之間的第一線接合111a之一線部分112。在選擇之實施例中，晶粒附著材料140、141a至141b及142及薄膜覆線材料143各可包含基於環氧樹脂材料之一積層薄膜。此等積層薄膜可包含(例如)一晶粒附著薄膜或一切割晶粒附著薄膜(熟習此項技術者分別已知為「DAF」、「DDF」)。在一項實施例中，晶粒附著材料及/或薄膜覆線材料各可包含由中國上海之Henkel AG & Co.提供之DAF或DDF(例如，第Ablestick ATB-100、100U、100A、100U號模型)。
在一些習知封裝總成中，控制器晶粒可經定位於封裝基板及一記憶體晶粒堆疊之間。通常藉由使用一囊封劑囊封控制器晶粒，且接著記憶體晶粒在囊封劑之表面上堆疊而形成此組態。然而，在此階段囊封控制器晶粒之一個挑戰在於其使製造複雜。舉例而言，囊封劑上之安裝表面可係不均勻的。當記憶體晶粒經堆疊於一不均勻安裝表面上時，其等可傾側或傾斜以達到晶粒突出於保護外殼之外側之程度。同樣地，晶粒傾斜可使線接合更困難，此係因為線接合在總成之相對側處具有不同長度。另一習知製造技術涉及形成封裝基板中之一腔形成封裝基板中之一腔，控制器晶粒可經插入至該腔中。此技術亦可使製造複雜且增加成本，此係因為其需要封裝基板經研磨或蝕刻以形成腔。
根據本技術之若干實施例組態之晶粒總成之實施例可解決習知晶粒總成之此等及其他限制。舉例而言，一個優點在於記憶體晶粒106之堆疊可經安裝至支撐構件130而不必首先將控制器晶粒103囊封於記憶體晶粒106下方。一相關優點在於可消除用於囊封控制器晶粒之高溫模製及固化步驟，且因此減少熱循環。因此，製造可係較不複雜的，此係因為其可消除若干製造步驟。另一優點在於支撐構件130 可具有類似於記憶體晶粒106或與之相同之一熱膨脹係數(CTE)。舉例而言，可自半導體材料(諸如矽)形成支撐構件130。此CTE匹配在操作期間減小封裝內之熱應力。又一優點在於記憶體晶粒106並不傾向於傾斜，因為支撐構件130可具有相同高度，且可自具有一均勻厚度之一積層薄膜形成晶粒附著材料140、141a至141b及142。
圖1B係總成100之一俯視平面圖，其中為繪示之目的移除圖1A中展示之外殼115及記憶體晶粒106。如展示，控制器晶粒103經定位於在封裝基板102上疊加之記憶體晶粒106堆疊(圖1A)之一周邊或覆蓋區107(以虛線展示)內。第一支撐構件130a及第二支撐構件130b亦經定位於覆蓋區107內，且分別沿控制器晶粒103之第一側105a及第二側105b延伸。在若干實施例中，支撐構件130各可包含自一插入器基板形成之一長形構件、一印刷電路板、一半導體晶圓或晶粒或另一適當支撐材料。在下文更詳細描述之一項實施例中，支撐構件130可係自一半導體晶圓或晶粒(諸如一坯料矽晶圓或晶粒)分裂(例如，切割或單粒化)之半導體材料件。
圖2係根據本技術之一實施例之已經分裂以使用晶粒附著材料141形成支撐構件130之一半導體晶圓220之一俯視平面圖。在經繪示之實施例中，藉由首先使用一晶粒附著材料240(例如，一晶粒附著薄膜)覆蓋半導體晶圓220且接著沿多個切割線221同時切割晶圓220及晶粒附著材料240來形成支撐構件130。一旦完成切割，則支撐構件130可經由自晶粒附著材料240之各自部分形成的晶粒附著材料141附著至封裝基板102(圖1A)。在一項實施例中，可自一坯料矽晶圓形成支撐構件130。在另一實施例中，可自原本將棄置之一半導體晶圓之部分形成支撐構件。舉例而言，可自在晶粒單粒化後剩餘之半導體晶圓220之一邊緣部分223形成支撐構件230。在額外或替代實施例中，不彎曲或不運作晶粒亦可經切割為多個件以形成個別間隔件構件。
圖3A至圖3C係繪示根據本技術之一實施例在各種製造階段之總成100的橫截面視圖。首先參考圖3A，控制器晶粒103使用晶粒附著材料140附著至封裝基板102，且第一支撐構件130a及第二支撐構件130b分別使用晶粒附著材料141a及141b附著至封裝基板。在一項實施例中，晶粒附著材料140及141a至141b之一或多者可包含一壓力固定薄膜，其當經壓縮(例如，在封裝基板102與支撐構件130之各者之間)超過一臨限壓力位準時，將材料黏合在一起。在另一實施例中，晶粒附著材料140及141a至141b之一或多者可係一UV固定薄膜，其藉由曝露於UV輻射而固定。
圖3B展示在封裝基板102之第一焊墊108a與控制器晶粒103之對應焊墊109a之間形成第一線接合111a後的總成100。如展示，支撐構件130可具有大於控制器晶粒103之一第二厚度t2之一第一厚度t1。在若干實施例中，第一厚度t1及第二厚度t2可經選擇，使得當第一記憶體晶粒106a經安裝至支撐構件130時，第一線接合111a之各者之一線部分312不與晶粒附著材料142接觸。在另一實施例中，厚度t1及t2可經選擇，使得線部分312至少部分突起至晶粒附著材料142中。在任一情況中，一旦形成第一線接合111a，則第一記憶體晶粒106a可經由晶粒附著材料142附著至支撐構件130。
圖3C展示在封裝基板102之第二焊墊108b與第一記憶體晶粒106a之對應焊墊109b之間形成第二線接合111b後的總成100。在形成第二線接合111b後，第二記憶體晶粒106b可使用薄膜覆線材料143附著至第一記憶體晶粒106a。一旦記憶體晶粒經附著至彼此，則處理可繼續後續製造階段。舉例而言，處理可藉由將第二記憶體晶粒106b線接合至封裝基板102且接著在晶粒堆疊上方模製封裝外殼115(圖1A)而繼續。在一些實施例中，一或多個額外記憶體晶粒306(以虛線展示)可經堆疊於第二記憶體晶粒106b上方，且經線接合至封裝基板102之第 二焊墊108b。
圖4係根據本技術之另一實施例組態之一半導體晶粒總成400(「總成400」)之一橫截面視圖。總成400可包含大體類似於上文詳細描述之總成100之該等特徵部之特徵部。舉例而言，總成400包含控制器晶粒103及藉由晶粒附著材料140及141a至141b附著至封裝基板120之支撐構件130。在圖4中展示之配置中，個別記憶體晶粒406經交錯使得記憶體晶粒406之個別焊墊409沿記憶體晶粒406之堆疊之至少一個邊緣曝露。在此實施例之一個態樣中，線接合411可經接合至曝露之焊墊409，使得其等不由一薄膜覆線材料(例如，圖1A之薄膜覆線材料143)覆蓋。如此，可使用比一薄膜覆線材料相對更薄之一晶粒附著材料440組裝記憶體晶粒406。同樣地，記憶體晶粒406之堆疊可具有比與更厚薄膜覆線材料附著在一起之相同數量之記憶體晶粒之一堆疊更小之一高度。
圖5係根據本技術之另一實施例組態之一半導體晶粒總成500(「總成500」)之一俯視平面圖。總成500可包含大體類似於上文詳細描述之總成之該等特徵部之特徵部。舉例而言，總成500包含經定位於記憶體晶粒106之覆蓋區107內之控制器晶粒103(圖1A)。在圖5之所繪示實施例中，總成500亦可包含亦在覆蓋區107內且經由焊墊508耦合至封裝基板102之電容器550。電容器550可包含(例如)單塊(例如，陶瓷)、積體電路、或其他適當電容器裝置。在若干實施例中，電容器550可經組態以調節電力信號或促進通電。在其他實施例中，總成500可包含額外或替代電路元件(例如，電感器、電阻器及/或二極體)及/或電路組件，諸如至少部分在覆蓋區107內之另一半導體晶粒。
圖6A及圖6B係繪示根據本技術之若干實施例分別組態之半導體晶粒總成600a及600b之俯視平面圖。總成600a及600b各可包含大體類 似於上文詳細描述之總成之該等特徵部之特徵部。舉例而言，半導體晶粒總成600a及600b各可包含藉由支撐構件130形成之在封裝基板102與記憶體晶粒106(圖1A)之間的腔118。
參考圖6A，半導體晶粒總成600a包含在與支撐構件130之各者大體成橫向之一方向上延伸之一第三支撐構件630(例如，一長形構件)。在此實施例之一個態樣中，第三支撐構件630可藉由在第三支撐構件630之相對側上之間隙G1與支撐構件130隔開以促進囊封劑116流動至腔118中以形成外殼115(圖1A)。參考圖6B，半導體晶粒總成600b可包含經定位於控制器晶粒103之各側處之支撐構件635。類似於在圖6A中展示之第三支撐構件630，支撐構件635藉由間隙G2與支撐構件分離以促進囊封劑116流動至腔118中。
上文參考圖1至圖6B描述之堆疊式半導體晶粒總成之任一者可經併入至大量更大及/或更複雜系統之任一者中，該等系統之一代表性實例係在圖7中示意性展示之系統790。系統790可包含一半導體晶粒總成700、一電源792、一驅動器794、一處理器796、及/或其他子系統或組件798。半導體晶粒總成700可包含大體類似於上文描述之堆疊式半導體晶粒總成之該等特徵部之特徵部。所得系統790可執行許多各種功能之任一者，諸如記憶體儲存、資料處理及/或其他適當功能。因此，代表性系統790可包含但不限於手持式裝置(例如，行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦及電子設備。系統790之組件可經容置於一單一單元中或經分佈遍及多個、互連之單元(例如，透過一通信網路)。系統700之組件亦可包含遠端裝置及許多各種電腦可讀媒體之任一者。
自前文將瞭解，在本文中已為繪示之目的描述本技術之特定實施例，但可在不脫離揭示內容的情況下做出各種修改。同樣地，在特定實施例之內容背景中描述之新技術之特定態樣亦可在其他實施例中 組合或消除。再者，儘管與新技術之特定實施例相關之優點已在該等實施例之內容背景中描述，但其他實施例亦可展現此等優點，且並非所有實施例需要必要地展現此等優點來落入本技術之範疇內。因此，本揭示內容及相關技術可涵蓋在本文中未清楚展示或描述之其他實施例。

Claims (20)

  1. 一種半導體晶粒總成，其包括：一封裝基板，該封裝基板包含複數個第一焊墊；一第一半導體晶粒，其經附著至該封裝基板，其中該第一半導體晶粒包含複數個第二焊墊；複數個支撐構件，其等經附著至該封裝基板，該複數個支撐構件包含經安置於該第一半導體晶粒之不同側上之一第一支撐構件及一第二支撐構件；一第二半導體晶粒，其經耦合至該複數個支撐構件，使得該第二半導體晶粒之至少一部分係在該第一半導體晶粒上方，其中該第二半導體晶粒延伸在該複數個第二焊墊上方；一第一晶粒附著薄膜，該第一晶粒附著薄膜將該等支撐構件之各者附著至該第二半導體晶粒，但不將該第一半導體晶粒附著至該第二半導體晶粒，其中該第一晶粒附著薄膜延伸在該第二半導體晶粒與該第一半導體晶粒之間，及該第二半導體晶粒與該等支撐構件之各者之間，且其中該第一晶粒附著薄膜具有一均勻厚度；一第二晶粒附著薄膜，該第二晶粒附著薄膜將該等支撐構件之一者附著至該封裝基板；一第三晶粒附著薄膜，該第三晶粒附著薄膜將該第一半導體晶粒附著至該封裝基板；及複數個線接合，該複數個線接合將該複數個第一焊墊電耦合至該複數個第二焊墊之對應者，其中該複數個第一焊墊在該第二晶粒附著薄膜與該第三晶粒附著薄膜之間，其中該複數個線接合不接觸該第一晶粒附著薄膜，其中該等支撐構件之各者包含一長形構件，該等長形構件之至少一者具有一長度，該長度實質上等於該第二半導體晶粒之一側的一長度，且其中該等支撐構件之一者之長形構件垂直於該等支撐構件之另一者之長形構件。
  2. 如請求項1之半導體晶粒總成，其中該封裝基板進一步包含：複數個第三焊墊，其等經電耦合至該第二半導體晶粒，其中該等第三焊墊延伸至該第二半導體晶粒外側。
  3. 如請求項2之半導體晶粒總成，其中該複數個線接合為第一線接合，且其中該半導體晶粒總成進一步包括複數個第二線接合，其等將該等第三焊墊電耦合至該第二半導體晶粒之對應焊墊。
  4. 如請求項1之半導體晶粒總成，其中該複數個支撐構件、該第二半導體晶粒及該封裝基板一起界定該第二半導體晶粒下方之一腔，且其中該半導體晶粒總成進一步包括包含至少部分延伸至該腔內之一囊封劑之一封裝外殼。
  5. 如請求項1之半導體晶粒總成，其中該第一晶粒附著薄膜包含一壓力固定薄膜，其中該第二半導體晶粒係一第一記憶體晶粒，且其中該半導體晶粒總成進一步包括堆疊於該第一記憶體晶粒上之一第二記憶體晶粒。
  6. 如請求項1之半導體晶粒總成，其中該等支撐構件之各者之該長形構件包含矽。
  7. 如請求項1之半導體晶粒總成，其中該等長形構件之各者具有一連續長度。
  8. 一種半導體晶粒總成，其包括：一封裝基板，該封裝基板包含複數個第一焊墊；複數個支撐構件，其等經附著至該封裝基板且在該封裝基板上相互隔開；一控制器晶粒，其附著至該封裝基板，位於該複數個支撐構件之間，且包含複數個第二焊墊；一記憶體晶粒，其經耦合至該複數個支撐構件，使得該記憶體晶粒之至少一部分係在該控制器晶粒上方，其中該記憶體晶粒延伸在該複數個第二焊墊上方；一第一晶粒附著薄膜，該第一晶粒附著薄膜將該等支撐構件之各者附著至該記憶體晶粒，但不將該控制器晶粒附著至該記憶體晶粒，其中該第一晶粒附著薄膜延伸在該記憶體晶粒與該控制器晶粒之間，及該記憶體晶粒與該等支撐構件之各者之間；一第二晶粒附著薄膜，該第二晶粒附著薄膜將該等支撐構件之一者附著至該封裝基板；一第三晶粒附著薄膜，該第三晶粒附著薄膜將該控制器晶粒附著至該封裝基板，其中該複數個第一焊墊位於該第二晶粒附著薄膜與該第三晶粒附著薄膜之間；及複數個線接合，該複數個線接合將該複數個第一焊墊電耦合至該複數個第二焊墊之對應者，其中該複數個線接合位於該第一晶粒附著薄膜下方，其中該複數個支撐構件包含位於該控制器晶粒之不同側之一第一長形構件及一第二長形構件，其中該第一長形構件具有一長度，該長度實質上等於該第二半導體晶粒之一側的一長度，且其中該第一長形構件及該第二長形構件彼此垂直。
  9. 如請求項8之半導體晶粒總成，其中該第一長形構件及該第二長形構件各包含矽。
  10. 如請求項8之半導體晶粒總成，進一步包括在與該第一長形構件平行之一第三長形構件，其中該第二長形構件在該第一長形構件與該第三長形構件間橫向延伸。
  11. 如請求項8之半導體晶粒總成，其中該記憶體晶粒係一第一記憶體晶粒，且其中該半導體晶粒總成進一步包含堆疊於該第一記憶體晶粒上之一第二記憶體晶粒。
  12. 如請求項8之半導體晶粒總成，進一步包括經定位於該記憶體晶粒下方且至少部分在該記憶體晶粒之覆蓋區內之一電路組件，其中該電路組件係在該封裝基板上與該控制器晶粒分離，且其中該電路組件係一電容器。
  13. 如請求項8之半導體晶粒總成，其中該第一長形構件及該第二長形構件之各者具有一連續長度。
  14. 一種製造一半導體晶粒總成之方法，該方法包括：將一第一半導體晶粒附著至一封裝基板，其中該封裝基板包含複數個第一焊墊，且其中該第一半導體晶粒包含複數個第二焊墊；將一第一支撐構件及一第二支撐構件定位於該第一半導體晶粒之不同側上且互相垂直；使用線接合將該複數個第一焊墊耦合至及該複數個第二焊墊之對應者；及將一第二半導體晶粒附著至該第一及該第二支撐構件，使得該第一及該第二支撐構件將該第二半導體晶粒承載於該第一半導體晶粒上方，使得該第二半導體晶粒延伸在該複數個第二焊墊上方，且其中該第一支撐構件具有一長度，該長度實質上等於該第二半導體晶粒之一側的一長度；其中附著該第二半導體晶粒包含將該等支撐構件之各者附著至該第二半導體晶粒，使得該等線接合不接觸一第一晶粒附著薄膜，其中該第一晶粒附著薄膜延伸在該第二半導體晶粒與該第一半導體晶粒之間，及該第二半導體晶粒與該等支撐構件之各者之間，且其中該第一晶粒附著薄膜具有一均勻厚度；使用一第二晶粒附著薄膜將該第一支撐構件附著至該封裝基板，且使用一第三晶粒附著薄膜將該第一半導體晶粒附著至該封裝基板，該第三晶粒附著薄膜與該第二晶粒附著薄膜分離。
  15. 如請求項14之方法，其中該等第一焊墊係在該第二半導體晶粒之一覆蓋區內。
  16. 如請求項14之方法，其中該第一及該第二支撐構件、該第二半導體晶粒及該封裝基板一起界定該第二半導體晶粒下方之一腔，且其中該方法進一步包含將一囊封劑流動至該腔中。
  17. 如請求項14之方法，其中形成該第一支撐構件及該第二支撐構件包含：使用一晶粒附著材料來覆蓋一半導體晶圓；及切割該半導體晶圓以形成長形半導體構件，其等各具有附著至其等之該第二晶粒附著材料及該第三晶粒附著材料之一者。
  18. 如請求項14之方法，其中該第一、該第二及該第三晶粒附著材料各包含一壓力固定晶粒附著薄膜。
  19. 如請求項14之方法，其中該第二半導體晶粒係一第一記憶體晶粒，其中該方法進一步包括將一第二記憶體晶粒堆疊於該第一記憶體晶粒之頂部上，且其中將該第二記憶體晶粒堆疊於該第一記憶體晶粒之頂部上包含堆疊該第二記憶體晶粒，使得該第二記憶體晶粒相對於該第一記憶體晶粒交錯。
  20. 如請求項14之方法，其中該第一支撐構件及該第二支撐構件之各者具有一連續長度。
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