CN110634850A - 一种ssd堆叠封装结构及其制备方法 - Google Patents

一种ssd堆叠封装结构及其制备方法 Download PDF

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CN110634850A
CN110634850A CN201910926954.8A CN201910926954A CN110634850A CN 110634850 A CN110634850 A CN 110634850A CN 201910926954 A CN201910926954 A CN 201910926954A CN 110634850 A CN110634850 A CN 110634850A
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substrate
spacer
control chip
ssd
chip
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王蕊
熊涛
马晓建
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Huatian Technology Xian Co Ltd
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Abstract

本发明公开了一种SSD堆叠封装结构及其制备方法，其特征在于，包括：基板；控制芯片，所述控制芯片贴装在所述基板上，且控制芯片与基板电性连接；间隔件，所述间隔件下表面具有容置空间，间隔件贴装在所述基板上，且控制芯片置于所述容置空间内；存储芯片，所述存储芯片贴装在间隔件上表面；存储芯片通过键合线与基板电性连接；及塑封体，所述塑封体包覆基板、间隔件、存储芯片和键合线。该封装结构通过U型的Spacer保护控制芯片，防止裂片，小体积便于实现并提高了封装质量。

Description

一种SSD堆叠封装结构及其制备方法
技术领域
本发明属于存储芯片封装技术领域，涉及一种SSD堆叠封装结构及其制备方法。
背景技术
SSD(Solid State Drives)堆叠封装趋势是封装厚度薄，体积小，集成度高，容量大，对于超薄芯片封装，多芯片堆叠的可靠性和高集成度成为了封装的一大趋势，是这个行业技术人员的挑战。
对于SSD封装，通常将控制芯片和存储芯片合封在一起。目前SSD封装有3种：一、将控制芯片单独放置一侧，另一侧为存储芯片；二、控制芯片放置底层，上面叠封存储芯片；三、控制芯片埋于基板内。
目前这三种分别存在的问题：一、便于实现，体积大；二、裂片是一大难题；三、控制芯片尺寸受限，工艺难度大。
发明内容
本发明的目的克服上述现有技术中SSD堆叠封装体积大的缺点，提供一种SSD存储芯片封装结构及其制备方法。该封装结构通过U型的间隔件保护控制芯片，防止裂片，小体积便于实现并提高了封装质量。
为实现上述目的，本发明采用以下技术手段：
一种SSD堆叠封装结构，包括：
基板；
控制芯片，所述控制芯片贴装在所述基板上，且控制芯片与基板电性连接；
间隔件，所述间隔件具有容置空间，间隔件贴装在所述基板上，且控制芯片置于所述容置空间内；
存储芯片，所述存储芯片贴装在间隔件上；存储芯片通过键合线与基板电性连接；
及塑封体，所述塑封体包覆基板、间隔件、存储芯片和键合线。
所述基板表面具有基板线路和锡球，控制芯片与存储芯片均与基板线路电性连接。
所述基板上开设有基板孔，基板孔内填充导电材料，锡球设置在基板底部，锡球与导电材料和/或基板线路电性连接。
所述间隔件的容置空间为U型槽，U型槽的宽度大于控制芯片的长度。
所述间隔件上堆叠多层存储芯片。
所述间隔件的材料为金属材质。
一种SSD堆叠封装结构的制备方法，包括以下步骤：
在间隔件下表面形成容置空间；
在基板1上贴装控制芯片，使控制芯片与基板电性连接；
将具有容置空间间隔件贴装在所述基板上，并使得控制芯片置于所述容置空间内；
将存储芯片贴装在间隔件上表面；
在间隔件贴装在所述基板上，且控制芯片置于所述容置空间内；通过打线的方式实现线路连接；
最后塑封体包覆基板、间隔件、存储芯片和键合线，进行塑封。
所述间隔件采用蚀刻开槽的方式形成U型槽结构的容置空间。
与现有技术相比，本发明具有以下优点：
本发明的SSD存储芯片封装结构，包括一个具有容置空间的间隔件，该结构通过U型间隔件将控制芯片和存储芯片分离，减小上层芯片对控制芯片的压力，防止控制芯片裂片，使得减小控制芯片单独放置一侧封装结构的体积，改变了控制芯片埋封于基板结构的控制芯片尺寸不在受限制，降低了工艺难度，易于实现，良率高，成本低。
优选地，间隔件的材质可以根据实际需要选择，当间隔件为金属材质时，可以减少控制芯片的电磁干扰，同时加强上层堆叠存储芯片的散热，起到散热传导的作用。
附图说明
图1是为本发明的底板结构示意图；
图2是间隔件通过蚀刻开槽形成U型槽的示意图；
图3包括提供的基板和一次上芯示意图；
图4在图3基础上二次上芯示意图；
图5是在图4的基础上增加其余晶粒示意图。
图中，1：基板，2：锡球，3：基板孔，4：基板线路，5：控制芯片，6：间隔件，7：键合线，8：塑封体，9：存储芯片。
具体实施方式
为了使本技术领域的人员更好地理解本发明中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
需要说明的是，当元件被称为“设置于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的，并不表示是唯一的实施例。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1所示，本发明一种SSD存储芯片封装结构，包括基板1，基板1上直接贴装控制芯片5，键合使之控制芯片5与基板1导通，依据控制芯片5和存储芯片9尺寸放置不同尺寸、材质的U型间隔件6(Spacer)，间隔件6上堆叠多层存储芯片。具体结构包括：
基板1；
控制芯片5，所述控制芯片5贴装在所述基板1上，且控制芯片5与基板1电性连接；
间隔件6，所述间隔件6下表面具有容置空间，间隔件6贴装在所述基板1上，且控制芯片5置于所述容置空间内；
存储芯片9，所述存储芯片9贴装在间隔件6上表面；存储芯片9通过键合线7与基板1电性连接；
及塑封体8，所述塑封体8包覆基板1、间隔件6、存储芯片9和键合线7。
优选地，所述基板1表面具有基板线路4和锡球2，控制芯片5与存储芯片9均与基板线路4电性连接。基板1上开设有基板孔3，基板孔3内填充导电材料，锡球2设置在基板1底部，锡球2与导电材料和/或基板线路4电性连接。
作为优选实施例，间隔件6的容置空间为U型槽，U型槽的宽度大于控制芯片5的长度。所述间隔件6上堆叠多层存储芯片9。
作为优选实施例，间隔件6的材质可以根据实际需要选择，当间隔件6为金属材质时，可以减少控制芯片5的电磁干扰，同时加强上层堆叠存储芯片9的散热。
上述的SSD堆叠封装结构的制备方法，包括以下步骤：
在间隔件6下表面形成容置空间；
在基板1上贴装控制芯片5，使控制芯片5与基板1电性连接；
将具有容置空间间隔件6贴装在所述基板1上，并使得控制芯片5置于所述容置空间内；
将存储芯片9贴装在间隔件6上表面；
在间隔件6贴装在所述基板1上，且控制芯片5置于所述容置空间内；通过打线的方式实现线路连接；
最后塑封体8包覆基板1、间隔件6、存储芯片9和键合线7，进行塑封。
间隔件6采用蚀刻开槽的方式形成U型槽结构的容置空间。
实施例
图2到图4是本发明一些实施例的封装结构制造方法，具体的制造方法如下：
图2是通过蚀刻开槽形成U型槽的示意图，然后切割形成单独的间隔件，间隔件不限制材质，如硅材料，主要起到支撑作用；当间隔件6为金属材质时，可以减少控制芯片5的电磁干扰，同时加强上层堆叠存储芯片9的散热。
图3是在基板1上提供一次上芯；将控制芯片5贴装在所述基板1上；
图4在图3基础上二次上芯(上间隔件)；在间隔件6贴装在所述基板1上，且控制芯片5置于所述容置空间内；
图5是在图4的基础上增加其余晶粒，并通过打线的方式实现晶粒与基板的线路实现连接。具体是将存储芯片9贴装在间隔件6上表面；存储芯片9通过键合线7与基板1电性连接；最后将塑封体8包覆基板1、间隔件6、存储芯片9和键合线7。
二次上芯是通过U型间隔件将控制芯片6和存储芯片9分离，保护控制芯片6，减小上层存储芯片9对控制芯片承载的压力，防止控制芯片6裂片。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (8)

1.一种SSD堆叠封装结构，其特征在于，包括：
基板(1)；
控制芯片(5)，所述控制芯片(5)贴装在所述基板(1)上，且控制芯片(5)与基板(1)电性连接；
间隔件(6)，所述间隔件(6)具有容置空间，间隔件(6)贴装在所述基板(1)上，且控制芯片(5)置于所述容置空间内；
存储芯片(9)，所述存储芯片(9)贴装在间隔件(6)上；存储芯片(9)通过键合线(7)与基板(1)电性连接；
及塑封体(8)，所述塑封体(8)包覆基板(1)、间隔件(6)、存储芯片(9)和键合线(7)。
2.根据权利要求1所述的一种SSD堆叠封装结构，其特征在于，所述基板(1)表面具有基板线路(4)和锡球(2)，控制芯片(5)与存储芯片(9)均与基板线路(4)电性连接。
3.根据权利要求2所述的一种SSD堆叠封装结构，其特征在于，所述基板(1)上开设有基板孔(3)，基板孔(3)内填充导电材料，锡球(2)设置在基板(1)底部，锡球(2)与导电材料和/或基板线路(4)电性连接。
4.根据权利要求1所述的一种SSD堆叠封装结构，其特征在于，所述间隔件(6)的容置空间为U型槽，U型槽的宽度大于控制芯片(5)的长度。
5.根据权利要求1所述的一种SSD堆叠封装结构，其特征在于，所述间隔件(6)上堆叠多层存储芯片(9)。
6.根据权利要求1所述的一种SSD堆叠封装结构，其特征在于，所述间隔件(6)的材料为金属材质。
7.一种SSD堆叠封装结构的制备方法，其特征在于，包括以下步骤：
在间隔件(6)下表面形成容置空间；
在基板1上贴装控制芯片(5)，使控制芯片(5)与基板(1)电性连接；
将具有容置空间间隔件(6)贴装在所述基板(1)上，并使得控制芯片(5)置于所述容置空间内；
将存储芯片(9)贴装在间隔件(6)上表面；
在间隔件(6)贴装在所述基板(1)上，且控制芯片(5)置于所述容置空间内；通过打线的方式实现线路连接；
最后塑封体(8)包覆基板(1)、间隔件(6)、存储芯片(9)和键合线(7)，进行塑封。
8.根据权利要求1所述的一种SSD堆叠封装结构的制备方法，其特征在于，所述间隔件(6)采用蚀刻开槽的方式形成U型槽结构的容置空间。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030038374A1 (en) * 2001-08-27 2003-02-27 Shim Jong Bo Multi-chip package (MCP) with spacer
US20100267202A1 (en) * 2006-02-03 2010-10-21 Siliconware Precision Industries Co., Ltd. Method of fabricating stacked semiconductor structure
US20150028472A1 (en) * 2013-07-26 2015-01-29 SK Hynix Inc. Stacked package and method for manufacturing the same
US20160359520A1 (en) * 2013-06-29 2016-12-08 Intel IP Corporation Radio frequency shielding within a semiconductor package
CN106256018A (zh) * 2014-04-29 2016-12-21 美光科技公司 具有支撑构件的堆叠式半导体裸片组合件及相关的系统及方法
US20190198452A1 (en) * 2017-12-27 2019-06-27 Toshiba Memory Corporation Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030038374A1 (en) * 2001-08-27 2003-02-27 Shim Jong Bo Multi-chip package (MCP) with spacer
US20100267202A1 (en) * 2006-02-03 2010-10-21 Siliconware Precision Industries Co., Ltd. Method of fabricating stacked semiconductor structure
US20160359520A1 (en) * 2013-06-29 2016-12-08 Intel IP Corporation Radio frequency shielding within a semiconductor package
US20150028472A1 (en) * 2013-07-26 2015-01-29 SK Hynix Inc. Stacked package and method for manufacturing the same
CN106256018A (zh) * 2014-04-29 2016-12-21 美光科技公司 具有支撑构件的堆叠式半导体裸片组合件及相关的系统及方法
US20190198452A1 (en) * 2017-12-27 2019-06-27 Toshiba Memory Corporation Semiconductor device

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