JP5673423B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5673423B2 JP5673423B2 JP2011170422A JP2011170422A JP5673423B2 JP 5673423 B2 JP5673423 B2 JP 5673423B2 JP 2011170422 A JP2011170422 A JP 2011170422A JP 2011170422 A JP2011170422 A JP 2011170422A JP 5673423 B2 JP5673423 B2 JP 5673423B2
- Authority
- JP
- Japan
- Prior art keywords
- adhesive layer
- semiconductor chip
- semiconductor device
- integrated circuit
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0614—Circular array, i.e. array with radial symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/06177—Combinations of arrays with different layouts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81395—Bonding interfaces outside the semiconductor or solid-state body having an external coating, e.g. protective bond-through coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/8149—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
- H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92162—Sequential connecting processes the first connecting process involving a wire connector
- H01L2224/92163—Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
(1)構造
図1及び2は、本実施の形態の半導体装置2の平面図である。図3は、半導体装置2が有する集積回路チップ4の平面図である。図1は、スペーサ12を通る直線(図3のI-I線)に沿った半導体装置2の断面図である。図2は、ICパッド電極24を通る直線(図3のII−II線)に沿った半導体装置2の断面図である。
図5乃至7は、本実施の形態の半導体装置2の製造方法を説明する工程断面図である。以下、図5乃至7にしたがって、半導体装置2の製造方法を説明する。
まず、導電性ペースト32が塗布された基板10に、集積回路チップ4をスクラブして接着する。これにより、集積回路チップ4は裏面側で基板10に接着される。
まず、ワイヤボンディング装置のキャピラリ(図示せず)から、ボンディングワイヤ(例えば、Auワイヤ)の先端を射出する。このボンディングワイヤの先端部を放電により融解して、第1のボール20を形成する。
次に、集積回路チップ4の表面に設けられたICパッド電極24(図2参照)にボンディングワイヤの一端を接着する。更に、基板10の基板表面側パッド電極(図示せず)に、ボンディングワイヤ26の他端を接続する。
基板側に熱可塑性の接着層14(例えば、接着フィルム)が設けられた積層部材6を、集積回路チップ4の表面に直接接着されたスペーサ12の上に載置する。
接着層14を加熱しながら、スペーサ12の上に載置された積層部材6をスペーサ12に対して押圧する。この時、例えば、集積回路チップ4が設けられた基板10と積層部材6を、オーブン等で接着層14ごと加熱する。
次に、積層部材6がスペーサ12に接着された基板10を、樹脂封止用の金型(図示せず)に装着する。この金型にエポキシ系樹脂を注入し、注入した樹脂を加熱して硬化(キャア)させる。これにより、集積回路チップ4は、封止材8により封止される。その後、金型を外す。
樹脂封止された半導体装置2を金型から外し、基板10の裏面に形成された基板裏面側パッド電極に半田ボール28を搭載する。最後に、基板10を切断して半導体装置2を個片化する。
図8及び9は、本実施の形態の変形例2aを説明する断面図である。図8は、スペーサ12を通る直線に沿った断面図である。図9は、ICパッド電極24を通る直線に沿った断面図である。
図12及び13は、本実施の形態の半導体装置40の断面図である。図14は、半導体装置40が有する積層部材6の平面図である。以下、図12乃至14にしたがって、本実施の形態の半導体装置40を説明する。尚、実施の形態1と共通する部分については、説明を省略する。
図12は、スペーサ12を通る直線に沿った断面図である。図13は、ICパッド電極24を通る直線に沿った断面図である。
半導体装置40を製造するには、まず実施の形態1で説明した接着工程(図6(b)及び(c))までを実施する。但し、積層部材6は、集積回路チップ4Bである。
回路基板と、
前記回路基板上に設けられた第一の半導体チップと、
前記第一の半導体チップ上に設けられた複数の第一スペーサと、
下面に第一接着剤層を有し、前記複数の第一スペーサの上部に設けられた第二の半導体チップと、
前記回路基板と前記第一の半導体チップとを接続するワイヤと、
前記第一の半導体チップと前記第一接着剤層の間を封止する第一封止材と
を有し、
前記複数の第一スペーサの高さは、前記第一の半導体チップの上面に対する前記ワイヤの高さよりも高いこと
を特徴とする半導体装置。
回路基板と、
前記回路基板上に設けられた第一の半導体チップと、
前記第一の半導体チップ上に設けられた複数の第一スペーサと、
下面に第一接着剤層を有し、前記複数の第一スペーサの上部に設けられた放熱板と、
前記回路基板と前記第一の半導体チップとを接続するワイヤと、
前記第一の半導体チップと前記第一接着剤層の間を封止する第一封止材と
を有し、
前記複数の第一スペーサの高さは、前記第一の半導体チップの上面に対する前記ワイヤの高さよりも高いこと
を特徴とする半導体装置。
付記1又は2に記載の半導体装置において、
前記複数の第一スペーサは全て同じ高さを有することを特徴とする半導体装置。
付記3に記載の半導体装置において、
前記ワイヤの一部は、前記第一接着剤層に埋め込まれていることを特徴とする半導体装置。
付記1に記載の半導体装置において、
前記第二の半導体チップ上に設けられた複数の第二スペーサと、
下面に第二接着剤層を有し、前記複数の第二スペーサの上部に設けられた、第三の半導体チップと、
少なくても前記第二の半導体チップと前記第二接着剤層の間とを封止する第二封止材と
を有することを特徴とする半導体装置。
付記1または2に記載の半導体装置において、
前記第一スペーサは、前記第一の半導体チップの表面の接着パッドに直接接着された第1の金属ボールと、前記第1の金属ボール上に直接接着された第2の金属ボールとを有することを
特徴とする半導体装置。
付記6に記載の半導体装置において、
前記ワイヤは、前記第一の半導体チップの表面に接着されたワイヤボールを有し、
前記第一のスペーサが有する前記第1の金属ボールおよび前記第2の金属ボールは、前記ワイヤボールより大きいことを
特徴とする半導体装置。
回路基板上に設けられた第一の半導体チップの上面に直接接着されたスペーサの上に、下面に熱可塑性の第一接着剤層が設けられた第二の半導体チップを載置する載置工程と、
前記第一接着剤層を加熱しながら前記スペーサの上に載置された前記第二の半導体チップを前記スペーサに押圧して、前記スペーサに前記第二の半導体チップを接着する接着工程とを
有することを特徴とする半導体装置の製造方法。
回路基板上に設けられた第一の半導体チップの上面に直接接着されたスペーサの上に、下面に熱可塑性の第一接着剤層が設けられた放熱板を載置する載置工程と、
前記第一接着剤層を加熱しながら前記スペーサの上に載置された前記放熱板を前記スペーサに押圧して、前記スペーサに前記放熱板を接着する接着工程とを
有することを特徴とする半導体装置の製造方法。
付記8に記載の半導体装置の製造方法において、
更に、前記載置工程の前に、前記第一の半導体チップの上面にボンディングワイヤの一端を接着するワイヤボンディング工程を有し、
前記接着工程において、前記第一接着剤層を加熱しながら前記第二の半導体チップを前記第一の半導体チップに押圧して、前記スペーサの一部および前記ボンディングワイヤの一部を前記接着剤層に埋め込むこと
を特徴とする半導体装置の製造方法。
付記9に記載の半導体装置の製造方法において、
更に、前記載置工程の前に、前記第一の半導体チップの上面にボンディングワイヤの一端を接着するワイヤボンディング工程を有し、
前記接着工程において、前記第一接着剤層を加熱しながら前記放熱板を前記第一の半導体チップに押圧して、前記スペーサの一部および前記ボンディングワイヤの一部を前記接着剤層に埋め込むこと
を特徴とする半導体装置の製造方法。
付記8または9に記載の半導体装置の製造方法において、
更に、前記載置工程の前に、ボンディングワイヤの先端部に形成された第1のボールを前記第一の半導体チップの表面に設けられた接着パッドに直接接着し、
前記直接接着された前記第1のボール上にボンディングワイヤ先端部に形成された第2のボールを接着して、前記スペーサを形成するスペーサ形成工程を有することを
特徴とする半導体装置の製造方法。
4・・・集積回路チップ
6・・・積層部材
8・・・封止材
12・・・スペーサ
14・・・接着層
18・・・接着パッド
20・・・第1のボール
22・・・第2のボール
24・・・パッド電極
30・・・ワイヤボール
42・・・追加積層部材
44・・・追加スペーサ
46・・・追加接着層
Claims (10)
- 回路基板と、
前記回路基板上に設けられた第一の半導体チップと、
前記第一の半導体チップ上に設けられた複数の第一スペーサと、
下面に第一接着剤層を有し、前記複数の第一スペーサの上部が前記第一接着剤層に埋め込まれて接着された第二の半導体チップと、
前記回路基板と前記第一の半導体チップとを接続するワイヤと、
前記第一の半導体チップと前記第一接着剤層の間を封止する第一封止材と
を有し、
前記複数の第一スペーサの高さは、前記第一の半導体チップの上面に対する前記ワイヤの高さよりも高いこと
を特徴とする半導体装置。 - 回路基板と、
前記回路基板上に設けられた第一の半導体チップと、
前記第一の半導体チップ上に設けられた複数の第一スペーサと、
下面に第一接着剤層を有し、前記複数の第一スペーサの上部が前記第一接着剤層に埋め込まれて接着された放熱板と、
前記回路基板と前記第一の半導体チップとを接続するワイヤと、
前記第一の半導体チップと前記第一接着剤層の間を封止する第一封止材と
を有し、
前記複数の第一スペーサの高さは、前記第一の半導体チップの上面に対する前記ワイヤの高さよりも高いこと
を特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記複数の第一スペーサは全て同じ高さを有することを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記ワイヤの一部は、前記第一接着剤層に埋め込まれていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第二の半導体チップ上に設けられた複数の第二スペーサと、
下面に第二接着剤層を有し、前記複数の第二スペーサの上部に設けられた、第三の半導体チップと、
少なくても前記第二の半導体チップと前記第二接着剤層の間とを封止する第二封止材と
を有することを特徴とする半導体装置。 - 請求項1乃至5に記載の半導体装置において、
前記第一接着剤層は、前記第一の半導体チップから離間していることを特徴とする半導体装置。 - 回路基板上に設けられた第一の半導体チップの上面に直接接着されたスペーサの上に、下面に熱可塑性の第一接着剤層が設けられた第二の半導体チップを載置する載置工程と、
前記第一接着剤層を加熱しながら前記スペーサの上に載置された前記第二の半導体チップを前記スペーサに押圧して、前記スペーサの上部を前記第一接着剤層に埋め込んで前記第二の半導体チップを接着する接着工程と
を有することを特徴とする半導体装置の製造方法。 - 回路基板上に設けられた第一の半導体チップの上面に直接接着されたスペーサの上に、下面に熱可塑性の第一接着剤層が設けられた放熱板を載置する載置工程と、
前記第一接着剤層を加熱しながら前記スペーサの上に載置された前記放熱板を前記スペーサに押圧して、前記スペーサの上部を前記第一接着剤層に埋め込んで前記放熱板を接着する接着工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
更に、前記載置工程の前に、前記第一の半導体チップの上面にボンディングワイヤの一端を接着するワイヤボンディング工程を有し、
前記接着工程において、前記第一接着剤層を加熱しながら前記第二の半導体チップを前記第一の半導体チップに押圧して、前記スペーサの一部および前記ボンディングワイヤの一部を前記接着剤層に埋め込むこと
を特徴とする半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
更に、前記載置工程の前に、前記第一の半導体チップの上面にボンディングワイヤの一端を接着するワイヤボンディング工程を有し、
前記接着工程において、前記第一接着剤層を加熱しながら前記放熱板を前記第一の半導体チップに押圧して、前記スペーサの一部および前記ボンディングワイヤの一部を前記接着剤層に埋め込むこと
を特徴とする半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011170422A JP5673423B2 (ja) | 2011-08-03 | 2011-08-03 | 半導体装置および半導体装置の製造方法 |
US13/553,084 US8664775B2 (en) | 2011-08-03 | 2012-07-19 | Semiconductor device |
US14/156,671 US8980692B2 (en) | 2011-08-03 | 2014-01-16 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011170422A JP5673423B2 (ja) | 2011-08-03 | 2011-08-03 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013038106A JP2013038106A (ja) | 2013-02-21 |
JP5673423B2 true JP5673423B2 (ja) | 2015-02-18 |
Family
ID=47626466
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011170422A Active JP5673423B2 (ja) | 2011-08-03 | 2011-08-03 | 半導体装置および半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US8664775B2 (ja) |
JP (1) | JP5673423B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201410010A (zh) * | 2012-08-22 | 2014-03-01 | Hon Hai Prec Ind Co Ltd | 相機模組 |
CN104752380B (zh) * | 2013-12-31 | 2018-10-09 | 晟碟信息科技(上海)有限公司 | 半导体装置 |
US9418974B2 (en) * | 2014-04-29 | 2016-08-16 | Micron Technology, Inc. | Stacked semiconductor die assemblies with support members and associated systems and methods |
TWI591707B (zh) * | 2014-06-05 | 2017-07-11 | 東琳精密股份有限公司 | 薄型化晶片之封裝結構及其製造方法 |
US9305901B2 (en) * | 2014-07-17 | 2016-04-05 | Seagate Technology Llc | Non-circular die package interconnect |
JP6582754B2 (ja) * | 2015-08-31 | 2019-10-02 | 日亜化学工業株式会社 | 複合基板、発光装置、及び発光装置の製造方法 |
WO2018182752A1 (en) * | 2017-04-01 | 2018-10-04 | Intel Corporation | Electronic device package |
JP7034706B2 (ja) * | 2017-12-27 | 2022-03-14 | キオクシア株式会社 | 半導体装置 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08250628A (ja) | 1995-03-07 | 1996-09-27 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
KR100467946B1 (ko) * | 1997-01-24 | 2005-01-24 | 로무 가부시키가이샤 | 반도체 칩의 제조방법 |
JP2000208698A (ja) * | 1999-01-18 | 2000-07-28 | Toshiba Corp | 半導体装置 |
US6333562B1 (en) * | 2000-07-13 | 2001-12-25 | Advanced Semiconductor Engineering, Inc. | Multichip module having stacked chip arrangement |
JP2002057272A (ja) * | 2000-08-04 | 2002-02-22 | ▲せき▼品精密工業股▲ふん▼有限公司 | スタックト・ダイ・パッケージ構造 |
US6340846B1 (en) * | 2000-12-06 | 2002-01-22 | Amkor Technology, Inc. | Making semiconductor packages with stacked dies and reinforced wire bonds |
JP2002222889A (ja) * | 2001-01-24 | 2002-08-09 | Nec Kyushu Ltd | 半導体装置及びその製造方法 |
KR100401020B1 (ko) * | 2001-03-09 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지 |
US7518223B2 (en) * | 2001-08-24 | 2009-04-14 | Micron Technology, Inc. | Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer |
US20030042615A1 (en) * | 2001-08-30 | 2003-03-06 | Tongbi Jiang | Stacked microelectronic devices and methods of fabricating same |
US20030127719A1 (en) * | 2002-01-07 | 2003-07-10 | Picta Technology, Inc. | Structure and process for packaging multi-chip |
JP3729266B2 (ja) | 2003-02-24 | 2005-12-21 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4705748B2 (ja) * | 2003-05-30 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP3693057B2 (ja) * | 2003-07-04 | 2005-09-07 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7629695B2 (en) | 2004-05-20 | 2009-12-08 | Kabushiki Kaisha Toshiba | Stacked electronic component and manufacturing method thereof |
JP4188337B2 (ja) * | 2004-05-20 | 2008-11-26 | 株式会社東芝 | 積層型電子部品の製造方法 |
JP2006128169A (ja) * | 2004-10-26 | 2006-05-18 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
US7443037B2 (en) * | 2006-04-01 | 2008-10-28 | Stats Chippac Ltd. | Stacked integrated circuit package system with connection protection |
JP2008244168A (ja) * | 2007-03-27 | 2008-10-09 | Sharp Corp | 半導体装置、その製造方法、放熱板、半導体チップ、インターポーザー基板、およびガラス板 |
SG150395A1 (en) * | 2007-08-16 | 2009-03-30 | Micron Technology Inc | Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices |
JP5184132B2 (ja) | 2008-02-15 | 2013-04-17 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
-
2011
- 2011-08-03 JP JP2011170422A patent/JP5673423B2/ja active Active
-
2012
- 2012-07-19 US US13/553,084 patent/US8664775B2/en active Active
-
2014
- 2014-01-16 US US14/156,671 patent/US8980692B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US8664775B2 (en) | 2014-03-04 |
US20130032942A1 (en) | 2013-02-07 |
US20140187000A1 (en) | 2014-07-03 |
US8980692B2 (en) | 2015-03-17 |
JP2013038106A (ja) | 2013-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5673423B2 (ja) | 半導体装置および半導体装置の製造方法 | |
TWI529878B (zh) | 集成電路封裝件及其裝配方法 | |
JP4188337B2 (ja) | 積層型電子部品の製造方法 | |
JP5161732B2 (ja) | 半導体装置の製造方法 | |
JP4705748B2 (ja) | 半導体装置の製造方法 | |
TWI724744B (zh) | 半導體裝置及半導體裝置之製造方法 | |
KR20010104626A (ko) | 반도체장치 및 그 제조방법 | |
JP2006049569A (ja) | スタック型半導体装置パッケージおよびその製造方法 | |
JP2012009655A (ja) | 半導体パッケージおよび半導体パッケージの製造方法 | |
US8217517B2 (en) | Semiconductor device provided with wire that electrically connects printed wiring board and semiconductor chip each other | |
JP4175138B2 (ja) | 半導体装置 | |
JP2007242684A (ja) | 積層型半導体装置及びデバイスの積層方法 | |
JP5547703B2 (ja) | 半導体装置の製造方法 | |
JP2006222470A (ja) | 半導体装置および半導体装置の製造方法 | |
WO2017043480A1 (ja) | 半導体パッケージ | |
JP4972968B2 (ja) | 半導体装置及びその製造方法 | |
JP4688443B2 (ja) | 半導体装置の製造方法 | |
JP3899755B2 (ja) | 半導体装置 | |
JP3968321B2 (ja) | 半導体装置およびその製造方法 | |
JP2005101312A (ja) | 半導体装置の製造方法 | |
JP5234703B2 (ja) | 半導体装置の製造方法 | |
TWI264101B (en) | Method of flip-chip packaging including chip thermocompression | |
JP2000277559A (ja) | 半導体パッケージ及びその製造方法 | |
JP4473668B2 (ja) | 半導体装置およびその製造方法 | |
TWI297538B (en) | Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140430 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140811 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140819 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141020 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141202 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141215 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5673423 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |