CN101101882A - 基板树脂封装方法 - Google Patents
基板树脂封装方法 Download PDFInfo
- Publication number
- CN101101882A CN101101882A CNA2006100615783A CN200610061578A CN101101882A CN 101101882 A CN101101882 A CN 101101882A CN A2006100615783 A CNA2006100615783 A CN A2006100615783A CN 200610061578 A CN200610061578 A CN 200610061578A CN 101101882 A CN101101882 A CN 101101882A
- Authority
- CN
- China
- Prior art keywords
- substrate
- resin
- encapsulation unit
- independent
- full wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 114
- 239000011347 resin Substances 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 title claims description 125
- 238000004806 packaging method and process Methods 0.000 title claims description 19
- 238000005538 encapsulation Methods 0.000 claims abstract description 91
- 238000000465 moulding Methods 0.000 claims abstract description 25
- 239000002131 composite material Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 230000002262 irrigation Effects 0.000 claims description 6
- 238000003973 irrigation Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 238000006073 displacement reaction Methods 0.000 abstract description 13
- 150000001875 compounds Chemical class 0.000 abstract 1
- 238000013461 design Methods 0.000 description 7
- 238000011031 large-scale manufacturing process Methods 0.000 description 6
- 238000012856 packing Methods 0.000 description 6
- 238000005336 cracking Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000004382 potting Methods 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004080 punching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000011469 building brick Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/0909—Preformed cutting or breaking line
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明公开了一种基板树脂封装方法,它特别适合于在有机介质或复合介质基板上大规模、低成本、高成品率地用树脂封装裸露器件。在一块整片基板上对多个裸露器件进行独立树脂封装时,各个独立树脂封装单元之间的间隔保持一定的距离,独立树脂封装单元的树脂与不同热膨胀系数的基板的绝对位移和全体应力就变得较小,经过高温加热成型后,独立树脂封装单元的树脂与不同热膨胀系数的基板可以紧密地结合。它特别适合于大批量地对裸露芯片的封装,封装成本低、成品率高。
Description
【技术领域】
本发明涉及一种规模生产的基板树脂封装方法,主要用于电子器件的封装。它特别适合于大规模、低成本、高成品率地在有机材料基板及复合介质材料基板上用树脂封装裸露芯片或半导体器件。
【背景技术】
在目前的电子器件封装工程中,有多种电子器件的树脂封装的实现方法。例如目前比较流行的DIP、SOP、QFP、BGA、CSP封装,最近发展起来的MCM、SIP、SOP封装等。尤其是MCM和SIP封装适合于高速数字和高频模拟电路,已被广泛应用于通信、雷达、导航和家电的各种系统领域中。尤其是MCM封装,是将集成电路裸芯片和其它微型元器件互连组装在同一块高密谋高层基板上,并封装在同一树脂或管壳内构成功能齐全质量可靠、独立功能的电子组件。MCM是实现电子装备小型化轻量化高速度高可靠、低成本电路集成不可缺少的关键技术。它与传统的混合IC主要区别在于MCM采用裸芯片、表贴无源器件与多层布线基板,并实现高密度互连。
但是目前MCM和SIP封装用于高频时多采用陶瓷基板。采用陶瓷基板封装有频率高、高温不易变形、性能好的特点,可是另一方面采用陶瓷基板封装的成本高、制作工艺复杂、加工较复杂。近年来有机基板和复合基板的高频特性等性能有了长足的发展,可是若采用低成本有机基板和复合基板上实现树脂封装,大批量生产高温成型时树脂与基板附着差,容易出现剥离现象。对器件的密封性、可靠性产生致命的缺陷,甚至使产品完全报废。有机基板和复合基板上芯片与部件封装的低成本利用受到了限制。
本发明提出了一种适合于规模生产的基板树脂封装方法。可以较好地解决上述问题。
【发明内容】
本发明提出一种基板树脂封装方法,它适合于大规模、低成本、高效率地封装芯片等半导体器件。
本发明所采用的技术方案是:一种基板树脂封装方法,其包括:整片基板1,用树脂封装在该整片基板1上的裸露物体6和封装后形成的独立树脂封装单元2,其特征在于:在一块整片基板1上对多个裸露物体6采取分离封装,形成独立树脂封装单元2,各个独立树脂封装单元2之间的间隔3保持一定的距离d,经过固化成型后,将整片基板1上形成的独立树脂封装单元2切割成独立的封装单元。
裸露物体6是半导体芯片、导电线、印刷电路、电阻、电感、电容或它们的组合。
整片基板1可以是有机介质基板或复合介质基板。
独立树脂封装单元2可以是用模具形成的封装单元、滴灌形成的封装单元或吸附形成的封装单元。
在整片基板1上各个独立树脂封装单元2之间可以设有基板隔离空心孔4,独立树脂封装单元2间形成小面积的连接,这种连接可以在独立树脂封装单元2的顶角处,也可以在其他位置。
固化成型的过程可以是高温加热固化或常温放置固化。
在一块整片有机基板或复合基板上对多个独立裸露物体进行注模树脂封装。基板在X、Y、Z轴上的热膨胀系数CTE(Coefficient of Thermal Expansion)与树脂在X、Y、Z轴上的热膨胀系数CTE不同,基板与树脂之间就会发生局部开裂和剥离。在整块基板设计时,在各个独立树脂封装单元间保持一定的距离。由于一定的间隔距离的存在,在树脂注入高温成型时,独立树脂封装单元的树脂与不同热膨胀系数的基板的绝对位移就变得较小,位移应力小于粘着力。经过高温加热成型后,独立树脂封装单元的树脂与不同热膨胀系数的基板不会发生剥离,能够紧密地结合在一起。
为了便于切片,尤其考虑到高效率、低成本切片时,采用冲压式切片是一种有效的方式。为此,在整片基板上各个独立树脂封装单元之间形成可以有基板隔离空心孔,只是在独立树脂封装单元的之间某处基板形成小面积的连接,这种连接可以在独立树脂封装单元的顶角处,也可以在其他位置。空心孔可以是各种形状的。采用空心孔,既可以满足高效率、低成本冲压式切片,又可以在树脂注入高温成型时,独立树脂封装单元的树脂与不同热膨胀系数的基板的绝对位移就变得较小,经过高温加热成型后,独立树脂封装单元的树脂与不同热膨胀系数的基板不会发生剥离,能够紧密地结合在一起。
在选择有机介质基板或复合介质基板以及配套的封装树脂时,针对低频还是高频应用、低密度还是高密度封装、功率器件还是非功率器件,选择采用不同的基板的材料特性、基板的层数、介质板和附铜板的厚度、布线设计及散热的设计。以上的因素决定了基板的温度热膨胀系数。针对不同器件封装应用目的,配合所需的封装树脂,在封装过程的加温成型时,超过一定大小的分装面积时,树脂与不同热膨胀系数的基板必然位移力超过粘着力发生开裂剥离。在整块基板上封装多个独立封装树脂单元的设计时,由于上述复杂封装条件,通过实验和计算,有意识在基板上使各个独立树脂封装单元的间隔保持一定的距离。由于一定的间隔距离的存在,在树脂注入高温成型时,独立树脂封装单元的树脂与不同热膨胀系数的基板的绝对位移就变得较小,位移应力小于粘着力。树脂封装单元中的经过高温加热成型后,树脂封装单元的树脂与不同热膨胀系数的基板不会发生开裂、剥离,能够紧密地结合在一起。
这种适合于规模生产的基板树脂封装方法对利用低成本易受热变形的有机介质基板和复合介质基板上器件封装有着重要的意义。
参照图1,图2,图3,图4,这种适合于规模生产的基板树脂封装方法各部分的符号说明如下:
(1).整片基板1
(2).独立树脂封装单元2
(3).间隔3
(4).间距d
(5).隔离空心孔4
(6).未分割的整片封装树脂5
(7).裸露物体6
由于本发明适合于低成本的规模生产,即使树脂热膨胀系数与有机介质基板或复合介质基板之间热膨胀系数相差较大,也能在整片基板上进行树脂封装的一种方法,在MCM、SIP、SOP等树脂封装有广泛的应用价值。
因此本发明具有以下优点:
a.由于克服了在整片基板上大批量树脂封装、高温成型时树脂与基板附着差,容易出现剥离现象的弱点,适合于大规模生产的基板树脂封装。
b.相对于价位较高的陶瓷基板,由于采用本发明的方法方式,适合于在有机介质基板和复合介质基板上对多数电子元器件进行封装,适合于低成本、高成品率的基板树脂封装。
c.基板上的独立封装单元之间实施基板隔离空心孔,便于切片,同时还大大减少基板与树脂的剥离现象。尤其考虑到高效率、低成本切片时,采用冲压式切片是一种有效的方式。
d.独立树脂封装单元可以适应于基板上的各种封装形式,如模具形成的封装单元、滴灌形成的封装单元和吸附形成的封装单元。
【附图说明】
图1是本发明即基板树脂封装方法的概略图。
图2在整片有机介质基板或复合介质基板上,采用传统多个单元一体封装方法时引起的树脂与基板的开裂剥离示意图。
图3是在整片基板上各个独立树脂封装单元之间形成有基板隔离空心孔4的封装方法。
图4是独立树脂封装单元由模具形成的封装单元、滴灌形成的封装单元和吸附形成的封装单元的例子。
【具体实施方式】
请参阅图1,这是本发明,即基板树脂封装方法的概略图。图1(a)包括:整片基板,用树脂封装在该整片基板上的裸露物体和封装后形成的独立树脂封装单元,在一块整片基板上对多个裸露物体采取分离封装,形成独立树脂封装单元,各个独立树脂封装单元之间的间隔保持一定的距离,经过固化成型后,将整片基板上形成的独立树脂封装单元切割成独立的封装单元。从图1(a)的A1-A2截面的图1(b)中可以看出,经过高温加热成型后,图中整片基板出现弯曲,偏离水平线A3-A4。通过实验和计算,有意识在整片基板上使各个独立树脂封装单元之间的间隔保持一定的距离。
在一块整片有机基板或复合基板上对多个独立裸露物体进行注模树脂封装。基板在X、Y、Z轴上的热膨胀系数CTE(Coefficient of Thermal Expansion)与树脂在X、Y、Z轴上的热膨胀系数CTE不同,基板与树脂之间就会发生局部开裂和剥离。
以有机介质基板上MCM封装实施为例,我们采用手机中目前普遍采用的高频基板材料介电常数为4.2的FR-4材料基板,采用4层基板制作。在FR-4基板上实施对裸露物体即半导体裸露芯片、导电线、印刷电路、电阻、电感、电容等器件封装在一个单元里。FR-4基板在X、Y方向的热膨胀系数CTE典型值约在在12~15ppm/℃左右。但板厚Z方向在無拘束下將擴大為55~60ppm/℃。环氧树脂在X、Y、Z三方向的无拘束下热膨胀系数为70ppm/℃左右。由于一定的间隔距离d的存在,在树脂注入高温成型时,独立树脂封装单元2的树脂与不同热膨胀系数的基板的绝对位移就变得较小,位移应力小于粘着力。经过高温加热成型后,独立树脂封装单元2的树脂与不同热膨胀系数的整片基板1不会发生开裂、剥离,独立树脂封装单元2的树脂与不同热膨胀系数的基板紧密地结合。
在选择有机介质基板或复合介质基板以及配套的封装树脂时,针对低频还是高频应用、低密度还是高密度封装、功率器件还是非功率器件,选择采用不同的基板的材料特性、基板的层数、介质板和附铜板的厚度、布线设计及散热的设计。以上的因素决定了基板的温度热膨胀系数。针对不同器件封装应用目的,配合所需的封装树脂,在封装过程的加温成型时,超过一定大小的分装面积时,树脂与不同热膨胀系数的基板必然位移力超过粘着力发生开裂剥离。在整片基板上封装多个独立树脂封装单元的设计时,考虑到上述复杂封装条件,通过实验和计算,有意识在基板上使各个独立树脂封装单元的间隔保持一定的距离。由于一定的间隔距离的存在,在树脂注入高温成型时,独立树脂封装单元的树脂与不同热膨胀系数的基板的绝对位移就变得较小,位移应力小于粘着力。经过固化成型后,比如高温加热成型后,独立树脂封装单元的树脂与不同热膨胀系数的基板不会发生开裂、剥离,能够紧密地结合在一起。
图2是实施本发明前整片有机介质基板或复合介质基板上,采用传统多个单元方法一体封装时引起的树脂与基板的开裂剥离示意图。图2(a)显示了整片有机介质基板或复合介质基板上,多个单元方法一体封装的情形。从图2(b)中可以看出,在介质基板或复合介质基板1上,由于热膨胀系数的不同,加热固化时,大面积整体封装树脂5与基板极其容易发生开裂剥离。
图3是在整片基板1上各个独立树脂封装单元2之间形成有基板隔离空心孔4的封装方法。这样,在独立树脂封装单元之间某处基板形成小面积的连接,这种连接可以在树脂封装单元的顶角处,也可以在其他位置。图3(a)是侧视图,图3(b)是俯视图。空心孔4可以是各种形状的。采用空心孔4,既可以满足高效率、低成本冲压式切片,又可以在树脂注入高温成型时,独立树脂封装单元2的树脂与不同热膨胀系数的基板的绝对位移就变得较小。图3(c)是截面图,可以看出,经过高温加热成型后,与图1(b)的情形类似,独立树脂封装单元的树脂与不同热膨胀系数的基板不会发生剥离,能够紧密地结合在一起。
独立树脂封装单元2可以是用模具形成的封装单元、滴灌形成的封装单元或吸附形成的封装单元。
图4(a)是独立树脂封装单元2由模具形成的封装单元的截面图的例子;图4(b)是滴灌形成的封装单元的截面图例子、图4(c)是吸附形成的封装单元的截面图例子。
这里要强调的是固化成型的过程可以是高温加热固化或常温放置固化。
本发明可作为一种适合于大规模、低成本、高成品率的有机介质或复合介质基板的树脂封装方法,必然能得到广泛的应用。
Claims (6)
1.一种基板树脂封装方法,其包括:整片基板1,用树脂封装在该整片基板1上的裸露物体6和封装后形成的独立树脂封装单元2,其特征在于:在一块整片基板1上对多个裸露物体6采取分离封装,形成独立树脂封装单元2,各个独立树脂封装单元2之间的间隔3保持一定的距离d,经过固化成型后,将整片基板1上形成的独立树脂封装单元2切割成独立的封装单元。
2.根据权利要求1所述的一种基板树脂封装方法,其特征在于:裸露物体6是半导体芯片、导电线、印刷电路、电阻、电感、电容或它们的组合。
3.根据权利要求1或2所述的一种基板树脂封装方法,其特征在于:整片基板1可以是有机介质基板或复合介质基板。
4.根据权利要求1、2、3或4所述的一种基板树脂封装方法,其特征在于:独立树脂封装单元2可以是用模具形成的封装单元、滴灌形成的封装单元或吸附形成的封装单元。
5.根据权利要求1所述的一种基板树脂封装方法,其特征在于:在整片基板1上各个独立树脂封装单元2之间可设有基板隔离空心孔4,独立树脂封装单元2间形成小面积的连接,这种连接可以在独立树脂封装单元2的顶角处,也可以在其他位置。
6.根据权利要求1所述的一种基板树脂封装方法,其特征在于:固化成型的过程可以是高温加热固化或常温放置固化。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2006100615783A CN101101882A (zh) | 2006-07-05 | 2006-07-05 | 基板树脂封装方法 |
GB0712834.1A GB2439837B (en) | 2006-07-05 | 2007-07-03 | Method for packaging using resin |
PCT/CN2007/002067 WO2008006299A1 (fr) | 2006-07-05 | 2007-07-04 | Procédé d'application d'un revêtement de conditionnement en résine sur un substrat |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2006100615783A CN101101882A (zh) | 2006-07-05 | 2006-07-05 | 基板树脂封装方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101101882A true CN101101882A (zh) | 2008-01-09 |
Family
ID=38421092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2006100615783A Pending CN101101882A (zh) | 2006-07-05 | 2006-07-05 | 基板树脂封装方法 |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN101101882A (zh) |
GB (1) | GB2439837B (zh) |
WO (1) | WO2008006299A1 (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2937765B1 (fr) * | 2008-10-27 | 2010-12-17 | Smart Packaging Solutions Sps | Procede de montage de composants passifs sur un objet portable de faible epaisseur, et objet portable ainsi obtenu |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS577144A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
US5612513A (en) * | 1995-09-19 | 1997-03-18 | Micron Communications, Inc. | Article and method of manufacturing an enclosed electrical circuit using an encapsulant |
JP3398580B2 (ja) * | 1997-09-13 | 2003-04-21 | 株式会社東芝 | 半導体装置の製造方法及び基板フレーム |
JPH1197466A (ja) * | 1997-09-18 | 1999-04-09 | Miyota Kk | Icチップのパッケージ方法 |
JP4073098B2 (ja) * | 1998-11-18 | 2008-04-09 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP3339838B2 (ja) * | 1999-06-07 | 2002-10-28 | ローム株式会社 | 半導体装置およびその製造方法 |
AU6001599A (en) * | 1999-10-01 | 2001-05-10 | Hitachi Limited | Semiconductor device and method of manufacture thereof |
FR2799306B1 (fr) * | 1999-10-04 | 2003-09-19 | Gemplus Card Int | Procede d'isolation de puce de circuit integre par depot de matiere sur la face active |
JP2002026182A (ja) * | 2000-07-07 | 2002-01-25 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP3738176B2 (ja) * | 2000-08-03 | 2006-01-25 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2002076040A (ja) * | 2000-08-30 | 2002-03-15 | Hitachi Ltd | 半導体装置及びその製造方法 |
EP1325518A1 (en) * | 2000-10-13 | 2003-07-09 | Tyco Electronics AMP GmbH | Electronic unit and process for the production thereof |
US6773961B1 (en) * | 2003-08-15 | 2004-08-10 | Advanced Semiconductor Engineering Inc. | Singulation method used in leadless packaging process |
JP2005079365A (ja) * | 2003-09-01 | 2005-03-24 | Oki Electric Ind Co Ltd | 基板フレーム及びこれを用いた半導体装置の製造方法 |
KR20050083322A (ko) * | 2004-02-23 | 2005-08-26 | 삼성테크윈 주식회사 | 반도체 패키지용 리이드 프레임과 이의 제조방법 |
-
2006
- 2006-07-05 CN CNA2006100615783A patent/CN101101882A/zh active Pending
-
2007
- 2007-07-03 GB GB0712834.1A patent/GB2439837B/en not_active Expired - Fee Related
- 2007-07-04 WO PCT/CN2007/002067 patent/WO2008006299A1/zh active Application Filing
Also Published As
Publication number | Publication date |
---|---|
GB0712834D0 (en) | 2007-08-08 |
GB2439837A (en) | 2008-01-09 |
WO2008006299A1 (fr) | 2008-01-17 |
GB2439837B (en) | 2012-01-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102479762B (zh) | 散热增益型半导体组件 | |
CN104253105B (zh) | 半导体器件和形成低廓形3d扇出封装的方法 | |
EP1764834B1 (en) | Electromagnetic shielding of packages with a laminate substrate | |
US8749049B2 (en) | Chip package with a chip embedded in a wiring body | |
CN109801893A (zh) | 半导体装置 | |
CN107968084A (zh) | 具有集成天线的半导体封装及其形成方法 | |
US20080211083A1 (en) | Electronic package and manufacturing method thereof | |
TW201133769A (en) | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP | |
CN202839599U (zh) | 一种芯片嵌入式三维圆片级封装结构 | |
CN104505382A (zh) | 一种圆片级扇出PoP封装结构及其制造方法 | |
CN109640521A (zh) | 制造具有嵌入式集群的部件承载件的方法以及部件承载件 | |
CN202871783U (zh) | 一种芯片嵌入式堆叠圆片级封装结构 | |
US10923364B2 (en) | Methods for producing packaged semiconductor devices | |
CN202905686U (zh) | 一种多芯片圆片级封装结构 | |
CN112018055B (zh) | 电磁屏蔽散热封装结构及其制备方法 | |
CN103367174A (zh) | 制造半导体器件的方法以及半导体器件 | |
CN101202259B (zh) | 芯片堆栈封装结构、内埋式芯片封装结构及其制造方法 | |
CN101101882A (zh) | 基板树脂封装方法 | |
CN203351591U (zh) | 一种柔性基板封装结构 | |
CN206116378U (zh) | 半导体封装构造 | |
WO2012126374A1 (en) | 3d system-level packaging methods and structures | |
CN202678302U (zh) | 一种扇出型圆片级芯片封装结构 | |
CN103346145B (zh) | 一种柔性基板封装结构 | |
CN203941896U (zh) | 一种圆片级芯片扇出封装结构 | |
US20080116587A1 (en) | Conductor polymer composite carrier with isoproperty conductive columns |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |