GB0712834D0 - Method for packaging using resin - Google Patents
Method for packaging using resinInfo
- Publication number
- GB0712834D0 GB0712834D0 GBGB0712834.1A GB0712834A GB0712834D0 GB 0712834 D0 GB0712834 D0 GB 0712834D0 GB 0712834 A GB0712834 A GB 0712834A GB 0712834 D0 GB0712834 D0 GB 0712834D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- resin
- substrate
- packaging
- components
- gaps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/12—Passive devices, e.g. 2 terminal devices
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- H01L2924/12044—OLED
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/0909—Preformed cutting or breaking line
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
Abstract
A method for packaging electronic components using resin comprises mounting a plurality of bare components 2 on a common substrate 1 separated by a gap d, individually encapsulating each component 2 with a resin packaging material, solidifying the resin and then cutting the substrate in the gaps to form separate resin encapsulated components. Holes 4 may be formed in the gaps to facilitate cutting. The invention relieves the problem of the resin splitting from the substrate due to different thermal expansions between the resin and substrate materials. This makes it possible to tightly attach the resin to the substrate, and is especially suitable for packaging of large scale bare chips.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2006100615783A CN101101882A (en) | 2006-07-05 | 2006-07-05 | Substrate resin packaging method |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0712834D0 true GB0712834D0 (en) | 2007-08-08 |
GB2439837A GB2439837A (en) | 2008-01-09 |
GB2439837B GB2439837B (en) | 2012-01-18 |
Family
ID=38421092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0712834.1A Expired - Fee Related GB2439837B (en) | 2006-07-05 | 2007-07-03 | Method for packaging using resin |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN101101882A (en) |
GB (1) | GB2439837B (en) |
WO (1) | WO2008006299A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2937765B1 (en) * | 2008-10-27 | 2010-12-17 | Smart Packaging Solutions Sps | METHOD FOR MOUNTING PASSIVE COMPONENTS ON A PORTABLE OBJECT OF LOW THICKNESS, AND PORTABLE OBJECT THUS OBTAINED |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS577144A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
US5612513A (en) * | 1995-09-19 | 1997-03-18 | Micron Communications, Inc. | Article and method of manufacturing an enclosed electrical circuit using an encapsulant |
JP3398580B2 (en) * | 1997-09-13 | 2003-04-21 | 株式会社東芝 | Semiconductor device manufacturing method and substrate frame |
JPH1197466A (en) * | 1997-09-18 | 1999-04-09 | Miyota Kk | Package method of ic chip |
JP4073098B2 (en) * | 1998-11-18 | 2008-04-09 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
JP3339838B2 (en) * | 1999-06-07 | 2002-10-28 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
JP4422380B2 (en) * | 1999-10-01 | 2010-02-24 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
FR2799306B1 (en) * | 1999-10-04 | 2003-09-19 | Gemplus Card Int | METHOD FOR INSULATING AN INTEGRATED CIRCUIT CHIP BY DEPOSITING MATERIAL ON THE ACTIVE FACE |
JP2002026182A (en) * | 2000-07-07 | 2002-01-25 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
JP3738176B2 (en) * | 2000-08-03 | 2006-01-25 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
JP2002076040A (en) * | 2000-08-30 | 2002-03-15 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
WO2002031881A1 (en) * | 2000-10-13 | 2002-04-18 | Tyco Electronics Amp Gmbh | Electronic unit and process for the production thereof |
US6773961B1 (en) * | 2003-08-15 | 2004-08-10 | Advanced Semiconductor Engineering Inc. | Singulation method used in leadless packaging process |
JP2005079365A (en) * | 2003-09-01 | 2005-03-24 | Oki Electric Ind Co Ltd | Substrate frame and method for manufacturing semiconductor device using this |
KR20050083322A (en) * | 2004-02-23 | 2005-08-26 | 삼성테크윈 주식회사 | Lead frame for semiconductor package and the fabrication method thereof |
-
2006
- 2006-07-05 CN CNA2006100615783A patent/CN101101882A/en active Pending
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2007
- 2007-07-03 GB GB0712834.1A patent/GB2439837B/en not_active Expired - Fee Related
- 2007-07-04 WO PCT/CN2007/002067 patent/WO2008006299A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
GB2439837B (en) | 2012-01-18 |
WO2008006299A1 (en) | 2008-01-17 |
CN101101882A (en) | 2008-01-09 |
GB2439837A (en) | 2008-01-09 |
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