GB2439837A - Method for packaging an electronic component using resin - Google Patents
Method for packaging an electronic component using resin Download PDFInfo
- Publication number
- GB2439837A GB2439837A GB0712834A GB0712834A GB2439837A GB 2439837 A GB2439837 A GB 2439837A GB 0712834 A GB0712834 A GB 0712834A GB 0712834 A GB0712834 A GB 0712834A GB 2439837 A GB2439837 A GB 2439837A
- Authority
- GB
- United Kingdom
- Prior art keywords
- resin
- packaging
- substrate
- independent
- components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 99
- 239000011347 resin Substances 0.000 title claims abstract description 65
- 229920005989 resin Polymers 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000007711 solidification Methods 0.000 claims description 8
- 230000008023 solidification Effects 0.000 claims description 8
- 239000002131 composite material Substances 0.000 claims description 7
- 238000010521 absorption reaction Methods 0.000 claims description 6
- 230000002262 irrigation Effects 0.000 claims description 6
- 238000003973 irrigation Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 3
- 239000005022 packaging material Substances 0.000 abstract 1
- 238000006073 displacement reaction Methods 0.000 description 12
- 238000000465 moulding Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000005266 casting Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 210000000056 organ Anatomy 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/0909—Preformed cutting or breaking line
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A method for packaging electronic components using resin comprises mounting a plurality of bare components 2 on a common substrate 1 separated by a gap d, individually encapsulating each component 2 with a resin packaging material, solidifying the resin and then cutting the substrate in the gaps to form separate resin encapsulated components. Holes 4 may be formed in the gaps to facilitate cutting. The invention relieves the problem of the resin splitting from the substrate due to different thermal expansions between the resin and substrate materials. This makes it possible to tightly attach the resin to the substrate, and is especially suitable for packaging of large scale bare chips.
Description
<p>METHOD FOR PACKAGING USING RESIN</p>
<p>The invention relates to a method, and more particularly to a method for packaging using resin.</p>
<p>Conventionally, resin is used to package electronic components on a substrate.</p>
<p>However, during a high-temperature molding process, the resin is prone to split or deviate from the substrate, which will severely decrease quality of the electronic components, and may ultimately obsolesce the electronic components.</p>
<p>It is a general object of the present invention to provide a method for packaging using resin, so as to tightly attach resin to a substrate.</p>
<p>In one aspect, the invention provides a method for packaging using resin, comprising a substrate, a plurality of bare objects to be packaged on the substrate via resin and an independent resin-packaging component formed after packaging; wherein the bare objects are separately packaged on the substrate to form the independent resin-packaging component; there is a gap with a certain width between the bare objects; and the independent resin-packaging component formed after packaging is cut into a plurality of independent packaging components after a solidification process.</p>
<p>In certain classes of this embodiment, the bare object is a semiconductor chip, a conductive lead, a printed circuit, a resistor, an inductor, a capacitor, or a combination thereof.</p>
<p>In certain classes of this embodiment, the substrate is an organic substrate.</p>
<p>In certain classes of this embodiment, the substrate is a composite substrate.</p>
<p>In certain classes of this embodiment, the independent resin-packaging component is a packaging component formed by moulds.</p>
<p>In certain classes of this embodiment, the independent resin-packaging component is a packaging component formed by drip irrigation.</p>
<p>In certain classes of this embodiment, the independent resin-packaging component is a packaging component formed by absorption.</p>
<p>In certain classes of this embodiment, a plurality of clearance holes are disposed between independent resin-packaging components on the substrate.</p>
<p>In certain classes of this embodiment, a plurality of connections are formed between independent resin-packaging components.</p>
<p>In certain classes of this embodiment, the connection may be located at a top corner of the independent resin-packaging components or somewhere else.</p>
<p>In certain classes of this embodiment, the solidification process may be implemented by high-temperature heating.</p>
<p>In certain classes of this embodiment, the solidification process may be implemented by normal-temperature placement.</p>
<p>A plurality of bare objects are packaged with casting resin on an organic substrate or a composite substrate. Since coefficients of thermal expansion (CTE) of the substrate along the X, Y and Z axis are different from those of the resin, the substrate may split or deviate from the resin. In designing a substrate, a gap with a certain width is disposed between the independent resin-packaging components, as the resin is molded with high temperature, an absolute displacement between the resin of the independent resin-packaging component and the substrates with different CTEs will decrease, and thus the displacement stress is less than the adhesion force. After high-temperature molding, the resin of the independent resin-packaging component will not split or deviate from, but tightly attach to the substrates with different CTEs.</p>
<p>A plurality of clearance holes are formed between different independent resin-packaging components on a substrate and a connection is formed on a certain substrate between different independent resin-packaging components.</p>
<p>The connection may be located at a top corner of the independent resin-packaging components or somewhere else. The clearance hole may take different shapes. Once the clearance hole is used, a cost effective ram slicing may be realized, and an absolute displacement between the resin of the independent resin-packaging component and the substrates with different CTEs will decrease as the resin is molded with high temperature. After high-temperature molding, the resin of the independent resin-packaging component will not split or deviate from, but tightly attach to the substrates with different CTEs.</p>
<p>In choosing an organ or a composite substrate and matching packaging resin, material characteristic of different substrates, the number of layers of a substrate, thickness of a dielectric plate and a copper-clad laminate, layout and heat-dissipation design, along with CTEs of different substrates are determined by factors such as low-frequency/highfrequency applications, low-density/high-density packaging, along with power/non-power devices.</p>
<p>During molding of the packaging process, as the displacement stress is greater than the adhesion force, the resin will split or deviate from substrates with different CTEs. In view of the above complex packaging situations, by way of experimenting and calculating, a gap with a certain width is disposed between the independent resin-packaging components, thereby the displacement stress is less than the adhesion force, and thus an absolute displacement between the resin of the independent resin-packaging component and the substrates with different CTEs will decrease. After high-temperature molding, the resin of the independent resin-packaging component will not split or deviate from, but tightly attach to the substrates with different CTEs.</p>
<p>The invention has the following advantages over the prior art: a. the invention is suitable for large scale packaging using resin.</p>
<p>b. the invention is suitable for cost-effective packaging using resin.</p>
<p>c. a plurality of clearance hole are disposed between the independent resin-packaging components, which makes it convenient for slicing, and prevents the resin from splitting or deviating from the substrate.</p>
<p>d. the independent resin-packaging component may be formed by different packaging technologies, such as moulds, drip irrigation or absorption.</p>
<p>The invention will now be described solely by way of example and with reference to the accompanying drawings in which: Fig. 1 is a schematic diagram of a method for packaging using resin of the invention; Fig. 2 is a diagram illustrating resin splitting from a substrate as a traditional packaging method is used; Fig. 3 is a packaging method in which a plurality of clearance holes 4 are formed between different independent resin-packaging components on a substrate; and Fig. 4 illustrates packaging components respectively formed by moulds, drip irrigation and absorption.</p>
<p>The invention will now be described further, by way of example, with reference to the accompany drawings and integral movement modes. The reference numbers of the parts/components in accordance with the present invention are listed below, in which: substrate 1, independent resin-packaging component 2, gap 3, clearance hole 4, resin 5 and bare object 6.</p>
<p>Fig. 1 is a schematic diagram of a method for packaging using resin of the invention.</p>
<p>Fig. 1(a) comprises a substrate 1, a plurality of bare objects 6 to be packaged on the substrate 1 via resin, and an independent resin-packaging component 2 formed after packaging. The bare objects 6 are separately packaged on the substrate 1 to form the independent resin-packaging components 2, and there is a gap 3 between the independent resin-packaging components 2.</p>
<p>After a solidification process, the independent resin-packaging component 2 formed on the substrate 1 is cut into a plurality of independent packaging components.</p>
<p>As can be seen from Fig. 1(b), the substrate 1 curves and deviates from a horizontal line A3-A4 after high-temperature molding. By way of experimenting and calculating, a gap 3 with a certain width is disposed between the independent resin-packaging components 2.</p>
<p>A plurality of bare objects 6 are packaged with casting resin 5 on an organic substrate or a composite substrate. Since coefficients of thermal expansion (GTE) of the substrate 1 along the X, Y and Z axis are different from those of the resin 5, the substrate 1 may split or deviate from the resin 5.</p>
<p>Taking a MCM packaging on the organic substrate for example, a 4-layer FR-4 substrate with a dielectric constant of 4.2 is employed. The bare objects 6 (namely a bare semiconductor chip, a conductive lead, a printed circuit, a resistor, an inductor, a capacitor and so on) are packaged into a component. A typical CTE value of the RF-4 substrate in X and Y direction is approximately 1215ppmI0C. However, in an unconstraint condition, a CTE value of the RF-4 substrate in Z direction may be up to 55-6OppmiC, and a CTE value of epoxy resin in X, V and Z direction is approximately 7Oppm/ C.</p>
<p>Due to the existence of the gap 3, as the resin 5 is molded with high temperature, an absolute displacement between the resin 5 of the independent resin-packaging component 2 and the substrates 1 with different CTEs will decrease, and thus the displacement stress is less than the adhesion force.</p>
<p>After high-temperature molding, the resin 5 of the independent resin-packaging component 2 will not split or deviate from, but tightly attach to the substrates 1 with different CTEs.</p>
<p>In choosing an organ or a composite substrate and matching packaging resin, material characteristic of different substrates, the number of layers of a substrate, thickness of a dielectric plate and a copper-clad laminate, layout and heat-dissipation design, along with CTEs of different substrates are determined by factors such as low-frequency/high-frequency applications, low-density/high-density packaging, along with power/non-power devices.</p>
<p>During molding of the packaging process, as the displacement stress is greater than the adhesion force, the resin 5 will split or deviate from substrates 1 with different CTEs. In view of the above complex packaging situations, by way of experimenting and calculating, a gap 3 with a certain width is disposed between the independent resin-packaging components 2, thereby the displacement stress is less than the adhesion force, and thus an absolute displacement between the resin 5 of the independent resin-packaging component 2 and the substrates 1 with different CTEs will decrease. After high-temperature molding, the resin 5 of the independent resin-packaging component 2 will not split or deviate from, but tightly attach to the substrates 1 with different CTEs.</p>
<p>Fig. 2 is a diagram illustrating resin 5 splitting from a substrate 1 as a traditional packaging method is used.</p>
<p>Fig. 2(a) illustrates a scenario where a plurality of components are integratively packaged on an organic or a composite substrate.</p>
<p>As can be seen from Fig. 2(b), in a heating process, the resin 5 is prone to split or deviate from the substrate 1 due to different CTEs on the substrate 1.</p>
<p>Fig. 3 is a packaging method in which a plurality of clearance holes 4 are formed between different independent resin-packaging components 2 on a substrate 1. Once the clearance hole 4 is used, a cost effective ram slicing may be realized, and an absolute displacement between the resin of the independent resin-packaging component 2 and the substrates with different CTEs will decrease as the resin 5 is molded with high temperature.</p>
<p>As shown in a side view Fig. 3(a), a plurality of connections are formed between different independent resin-packaging components 2. In this embodiment, the connection is located at a top corner of the independent resin-packaging components 2. In other embodiments, the connection may be located somewhere else.</p>
<p>As shown in a top view Fig. 3(b), the clearance hole 4 may take different shapes.</p>
<p>As shown in a sectional view Fig. 3(c), the resin 5 of the independent resin-packaging component 2 will not split or deviate from, but tightly attach to the substrates 1 with different CTEs.</p>
<p>The independent resin-packaging component 2 may be formed by moulds, drip irrigation or absorption.</p>
<p>Figs. 4(a), 4(b) and 4(c) respectively illustrates packaging components respectively formed by moulds, drip irrigation and absorption.</p>
<p>It should be emphasized herein that the solidification process may be implemented by high-temperature or normal-temperature heating.</p>
<p>The particular embodiment having thus been described, it will now be evident to those skilled in the art that further modifications and variation thereto may be contemplated. Such modifications and variations are not regarded as a departure from the invention.</p>
<p>All publications and patent applications mentioned in this specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication or patent application mentioned in this specification was specifically and individually indicated to be incorporated by reference.</p>
Claims (1)
- <p>CLAIMS</p><p>1. A method for packaging using resin, comprising a substrate; a plurality of bare objects to be packaged on the substrate via resin; and an independent resin-packaging component formed after packaging; wherein the bare objects are separately packaged on the substrate to form the independent resin-packaging component; there is a gap with a certain width between the bare objects; and the independent resin-packaging component formed after packaging is cut into a plurality of independent packaging components after a solidification process.</p><p>2. The method for packaging using resin of claim 1, wherein the bare object is a semiconductor chip, a conductive lead, a printed circuit, a resistor, an inductor, a capacitor, or a combination thereof.</p><p>3. The method for packaging using resin of claim 2, wherein the substrate is an organic substrate 4. The method for packaging using resin of claim 3, wherein the substrate is a composite substrate.</p><p>5. The method for packaging using resin of claim 1, wherein the independent resin-packaging component is a packaging component formed by moulds.</p><p>6. The method for packaging using resin of claim 5, wherein the independent resin-packaging component is a packaging component formed by drip irrigation.</p><p>7. The method for packaging using resin of claim 6, wherein the independent resin-packaging component is a packaging component formed by absorption.</p><p>8. The method for packaging using resin of claim 1, wherein a plurality of clearance holes are disposed between independent resin-packaging components on the substrate 1.</p><p>9. The method for packaging using resin of claim 8, wherein a plurality of connections are formed between independent resin-packaging components.</p><p>10. The method for packaging using resin of claim 9, wherein the connection may be located at a top corner of the independent resin-packaging components or somewhere else.</p><p>11. The method for packaging using resin of claim 1, wherein the solidification process may be implemented by high-temperature heating.</p><p>12. The method for packaging using resin of claim 11, wherein the solidification process may be implemented by normal-temperature placement.</p>
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2006100615783A CN101101882A (en) | 2006-07-05 | 2006-07-05 | Substrate resin packaging method |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0712834D0 GB0712834D0 (en) | 2007-08-08 |
GB2439837A true GB2439837A (en) | 2008-01-09 |
GB2439837B GB2439837B (en) | 2012-01-18 |
Family
ID=38421092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0712834.1A Expired - Fee Related GB2439837B (en) | 2006-07-05 | 2007-07-03 | Method for packaging using resin |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN101101882A (en) |
GB (1) | GB2439837B (en) |
WO (1) | WO2008006299A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2937765A1 (en) * | 2008-10-27 | 2010-04-30 | Smart Packaging Solutions Sps | METHOD FOR MOUNTING PASSIVE COMPONENTS ON A PORTABLE OBJECT OF LOW THICKNESS, AND PORTABLE OBJECT THUS OBTAINED |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4481526A (en) * | 1980-06-17 | 1984-11-06 | Fujitsu Limited | Semiconductor device |
US5907477A (en) * | 1995-09-19 | 1999-05-25 | Micron Communications, Inc. | Substrate assembly including a compartmental dam for use in the manufacturing of an enclosed electrical circuit using an encapsulant |
FR2799306A1 (en) * | 1999-10-04 | 2001-04-06 | Gemplus Card Int | IC chip, especially having conductive side faces, is insulated by depositing a low viscosity insulating material on an active face surface portion between connection bumps |
US20020025607A1 (en) * | 2000-08-30 | 2002-02-28 | Tadatoshi Danno | Semiconductor device and a method of manufacturing the same |
WO2002031881A1 (en) * | 2000-10-13 | 2002-04-18 | Tyco Electronics Amp Gmbh | Electronic unit and process for the production thereof |
US6773961B1 (en) * | 2003-08-15 | 2004-08-10 | Advanced Semiconductor Engineering Inc. | Singulation method used in leadless packaging process |
US20050048259A1 (en) * | 2003-09-01 | 2005-03-03 | Norio Takahashi | Substrate frame |
US6870248B1 (en) * | 1999-06-07 | 2005-03-22 | Rohm Co., Ltd. | Semiconductor chip with external connecting terminal |
US20050184364A1 (en) * | 2004-02-23 | 2005-08-25 | Jeung-Il Kim | Lead frame for semiconductor package and method of fabricating semiconductor package |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3398580B2 (en) * | 1997-09-13 | 2003-04-21 | 株式会社東芝 | Semiconductor device manufacturing method and substrate frame |
JPH1197466A (en) * | 1997-09-18 | 1999-04-09 | Miyota Kk | Package method of ic chip |
JP4073098B2 (en) * | 1998-11-18 | 2008-04-09 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
WO2001026146A1 (en) * | 1999-10-01 | 2001-04-12 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
JP2002026182A (en) * | 2000-07-07 | 2002-01-25 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
JP3738176B2 (en) * | 2000-08-03 | 2006-01-25 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
-
2006
- 2006-07-05 CN CNA2006100615783A patent/CN101101882A/en active Pending
-
2007
- 2007-07-03 GB GB0712834.1A patent/GB2439837B/en not_active Expired - Fee Related
- 2007-07-04 WO PCT/CN2007/002067 patent/WO2008006299A1/en active Application Filing
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4481526A (en) * | 1980-06-17 | 1984-11-06 | Fujitsu Limited | Semiconductor device |
US5907477A (en) * | 1995-09-19 | 1999-05-25 | Micron Communications, Inc. | Substrate assembly including a compartmental dam for use in the manufacturing of an enclosed electrical circuit using an encapsulant |
US6870248B1 (en) * | 1999-06-07 | 2005-03-22 | Rohm Co., Ltd. | Semiconductor chip with external connecting terminal |
FR2799306A1 (en) * | 1999-10-04 | 2001-04-06 | Gemplus Card Int | IC chip, especially having conductive side faces, is insulated by depositing a low viscosity insulating material on an active face surface portion between connection bumps |
US20020025607A1 (en) * | 2000-08-30 | 2002-02-28 | Tadatoshi Danno | Semiconductor device and a method of manufacturing the same |
WO2002031881A1 (en) * | 2000-10-13 | 2002-04-18 | Tyco Electronics Amp Gmbh | Electronic unit and process for the production thereof |
US6773961B1 (en) * | 2003-08-15 | 2004-08-10 | Advanced Semiconductor Engineering Inc. | Singulation method used in leadless packaging process |
US20050048259A1 (en) * | 2003-09-01 | 2005-03-03 | Norio Takahashi | Substrate frame |
US20050184364A1 (en) * | 2004-02-23 | 2005-08-25 | Jeung-Il Kim | Lead frame for semiconductor package and method of fabricating semiconductor package |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2937765A1 (en) * | 2008-10-27 | 2010-04-30 | Smart Packaging Solutions Sps | METHOD FOR MOUNTING PASSIVE COMPONENTS ON A PORTABLE OBJECT OF LOW THICKNESS, AND PORTABLE OBJECT THUS OBTAINED |
WO2010049604A1 (en) * | 2008-10-27 | 2010-05-06 | Smart Packaging Solutions (Sps) | Method for mounting passive components on a portable object having a small thickness, and portable object thus obtained |
Also Published As
Publication number | Publication date |
---|---|
GB2439837B (en) | 2012-01-18 |
CN101101882A (en) | 2008-01-09 |
GB0712834D0 (en) | 2007-08-08 |
WO2008006299A1 (en) | 2008-01-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7665201B2 (en) | Method for manufacturing electronic modules | |
JP4510020B2 (en) | Manufacturing method of electronic module | |
CN100514583C (en) | Underlay embedded passive device | |
TWI482243B (en) | Wafer level applied thermal heat sink | |
US11081416B2 (en) | Configuring a sealing structure sealing a component embedded in a component carrier for reducing mechanical stress | |
JP5073756B2 (en) | Packaging for high thermal performance of circuit dies | |
TW201907530A (en) | Embedded power module with power coverage structure | |
US20080123318A1 (en) | Multi-component electronic package with planarized embedded-components substrate | |
CN107295747B (en) | Device carrier and method of manufacturing a device carrier | |
KR20010053088A (en) | Method of making an adhesive preform lid for electronic devices | |
US10806021B2 (en) | Packaged microelectronic component mounting using sinter attachment | |
US20080099903A1 (en) | Stacked chip package, embedded chip package and fabricating method thereof | |
CN107017211B (en) | Electronic component and method | |
GB2439837A (en) | Method for packaging an electronic component using resin | |
TWI576025B (en) | Substrate structure and fabrication method thereof | |
US20120018901A1 (en) | Flip-chip package and method of manufacturing the same using ablation | |
US20230317554A1 (en) | Embedded heat slug in a substrate | |
US12041721B2 (en) | Component carrier comprising at least two components | |
US8556159B2 (en) | Embedded electronic component | |
TWI714195B (en) | System-level semiconductor double-sided packaging circuit board with thermal stress resistance and manufacturing method | |
US20230074572A1 (en) | Electronic Module, Method for Producing an Electronic Module, and Industrial Plant | |
KR101205866B1 (en) | Manufacturing method of metal pcb and metal pcb thereof | |
KR20000040214A (en) | Method of planarizing surface of printed circuit board | |
JPH11224916A (en) | Semiconductor device, wiring board, and manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20130703 |