WO2008006299A1 - Procédé d'application d'un revêtement de conditionnement en résine sur un substrat - Google Patents
Procédé d'application d'un revêtement de conditionnement en résine sur un substrat Download PDFInfo
- Publication number
- WO2008006299A1 WO2008006299A1 PCT/CN2007/002067 CN2007002067W WO2008006299A1 WO 2008006299 A1 WO2008006299 A1 WO 2008006299A1 CN 2007002067 W CN2007002067 W CN 2007002067W WO 2008006299 A1 WO2008006299 A1 WO 2008006299A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- resin
- package unit
- package
- individual
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims abstract description 151
- 229920005989 resin Polymers 0.000 title claims abstract description 131
- 239000011347 resin Substances 0.000 title claims abstract description 131
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000012856 packing Methods 0.000 title abstract 7
- 239000011248 coating agent Substances 0.000 title abstract 2
- 238000000576 coating method Methods 0.000 title abstract 2
- 238000004806 packaging method and process Methods 0.000 claims description 38
- 239000002131 composite material Substances 0.000 claims description 20
- 238000001723 curing Methods 0.000 claims description 9
- 238000005538 encapsulation Methods 0.000 claims description 9
- 230000002262 irrigation Effects 0.000 claims description 7
- 238000003973 irrigation Methods 0.000 claims description 7
- 238000001179 sorption measurement Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000013007 heat curing Methods 0.000 claims description 3
- 238000006073 displacement reaction Methods 0.000 abstract description 13
- 238000000465 moulding Methods 0.000 abstract description 11
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 238000005336 cracking Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/3157—Partial encapsulation or coating
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Definitions
- the present invention relates to a substrate resin packaging method that can be mass-produced, and is mainly used for packaging of electronic devices. It is particularly suitable for packaging bare chips or semiconductor devices with resins on organic material substrates and composite dielectric substrates on a large scale, low cost, and high yield.
- Background Art In the current electronic device packaging engineering, there are a method of realizing a resin package of various electronic devices. ⁇ column is currently popular DIP, SOP, QFP, BGA, CSP package, recently developed MCM, SIP, SOP package.
- MCM and SIP packages are suitable for high-speed digital and high-frequency analog circuits and have been widely used in various system fields of communication, radar, navigation and home appliances.
- the MCM package integrates integrated circuit bare chips and other micro-components on the same high-precision high-rise substrate, and is packaged in the same resin or package to form a functional, reliable, and independent electronic component.
- MCM is an indispensable key technology for miniaturization, lightweight, high-speed, high-reliability, low-cost circuit integration of electronic equipment.
- the main difference between it and the traditional hybrid IC is that MCM uses bare chips, surface mount passive devices and multilayer wiring substrates, and achieves high-density interconnection.
- MCM and SIP packages are currently used for ceramic substrates at high frequencies.
- the ceramic substrate is packaged with high frequency, high temperature and deformation resistance, and good performance.
- the cost of using the ceramic substrate package is high, the manufacturing process is complicated, and the processing is complicated.
- the high-frequency characteristics of organic substrates and composite substrates have been greatly developed.
- the resin and the substrate are poorly attached during high-temperature molding, and peeling is likely to occur. . It has fatal flaws in the sealing and reliability of the device, and even completely eliminates the product.
- the low cost utilization of chip and component packages on organic and composite substrates is limited.
- the present invention proposes a substrate resin encapsulation method suitable for mass production. Can solve the above 3 ⁇ 4 problem better. SUMMARY OF THE INVENTION The present invention provides a substrate resin packaging method suitable for large scale, low cost, and high efficiency.
- a semiconductor device such as a packaged chip.
- the technical solution adopted by the present invention is: a substrate resin packaging method, comprising: a whole substrate, a bare object encapsulated on the whole substrate by a resin, and a separate resin packaging unit formed after packaging, in a whole substrate
- the plurality of bare objects are separately packaged to form a separate resin package unit, and the distance between the individual resin package units is kept at a certain distance.
- the independent resin package unit formed on the whole substrate is cut into independent Package unit.
- the exposed object is a semiconductor chip, a conductive line, a printed circuit, a resistor, an inductor, a capacitor, or a combination thereof.
- the entire substrate may be an organic dielectric substrate or a composite dielectric substrate.
- the individual resin package unit may be a package unit formed by a mold, a package unit formed by drip irrigation, or a package unit formed by adsorption.
- a substrate isolation hollow hole may be disposed between each of the independent resin package units on the entire substrate, and a small area connection is formed between the independent resin package units, and the connection may be in a separate resin package unit. At the top corner, it can also be in other locations.
- the curing process can be a high temperature heat curing or a room temperature curing.
- An injection molded resin package is applied to a plurality of individual bare objects on a single organic substrate or composite substrate.
- the thermal expansion coefficient CTE Coefficient of Thermal Expansion
- the thermal expansion coefficient CTE of the substrate on the X, Y, and ⁇ axes is different from the thermal expansion coefficient CTE of the resin on the X, Y, and x axis, and local cracking and peeling occur between the substrate and the resin. Maintain a certain distance between individual resin package units during the entire substrate design. Due to the existence of a certain separation distance, the absolute displacement of the resin of the independent resin package unit and the substrate of different thermal expansion coefficients becomes smaller when the resin is injected at a high temperature, and the displacement stress is less than the adhesion force. After high-temperature heating, the resin of the individual resin package unit and the substrate of different thermal expansion coefficients are not peeled off, and can be tightly bonded together.
- a hollow insulating hole may be formed between the individual resin packaging units on the entire substrate, but a small area connection is formed at a certain place between the independent resin packaging units, and the connection may be in a separate resin package. At the top corner of the unit, it can also be in other locations.
- the hollow holes can be of various shapes. The use of hollow holes can not only meet high-efficiency, low-cost stamping and slicing, but also can reduce the absolute displacement of the resin of the independent resin packaging unit and the substrate with different thermal expansion coefficients when the resin is injected into the high-temperature molding. After that, the resin of the independent resin package unit and the substrate having different thermal expansion coefficients are not peeled off, and can be tightly bonded together.
- the material properties of the substrate are not selected, and the substrate is selected.
- This substrate resin packaging method suitable for mass production is of great significance for the use of low-cost heat-deformable organic dielectric substrates and device packages on composite dielectric substrates.
- the present invention is suitable for low-cost scale production, even if the thermal expansion coefficient of the resin differs greatly from the thermal expansion coefficient between the organic medium substrate or the composite dielectric substrate, a method of resin encapsulation on the entire substrate can be performed in MCM, SIP. , SOP and other resin packages have a wide range of applications.
- the method of the invention is suitable for packaging most electronic components on the organic medium substrate and the composite dielectric substrate, and is suitable for low-cost, high-yield substrate resin packaging. .
- the substrate is isolated from the individual package units on the substrate to facilitate the slicing, and the peeling of the substrate and the resin is greatly reduced. Especially when considering high efficiency and low cost slicing, Stamping is an effective way.
- FIG. 1 is a schematic view showing a method of encapsulating a substrate resin according to the present invention.
- Fig. 2 is a schematic diagram showing the cracking and peeling of the resin and the substrate caused by the conventional multi-unit integrated packaging method on the entire organic medium substrate or the composite dielectric substrate.
- Fig. 3 is a packaging method in which a substrate isolation hollow hole 4 is formed between individual resin package units on a whole substrate.
- FIG. 4 is an example of a package unit in which a separate resin package unit is formed by a mold, a package unit formed by drip irrigation, and a package unit formed by adsorption.
- DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 1, this is a schematic view of a substrate resin encapsulation method of the present invention.
- Figure 1 (a) includes: a whole substrate, a bare object encapsulated on the whole substrate by a resin, and a separate resin package unit formed after packaging, and a plurality of bare objects are separated and packaged on one whole substrate to form an independent
- the resin packaging unit maintains a certain distance between the individual resin packaging units, and after curing, the individual resin packaging units formed on the entire substrate are cut into individual packaging units.
- Fig. 1(b) of the Al-A2 cross section of Fig. 1(a) that after high-temperature heating, the entire substrate is bent in the figure, deviating from the horizontal line A3-A4.
- Predetermined in the entire base by experiment and calculation The plates maintain a certain distance between the individual resin package units.
- An injection molded resin package is applied to a plurality of individual bare objects on a single organic substrate or composite substrate.
- the thermal expansion coefficient CTE (Coefficient of Thermal Expansion) of the substrate on the X, Y, and ⁇ axes is different from the thermal expansion coefficient CTE of the resin on the X, Y, and x axis, and local cracking and peeling occur between the substrate and the resin.
- FR-4 material substrate with a dielectric constant of 4.2 in the high-frequency substrate material currently used in mobile phones, which is fabricated on a 4-layer substrate.
- devices such as bare semiconductor chips, conductive lines, printed circuits, resistors, inductors, capacitors, etc., are packaged in a single unit.
- the thermal expansion coefficient of the FR-4 substrate in the X and Y directions is about 12 to 15 ppm/°C.
- the plate thickness Z direction will be expanded to 55 ⁇ 60ppm/°C without restraint.
- the epoxy resin has a thermal expansion coefficient of about 70 ppm/°C under the unconstrained directions of X, Y and ⁇ .
- the absolute displacement of the resin of the individual resin package unit 2 and the substrate of different thermal expansion coefficients becomes smaller at the time of resin injection high-temperature molding, and the displacement stress is less than the adhesion force. After the high-temperature heating molding, the resin of the individual resin package unit 2 and the entire substrate 1 having different thermal expansion coefficients are not cracked or peeled off, and the resin of the individual resin package unit 2 is tightly bonded to the substrate having different thermal expansion coefficients.
- the material properties of different substrates and the number of layers of the substrate are selected for low or high frequency applications, low density or high density packaging, power devices or non-power devices. , dielectric plate and copper plate thickness, wiring design and heat dissipation design.
- the above factors determine the thermal expansion coefficient of the substrate.
- the resin and the substrate with different thermal expansion coefficients must have a displacement force exceeding the adhesion force. Cracking and peeling.
- Fig. 2 is a schematic view showing the cracking and peeling of the resin and the substrate caused by the conventional multi-unit method on the entire organic medium substrate or the composite dielectric substrate before the implementation of the present invention.
- Figure 2 (a) shows the case where a plurality of unit methods are integrally packaged on a single organic medium substrate or a composite dielectric substrate.
- the large-area bulk-package resin 5 and the substrate are extremely susceptible to cracking and peeling due to the difference in thermal expansion coefficient.
- Fig. 3 is a packaging method in which a substrate isolation hollow hole 4 is formed between the individual resin package units 2 on the entire substrate 1. Thus, a small area of the substrate is formed somewhere between the individual resin package units, and the connection may be at the top corner of the resin package unit or at other locations.
- Figure 3 (a) is a side view
- Figure 3 (b) is a top view.
- the hollow holes 4 can be of various shapes.
- the hollow hole 4 is used to satisfy both high-efficiency and low-cost stamping slicing, and the absolute displacement of the resin of the independent resin encapsulating unit 2 and the substrate having different thermal expansion coefficients becomes small when the resin is injected at a high temperature.
- Figure 3 (c) is a cross-sectional view. It can be seen that after high-temperature heating, similar to the case of Figure 1 (b), the resin of the independent resin package unit and the substrate with different thermal expansion coefficients are not peeled off, and can be tightly combined. Together.
- the independent resin package unit 2 may be a package unit formed by a mold, and a package form formed by drip irrigation The package unit formed by the element or the ⁇ .
- FIG. 4(a) is an example of a cross-sectional view of a package unit in which the individual resin package unit 2 is formed by a mold
- FIG. 4(b) is a cross-sectional view of a package unit formed by drip irrigation
- FIG. 4(c) is a package unit formed by adsorption.
- the curing molding process may be high temperature heat curing or room temperature curing.
- the substrate resin packaging method suitable for the present invention can perform resin encapsulation on a whole substrate even if the thermal expansion coefficient of the resin differs greatly from the thermal expansion coefficient between the organic dielectric substrate or the composite dielectric substrate, and resin such as MM, SIP, SOP, etc.
- the package has a wide range of application values.
- the invention overcomes the disadvantages of poor resin-to-substrate adhesion during large-volume resin encapsulation on a whole substrate and high-temperature molding, and is prone to peeling phenomenon, and is suitable for substrate resin packaging for mass production.
- the ceramic substrate having a higher valence is suitable for packaging a plurality of electronic components on an organic dielectric substrate and a composite dielectric substrate by the method of the present invention, and is suitable for a low-cost, high-yield substrate resin package.
- the substrate isolated hollow holes between the individual package units on the substrate to facilitate slicing, and the peeling of the substrate and the resin is greatly reduced. Especially in the case of high efficiency, low cost slicing, stamping slicing is an effective way.
- the individual resin package unit can be adapted to various package forms on the substrate, such as a package unit formed by a mold, a package unit formed by drip irrigation, and a package unit formed by adsorption.
- the invention can be used as a resin encapsulation method suitable for a large-scale, low-cost, high-yield organic medium or composite dielectric substrate, and is widely used in industrial applications.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
L'invention concerne un procédé d'application d'un revêtement de conditionnement en résine sur un substrat, qui est en particulier utilisé pour sceller des éléments exposés sur un substrat composé d'un milieu organique ou de plusieurs milieux dans la production à grande échelle, à faible coût et à rendement élevé de produits finis. Le procédé de l'invention fait intervenir un substrat (1), des éléments exposés (6) conditionnés avec de la résine sur ledit substrat et une unité de conditionnement (2) en résine non fixée formée après le conditionnement. Lorsque plusieurs éléments exposés sont conditionnés avec de la résine non fixée sur le substrat, les espaces (3) formés entre chaque unité de conditionnement en résine non fixée représentent une certaine distance (d) par rapport au déplacement absolu et toutes les contraintes corporelles de la résine desdites unités et du substrat qui présente un coefficient de dilatation thermique différent sont réduites. La résine de l'unité de conditionnement non fixée et le substrat présentant le coefficient de dilatation thermique différent peuvent être raccordés à proximité l'un de l'autre après un procédé de moulage thermique haute température. Le procédé de l'invention est en particulier utilisé pour le conditionnement de puces exposées à grande échelle, et présente des coûts de conditionnement réduits et un rendement élevé pour des produits finis.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200610061578.3 | 2006-07-05 | ||
CNA2006100615783A CN101101882A (zh) | 2006-07-05 | 2006-07-05 | 基板树脂封装方法 |
Publications (1)
Publication Number | Publication Date |
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WO2008006299A1 true WO2008006299A1 (fr) | 2008-01-17 |
Family
ID=38421092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/CN2007/002067 WO2008006299A1 (fr) | 2006-07-05 | 2007-07-04 | Procédé d'application d'un revêtement de conditionnement en résine sur un substrat |
Country Status (3)
Country | Link |
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CN (1) | CN101101882A (fr) |
GB (1) | GB2439837B (fr) |
WO (1) | WO2008006299A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2937765B1 (fr) * | 2008-10-27 | 2010-12-17 | Smart Packaging Solutions Sps | Procede de montage de composants passifs sur un objet portable de faible epaisseur, et objet portable ainsi obtenu |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH1197466A (ja) * | 1997-09-18 | 1999-04-09 | Miyota Kk | Icチップのパッケージ方法 |
WO2001026146A1 (fr) * | 1999-10-01 | 2001-04-12 | Hitachi, Ltd. | Dispositif a semi-conducteur et son procede de fabrication |
US6326232B1 (en) * | 1998-11-18 | 2001-12-04 | Sanyo Electric Co., Ltd. | Method of fabricating semiconductor device |
CN1183585C (zh) * | 2000-07-07 | 2005-01-05 | 三洋电机株式会社 | 半导体器件的制造方法 |
CN1184680C (zh) * | 2000-08-03 | 2005-01-12 | 三洋电机株式会社 | 半导体器件的制造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS577144A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
US5612513A (en) * | 1995-09-19 | 1997-03-18 | Micron Communications, Inc. | Article and method of manufacturing an enclosed electrical circuit using an encapsulant |
JP3398580B2 (ja) * | 1997-09-13 | 2003-04-21 | 株式会社東芝 | 半導体装置の製造方法及び基板フレーム |
JP3339838B2 (ja) * | 1999-06-07 | 2002-10-28 | ローム株式会社 | 半導体装置およびその製造方法 |
FR2799306B1 (fr) * | 1999-10-04 | 2003-09-19 | Gemplus Card Int | Procede d'isolation de puce de circuit integre par depot de matiere sur la face active |
JP2002076040A (ja) * | 2000-08-30 | 2002-03-15 | Hitachi Ltd | 半導体装置及びその製造方法 |
EP1325518A1 (fr) * | 2000-10-13 | 2003-07-09 | Tyco Electronics AMP GmbH | Unite electronique et procede de production de ladite unite |
US6773961B1 (en) * | 2003-08-15 | 2004-08-10 | Advanced Semiconductor Engineering Inc. | Singulation method used in leadless packaging process |
JP2005079365A (ja) * | 2003-09-01 | 2005-03-24 | Oki Electric Ind Co Ltd | 基板フレーム及びこれを用いた半導体装置の製造方法 |
KR20050083322A (ko) * | 2004-02-23 | 2005-08-26 | 삼성테크윈 주식회사 | 반도체 패키지용 리이드 프레임과 이의 제조방법 |
-
2006
- 2006-07-05 CN CNA2006100615783A patent/CN101101882A/zh active Pending
-
2007
- 2007-07-03 GB GB0712834.1A patent/GB2439837B/en not_active Expired - Fee Related
- 2007-07-04 WO PCT/CN2007/002067 patent/WO2008006299A1/fr active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1197466A (ja) * | 1997-09-18 | 1999-04-09 | Miyota Kk | Icチップのパッケージ方法 |
US6326232B1 (en) * | 1998-11-18 | 2001-12-04 | Sanyo Electric Co., Ltd. | Method of fabricating semiconductor device |
WO2001026146A1 (fr) * | 1999-10-01 | 2001-04-12 | Hitachi, Ltd. | Dispositif a semi-conducteur et son procede de fabrication |
CN1183585C (zh) * | 2000-07-07 | 2005-01-05 | 三洋电机株式会社 | 半导体器件的制造方法 |
CN1184680C (zh) * | 2000-08-03 | 2005-01-12 | 三洋电机株式会社 | 半导体器件的制造方法 |
Also Published As
Publication number | Publication date |
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CN101101882A (zh) | 2008-01-09 |
GB2439837A (en) | 2008-01-09 |
GB2439837B (en) | 2012-01-18 |
GB0712834D0 (en) | 2007-08-08 |
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