CN1184680C - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN1184680C
CN1184680C CNB011247592A CN01124759A CN1184680C CN 1184680 C CN1184680 C CN 1184680C CN B011247592 A CNB011247592 A CN B011247592A CN 01124759 A CN01124759 A CN 01124759A CN 1184680 C CN1184680 C CN 1184680C
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semiconductor device
semiconductor chip
mentioned
location recognition
substrate
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CN1337739A (zh
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池谷浩司
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种半导体器件的制造方法，可以克服在通过以往的传递模塑制造单独的半导体器件的方法中，由于在传递模塑以后凌乱地分离为一个个半导体器件，因此需要使各个半导体器件对准一定的方向单独地进行特性的测定，增加多余的工艺并且浪费时间的缺点。本发明在粘贴在粘合片的状态下测定一个个半导体器件40的特性。这时，一个个半导体器件40沿一定方向对准并排列，进而，用照相机视野53捕捉半导体器件40a进行位置识别，省略与半导体器件40a相邻接的半导体器件40b、40c、40d、40e的位置识别工艺。具有大幅度地缩短作业时间而且提高生产性的特征。

Description

半导体器件的制造方法
技术领域
本发明涉及半导体器件的制造方法，特别是涉及用去引线缩小封装外形减少安装面积，能够大幅度降低成本的半导体器件的制造方法。
背景技术
在半导体器件的制造中，进行以下的工艺，判断形成在晶片上的一个个半导体芯片是否良好，把从晶片切割分离了的半导体芯片固定在引线框上，通过由模具和树脂注入进行的传递模塑把固定在引线框上的半导体芯片密封，把被密封了的半导体芯片分离为一个个半导体器件。该引线框使用矩形或者环形的框，在每一种情况下都是在一次密封工艺中同时密封多个半导体器件。
图13示出形成在晶片上的半导体芯片的检查工艺。在该工艺中，判断形成在晶片上的一个个半导体芯片1的优良与不良。首先，进行晶片的位置确认，探针的针14被送出芯片尺寸的距离，接触各个半导体芯片1的电极焊盘。而且，在该状态下，预先从输入电极焊盘输入被程序化了的输入信号波形，从输出端子输出一定的信号波形，测试器读取该信号进行优良、不良的判断。这里，被判断为不良的半导体芯片1被打印标记，在把半导体芯片1固定在引线框上的时候，确认用照相机识别该打印标记去除不良的半导体芯片1。
图14示出传递模塑工艺。在传递模塑工艺中，把通过芯片粘合，线粘合固定了半导体芯片1的引线框2设置在由上下模具3A、3B形成的空腔4的内部，通过在空腔4内注入环氧树脂，进行半导体芯片1的密封。在这样的传递模塑工艺以后，把引线框2按照各个半导体芯片1切断，制造单独的半导体器件(例如特开平05-129473号)。
这时，如图15所示，在模具3B的表面设置多个空腔4a～4f，用于输入树脂的树脂源5，横浇口6以及用于从横浇口6向各个空腔4a～4f流入树脂的浇口7。这些全部是设置在模具3B表面上的槽。如果是矩形的引线框，则在一个引线框上搭载10个半导体芯片1，对应于一个引线框，设置10个空腔4和10个浇口7以及1个横浇口6。而且，在模具3表面上例如设置与20个引线框相当的空腔4。
在传递模塑以后从引线框切断各个半导体芯片1，分离为一个个半导体器件。该一个个半导体器件进而在测定工艺中按特性差(hfe级别差)分类，捆扎后出厂。
图16示出通过上述的传递模塑制造的半导体器件。形成了晶体管等元件的半导体芯片1在引线框的岛8上由焊锡等焊料9固定安装，用线11连接半导体芯片1的电极焊盘与引线10。半导体芯片1的周边部分由与上述空腔形状一致的树脂12覆盖，在树脂12的外部导出引线端子10的前端部分。
在以往的通过传递模塑制造单独的半导体器件的方法中，由于在传递模塑后分离为各个半导体器件而比较凌乱，因此需要使各个半导体器件沿一定的方向聚齐个别地进行特性的测定，具有要求过多的工艺并且浪费时间的缺点。
发明内容
本发明是鉴于上述的问题而产生的，其目的在于提供一各可克服上述缺点的半导体器件的制造方法，本发明的特征在于在把搭载了多个半导体芯片的陶瓷或者玻璃环氧等构成的绝缘基板粘贴在粘合片上的状态下，切割以后不分离为单个的半导体器件，用识别用照相机把一个半导体器件的基板电极进行位置识别，对其位置识别了的半导体器件进行特性(hfe级别差)的判断，同时对位于其周围的的多个半导体器件不进行位置识别而进行特性(hfe级别差)的判断。
另外本发明中的特征在于，由于使用由陶瓷或玻璃环氧等构成的绝缘基板，因此伸缩率比以往的硅基板增大，极板间的间隔将产生微小的偏移，因此通过遮挡把识别用照相机的视野取为一个半导体器件的大小，能够更进一步提高位置识别的精度。另外，不仅如此，通过减小位置识别的面积能够实现缩短位置识别时间。
进而本发明的特征在于，固定进行半导体器件测定时使用的识别用照相机和探针的针的位置，使形成了半导体器件的基板移动。由此，由于提高位置识别的精度，还将提高作业速度，因此能够极其容易而且大量地进行半导体器件的特性测定。而且，通过识别一个半导体芯片的电极焊盘，从图形处理装置取入来自目标位置的偏移，加入其偏移部分，使下一个半导体芯片移动，由此能够经常边修正位置偏移边进行位置识别。
附图说明
图1是用于说明本发明的制造方法的透视图。
图2是用于说明本发明的制造方法的(A)平面图(B)剖面图。
图3是用于说明本发明的制造方法的平面图。
图4是用于说明本发明的制造方法的剖面图。
图5是用于说明本发明的制造方法的(A)剖面图(B)剖面图。
图6是用于说明本发明的制造方法的(A)剖面图(B)平面图。
图7是用于说明本发明的制造方法的(A)剖面图(B)平面图。
图8是用于说明本发明的制造方法的(A)剖面图(B)平面图。
图9是用于说明本发明的制造方法的(A)平面图(B)剖面图。
图10是用于说明本发明的制造方法的(A)剖面图(B)平面图。
图11是用于说明本发明的制造方法的(A)平面图(B)剖面图(C)剖面图。
图12是用于说明本发明的制造方法的(A)透视图(B)透视图
图13是用于说明以往例的平面图。
图14是用于说明以往例的剖面图。
图15是用于说明以往例的平面图。
图16是用于说明以往例的剖面图。
发明的具体实施方式
以下详细地说明本发明的实施形态。
本发明的第1工艺如从图1至图3所示，准备具有多个搭载部分的基板。
首先，如图1所示，准备排列了多个对应于1个半导体器件的搭载部分20的，例如，以10行10列纵横排列了100个的大块基板21。基板21是由陶瓷或玻璃环氧等制成的绝缘基板，把它们的一片或者多片重叠起来，具有总计板厚200～350μm可以维持制造工艺中的机械强度的板厚。
在基板21的各个搭载部分20的表面上，形成钨等金属胶的印刷和通过金的电镀形成的导电图形。另外，在基板21的背面一侧，形成作为外部连接电极的电极图形。
图2(A)是示出形成在基板21表面的导电图形的平面图，图2(B)是基板21的剖面图。
用虚线包围的各个搭载部分20例如具有长边×短边1.0mm×0.8mm的矩形形状，它们相互隔开20～50μm的间隔纵横地排列。上述间隔成为后述工艺中的切割线24。导电图形在各个搭载部分20内形成岛形部分25和引线部分26，这些图形在各个搭载部分20内是相同形状。岛形部分25是搭载半导体芯片的位置，引线部分26是与半导体芯片的电极焊盘线连接的位置。从岛形部分25以2条第1连接部分27连接了的图形延长。它们的线宽比岛形部分25窄，例如以0.1mm线宽延长。第1连接部分27跨过切割线24与相邻的搭载部分20的引线部分26连接。进而，从引线部分26各个第2连接部分28沿着与第1连接部分27垂直的方向延伸，跨过切割线24与相邻的搭载部分20的引线部分26连接。第2连接部分28进而连接包围搭载部分20群的周围的共同连接部分29。这样通过第1和第2连接部分27，28延伸，把各个搭载部分20的岛形部分25与引线部分26电气地共同连接起来。这是为了在进行金等电镀时作为共同电极。
参照图2(B)，在绝缘基板21上，在每个搭载部分20中设置通孔30。通孔30的内部埋设钨等导电材料。而且，对应于各个通孔30，在背面一侧形成外部电极31。
图3是示出了从背面一侧观测基板21时外部电极31a～31d的图形的平面图。这些外部电极31a、31b、31c、31d从搭载部分20的边缘后退0.05～0.1mm左右，而且以各自独立的图形形成。尽管如此，在电气上经过各个通孔30连接到共同连接部分29。由此，在把导电图形作为一个电极的电镀法中，能够在所有的导电图形上形成镀金层。另外，横断切割线24能够只作成线宽窄的第1和第2连接部分27，28。
本发明的第2工艺如图4所示，是在搭载部分的每一个上固定半导体芯片，进行线连接。
形成了镀金层的基板21的各个搭载部分20，把半导体芯片33进行芯片粘合或者线粘合。半导体芯片33在岛形部分25的表面上由Ag胶等粘接剂固定，用各条线34连接半导体芯片33的电极焊盘与引线部分32a，32b。作为半导体芯片33，形成双极型晶体管，功率MOSFET等3端子的有源元件。搭载了双极型元件的情况下，连接在岛形部分25的外部电极31a，31b是集电极端子，连接在引线部分26的外部电极31c，31d成为基极·发射极电极。
其次，本发明的第3工艺如图5所示，用树脂层覆盖基板表面，用共同的树脂层覆盖固定在各个搭载部分的半导体芯片的每一个。
如图5(A)所示，从移动到基板21上方的调合器(未图示)滴下一定量的环氧系列液体树脂(浇注封装)，用共同的树脂层35覆盖所有的半导体芯片33。例如，在一片基板21上搭载了100个半导体芯片33的情况下，把所有的100个半导体芯片33一起覆盖。作为上述液体树脂，使用例如CV576AN(松下电工制)。滴下的液体树脂由于粘度比较高，具有表面张力，因此其表面弯曲。
接着，如图5(B)所示，把滴下的树脂层35通过100～200度，数小时的热处理(热化)使其硬化以后，通过磨削弯曲面把树脂层35的表面加工为平坦面。磨削使用切割装置，由切割刀片36切削树脂层35的表面使树脂层35的表面取齐并且从基板21高出一定的高度。在该工艺中，把树脂层35的膜厚形成为0.3～1.0mm。平坦面扩张到其端部，使得在至少把位于最外侧的半导体芯片33分离为单独的半导体器件时，可以构成为标准化的封装尺寸的树脂外形。上述刀片中准备多种板厚的刀片，使用比较厚的刀片，通过反复进行切削，把总体形成平坦面。
另外，也可以考虑在把滴下的树脂层35硬化之前，在树脂层35的表面按压平坦的成形材料形成平坦而且水平的面，然后进行硬化的方法。
其次，本发明的第4工艺如图6所示，使树脂层35搭接到基板21上，粘贴粘合片50。
如图6(A)所示，把基板21反转，在树脂层35的表面上粘贴粘合片50(例如，商品名称：UV片，リンテツク株式会社制)。通过在前面的工艺中把树脂层35表面加工成平坦而且对于基板21的表面为水平的面，因此即使粘贴在树脂层35一侧也能够使基板21不倾斜，维持其水平垂直的精度。
如图6(B)所示，在不锈钢制环形金属框51上粘贴粘合片50的周边，在粘合片50的中央部分设置间隔粘贴6个基板21。
其次，本发明的第5工艺如图7所示，从基板的背面一侧，在每个搭载部分，切割基板和树脂层，分离为一个个半导体器件。
如图7(A)所示，在每个搭接部分20切断基板以及树脂层35分离为各个半导体器件。切割使用切割装置的切割刀片36，沿着切割线24同时切割树脂层35和基板21，由此形成在每个搭载部分20分割了的半导体器件。在切割工艺中上述切割刀片36以达到粘合片50的表面的切削深度进行切割。这时，在切割装置一侧能够从基板21的背面一侧自动识别能够观测的标志(例如，形成在基板21的周边部分的贯通孔或者镀金层的一部分)，以其作为基准进行切割。另外，电极图形31a，31b，31c，31d或者岛形部分25采用不接触切割刀片36的图形设计。其目的是因为镀金层的切断性比较差，因而尽量防止产生镀金层毛边。从而，切割刀片36与镀金层接触的部分仅是以导电为目的的第1和第2连接部分27，28。
如图7(B)所示，四边粘贴在金属框51上的粘合片50上所粘贴的多片基板21按照每一片识别切割线24，用切割装置沿着纵方向的各条切割线24进行分离，接着把金属框51旋转90度沿着行方向的各条切割线24进行分离。通过切割被分离了的各个半导体器件用粘接剂以其原来的状态粘贴到粘合片50上，而不是被单个散乱地分离。
其次，本发明第6工艺是作为本发明特征的工艺，如图8(A)，(B)所示，进行被一体地支撑在粘合片50上的切割后的各个半导体器件特性的测定。
如图8(A)所示，在从被一体地支撑在粘合片50上的各个半导体器件的基板21露出到背面一侧的外部电极31a～31d上接触探针的针52，单个测定各个半导体器件的特性参数进行优良与不良以及不同特性(hfe等级差)的判断。由于基板21使用陶瓷或者玻璃环氧等构成的绝缘基板，因此考虑到在制造工艺中由于伸缩引起的基板大小的分散性或者为了用粘合片50支撑产生的微小位置偏移，检测外部电极31a～31d的位置偏移，在进行位置修正的同时使探针的针52接触外部电极31a～31d进行测定。
如图8(B)所示，由于在金属框51上粘贴着多片基板21，在切割工艺的状态下支撑着单个的半导体器件，因此可以不需要半导体器件正反面的判断以及外部电极的发射极、基极、集电极等的类别或者方向的判断。该测定按各个基板21沿着箭头方向一行行地顺序进行，如果到达边缘部分则返回到起始端后移动到下一行。金属框51边进行一个半导体器件的尺寸部分的位置修正边向行方向生成给进间距，如果到达边缘部分则沿着列方向移动，再次向行方向生成给进间距，由此能够极其容易地大量地进行。
具体地讲，如图9(A)以及(B)所示，识别用照相机54把半导体器件40a捕捉到照相机视野53的中心进行位置识别，这时，照相机视野53除去多个半导体器件40a以外同时捕捉其周围的半导体器件40b，40e等。然而，在该识别用照相机54的透镜中，进行遮挡使得照相机视野53的中心中成为一个半导体器件部分的视野。因此，照相机视野53能够可靠地捕捉半导体器件40a，能够进一步提高位置识别的精度。特别是，由于很小地密集形成半导体器件40的尺寸，因此位置识别多少有偏移，由于在与周围的半导体器件的同时测定时将产生干扰，所以位置识别的精度很重要。
而且，在首先进行半导体器件40c的位置识别，进行了位置修正以后，探针的针52接触相邻的半导体器件40b，40c，40d，40e的电极焊盘，测定这些半导体器件的特性。这时，承认周围的半导体器件40b，40c，40d，40e的位置识别具有允许范围内的位置偏移而省略，由于仅进行特性的测定因此带来生产性的提高。
其次，在半导体器件40b，40c，40d，40e的测定中位置识别下一个进行测定的半导体器件40a检测微小的位置偏移。修正该位置偏移使探针的针52接触包括下一个半导体器件40a在内的与其周围相邻的多个半导体器件的电极焊盘，测定这些半导体器件的特性。把该作业反复了一列以后，跳过一列在下一列进行相同的作业。通过该作业的反复进行测定1个基板21的所有半导体器件40的特性。半导体器件40的测定结果存储在测试器的存储器中，把该测定结果移送到软盘中，在以后的工艺作业中使用。
在测定的半导体器件40的特性的作业中，固定识别用照相机54以及探针的针52的位置。而且，通过移动固定半导体器件40的金属框51，进行该作业。而且，在位置识别作业中，识别1个半导体器件40的电极焊盘，从图像处理装置取入来自目标位置的偏移量加入其偏移量部分，使下一个半导体器件40移动。
这里，叙述了位置识别1个半导体器件，进行与该半导体器件相邻的4个半导体器件的特性测定的情况，当然并不特别必须是4个装置，能够不进行位置识别而进行最多10个半导体器件的特性测定。
进而，本发明的第7工艺如图9所示，直接把一体地支撑在粘合片50上的各个半导体器件40收容在承载带41上。
如图10(A)所示，一体地支撑在粘合片50上的测试完毕的各个半导体器件识别测定数据，通过吸附筒夹53从粘合片50脱离而收容到承载带41的收容孔内。
如图10(B)所示，由于在金属框51上粘贴着多片基板21，在切割的状态下支撑单个半导体器件40，因此在向承载带41收容时可以使金属框51仅移动到所需要的半导体器件40的位置，能够以所需要的最小限度的动作进行，因此能够极其容易地而且大量地进行。
图11示出在本工艺中使用的承载带的(A)平面图(B)AA线剖面图(C)BB线剖面图。带本体41是膜厚0.5～1.0mm，宽度6～15mm，长度数十m的带形的部件，材料是瓦楞纸板那样的纸。在带本体41上以一定的间隔穿设贯通孔42。另外，形成用于以一定的间隔送出带本体41的送进孔43。该贯通孔42和送进孔43通过模具冲压加工形成。带本体41的膜厚与贯通孔42的尺寸设计成能够收容要捆扎的电子部件40的大小。
在带本体41的背面一侧，粘贴透明薄膜形的第1条带44并且填塞贯通孔42的底部。在带本体41的表面一侧，同样粘贴透明薄膜形的第2条带45并且填塞贯通孔43的上部。第2条带45以侧面部分附近的粘贴部分46与带本体41粘贴。另外，第1条带44也在与第2条带45相同的位置与带本体41粘贴。它们的粘贴从薄膜上部通过用具有对应于粘贴部分46的加热部分的部件热压进行，这是通过两者都拉引薄膜而能够剥离的状态下的粘贴。
最后，图12是示出根据上述的工艺完成的各半导体器件的透视图。在封装周围4侧面由树脂层35和基板21的剖面形成，封装的上面由平坦化的树脂层35的表面形成，封装的下面由绝缘基板21的背面一侧形成。
该半导体器件的长×宽×高具有例如1.0mm×0.6mm×0.5mm这样的大小。在基板21上面覆盖0.5mm左右的树脂层35，密封半导体芯片33。半导体芯片33具有大约150μm左右的厚度。岛形部分25与引线部分26从封装的端面后退，仅第1与第2连接部分27、28的切断部分露出到封装侧面。
外部电极31a～31d在基板21的4个角，以0.2×0.3mm左右的大小排列，对于封装外形的中心线以成为左右(上下)相对的图形排列。这种对称排列由于难以进行电极的极性判断，因此最好是在树脂层35的表面一侧形成或者印刷凹部等，刻印表示极性的标记。
由上述制造方法形成的半导体器件由于汇集多个元件用树脂封装，因此与一个个封装的情况相比较，能够减少无用的树脂材料，降低材料费。另外，由于不使用引线框，因此与以往的传递模塑方法相比较，能够大幅度减小封装外形。进而，由于外部连接用的端子形成在基板21的背面，并且不从封装外形突出，因此能够大幅度减小装置的安装面积。
进而，上述制造方法不是在基板21一侧而是在树脂层35一侧粘贴粘合片50进行切割。例如粘贴在基板21一侧的情况下，在剥离元件时粘合片50的粘接剂附着在电极图形31a～31d的表面。如果在这种粘接剂残留的状态下把元件投入到自动安装装置中，则具有使安装时的电极图形31a～31d的焊接特性恶化的危险。另外，还有在电极图形31a～31d表面粘附灰尘的危险。而如果依据本发明，通过粘贴在树脂层35一侧能够消除这些弊端。
进而，在树脂层35一侧粘贴粘合片50时，通过把树脂层35的表面加工成水平而且平坦的面，能够维持与在基板21一侧粘贴粘合片50时相同的垂直水平精度。
另外，在上述实施例中说明了密封3端子元件形成4个外部电极的例子，而例如在密封2个半导体芯片或者密封集成电路的情况下也同样能够加以实施。
发明效果
如果依据本发明，则第1，在半导体器件的特性测定作业中，特征在于首先用识别用照相机识别一个半导体器件，并且不识别与该半导体器件相邻接的多个半导体器件而测定半导体器件的特性。由此，能够缩短半导体器件的位置识别中的作业时间，能够实现极其富有批量生产性的半导体器件的制造方法。
第2，虽然识别用照相机在半导体器件的电极焊盘进行位置识别，然而由于通过遮挡使得识别用照相机的视野在狭窄到一个半导体器件大小的状态下进行位置识别，因此能够实现进一步提高了半导体器件的位置识别精度的半导体器件的制造方法。
第3，在测定半导体器件的特性的作业中，固定识别用照相机以及探针的针的位置，通过固定着半导体器件的金属框移动，进行该作业。因此，在位置识别作业中，识别一个半导体器件的电极焊盘，从图像处理装置取入来自目标位置的偏移量，加入其偏移部分使下一个半导体器件移动，因此能够实现进一步提高了半导体器件的识别位置精度的半导体器件的制造方法。

Claims (4)

1.一种半导体器件的制造方法，在具有多个装配部分的基板的该装配部分的每一个上固定半导体芯片，用共同的树脂层把固定在上述各装配部分的上述半导体芯片的每一个覆盖以后，把上述树脂层粘贴在粘合片上，并把上述基板与上述树脂层进行切割，在没有切离上述粘合片的状态下进行测定，其特征在于：
对上述半导体芯片之一的上述基板的外部电极进行位置识别，并且测定进行了位置识别的上述半导体芯片，同时对位于其周围的多个半导体芯片不进行位置识别而进行测定。
2.如权利要求1中所述的半导体器件的制造方法，其特征在于：
上述半导体芯片中，测定进行了位置识别的半导体芯片，同时对位于其周围的3个上述半导体芯片不进行位置识别而进行测定。
3.如权利要求1中所述的半导体器件的制造方法，其特征在于：
测定上述半导体芯片时，固定识别用照相机以及探针的位置，移动上述半导体芯片进行测定。
4.如权利要求3中所述的半导体器件的制造方法，其特征在于：
上述识别用照相机在上述半导体芯片的上述基板的外部电极进行位置识别时，上述识别用照相机的视野在通过遮挡狭窄到一个半导体芯片大小的状态下进行位置识别。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008006299A1 (fr) * 2006-07-05 2008-01-17 Yuejun Yan Procédé d'application d'un revêtement de conditionnement en résine sur un substrat

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3610887B2 (ja) * 2000-07-03 2005-01-19 富士通株式会社 ウエハレベル半導体装置の製造方法及び半導体装置
JP2002026182A (ja) * 2000-07-07 2002-01-25 Sanyo Electric Co Ltd 半導体装置の製造方法
JP3619773B2 (ja) * 2000-12-20 2005-02-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3958532B2 (ja) * 2001-04-16 2007-08-15 ローム株式会社 チップ抵抗器の製造方法
US6884663B2 (en) * 2002-01-07 2005-04-26 Delphon Industries, Llc Method for reconstructing an integrated circuit package using lapping
US6905891B2 (en) * 2002-02-28 2005-06-14 Frrescale Semiconductor, Inc. Method for processing multiple semiconductor devices for test
US20030209847A1 (en) * 2002-05-10 2003-11-13 Allison Claudia Leigh Handling device comprising multiple immobilization segments
US20110005667A1 (en) * 2002-05-10 2011-01-13 Delphon Industries LLC Multiple segment vacuum release handling device
US6983872B2 (en) * 2003-06-03 2006-01-10 Asm Assembly Automation Ltd. Substrate alignment method and apparatus
JP4280177B2 (ja) * 2004-02-25 2009-06-17 日東電工株式会社 基板処理装置の除塵部材
US7507638B2 (en) * 2004-06-30 2009-03-24 Freescale Semiconductor, Inc. Ultra-thin die and method of fabricating same
JP2007096196A (ja) * 2005-09-30 2007-04-12 Renesas Technology Corp 半導体装置の製造方法
CN103000768A (zh) * 2011-09-09 2013-03-27 展晶科技(深圳)有限公司 发光二极管封装结构的制造方法
US8710859B2 (en) * 2011-09-23 2014-04-29 Powertech Technology Inc. Method for testing multi-chip stacked packages
DE102011056706B4 (de) * 2011-12-20 2016-12-15 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen, Anordnung und optoelektronisches Halbleiterbauteil
US10105927B1 (en) 2013-03-15 2018-10-23 Delphon Industries, Llc Silicone-free thermoplastic elastomer (TPE) materials for use in carrier devices
TW201445644A (zh) * 2013-05-24 2014-12-01 矽品精密工業股份有限公司 半導體封裝件之製法
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541525A (en) * 1991-06-04 1996-07-30 Micron Technology, Inc. Carrier for testing an unpackaged semiconductor die
JPH05142296A (ja) * 1991-07-01 1993-06-08 Inter Tec:Kk 半導体素子検査方法及び半導体素子検査装置
JPH05129473A (ja) 1991-11-06 1993-05-25 Sony Corp 樹脂封止表面実装型半導体装置
US6048750A (en) * 1997-11-24 2000-04-11 Micron Technology, Inc. Method for aligning and connecting semiconductor components to substrates
JP3819574B2 (ja) * 1997-12-25 2006-09-13 三洋電機株式会社 半導体装置の製造方法
JP2000114204A (ja) * 1998-10-01 2000-04-21 Mitsubishi Electric Corp ウエハシート及びこれを用いた半導体装置の製造方法並びに半導体製造装置
JP3710942B2 (ja) * 1998-10-20 2005-10-26 三洋電機株式会社 半導体装置の製造方法
JP3877454B2 (ja) * 1998-11-27 2007-02-07 三洋電機株式会社 半導体装置の製造方法
JP2000162275A (ja) * 1998-12-01 2000-06-16 Fujitsu Ltd 半導体試験方法及び半導体試験装置
JP4803855B2 (ja) * 1999-02-09 2011-10-26 三洋電機株式会社 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008006299A1 (fr) * 2006-07-05 2008-01-17 Yuejun Yan Procédé d'application d'un revêtement de conditionnement en résine sur un substrat

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