CN1577798A - 制造半导体器件的方法和使用该方法的半导体器件制造装置 - Google Patents

制造半导体器件的方法和使用该方法的半导体器件制造装置 Download PDF

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Publication number
CN1577798A
CN1577798A CNA2004100597729A CN200410059772A CN1577798A CN 1577798 A CN1577798 A CN 1577798A CN A2004100597729 A CNA2004100597729 A CN A2004100597729A CN 200410059772 A CN200410059772 A CN 200410059772A CN 1577798 A CN1577798 A CN 1577798A
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array substrates
substrate
semiconductor device
many array
many
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CN100370595C (zh
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山口嘉彦
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Renesas Eastern Japan Semiconductor Inc
Renesas Electronics Corp
Renesas Semiconductor Package and Test Solutions Co Ltd
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Renesas Technology Corp
Renesas Northern Japan Semiconductor Inc
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Abstract

一种半导体器件制造装置包括预对准部分,其具有适合于识别在多阵列基片上形成的识别标记的预对准相机,切割部分,其根据由预对准部分对标记的图象识别获得的信息用切刀切割基片,和xy台,其携带基片。预对准部分根据图象识别预先识别基片上的所有标记,借此确定切割位置,而切割部分仅仅用对准相机识别基片上的几个点。结果,预对准和切割能够同时发生,从而能够提高切割处理的产量。

Description

制造半导体器件的方法和 使用该方法的半导体器件制造装置
相关专利申请相互参考
本专利申请要求获得日本专利申请JP 2003-194955的优先权,其于2003年7月10日提出申请并在本专利申请中引用其内容作为参考。
技术领域
本发明涉及半导体器件制造技术,特别地,涉及用于提高块模制处理之后切片处理(dicing process)产量的技术。
背景技术
传统的切割(切片)方案是基于在基片上与布线图形的形成同时地并且以相同的方式形成参考分割标记,其中在基片上集成有多个电子部件,并根据该参考标记将基片切割成单个的电子器件,如拟公开日本专利申请No.Hei 11(1999)-274357(图4所示)。
由多个电子部件在未形成树脂的母片上形成的传统电子器件具有用于切割的标记,如拟公开日本专利申请No.2002-246336所示(图2)。
发明内容
本发明的发明人用多阵列基片(multi-arrayed substrate)研究了半导体器件的制造,其中基片在树脂密封之后被切割成单个的器件,并且发现了如下的问题。
在树脂密封之后的基片切割中,需要自动地识别表示切割位置的对准标记。由于标记识别和切割处于同一阶段,这些操作又不能同时发生,导致生产率降低。
减少自动识别点的数目意图加速标记的识别会导致切割位置精度的降低。在基于多层基片的多阵列基片实例中,内部布线的宽度和位置显著地不一致,切割位置精度的降低很可能会导致布线间的短路。
特别地,为了处理更多的信号针而增加布线层很可能导致布线间短路。因此,作为自动识别点数目减少的结果,处理精度不可避免地降低。
在很多情况下,通过成本相对低廉的电解电镀来电镀布线,而该电镀处理必需在每个布线层上具有电力馈给布线。电力馈给布线必须在树脂密封之后进行的切割中无误地加以切割。增加布线层以处理更多的信号针,以及类似的,会增大各层之中电力馈给布线的位置误差,导致布线层之间短路的可能性增加。
本发明的一个目的是提供一种能够提高切割处理产量的半导体器件制造方法和一种执行该方法的半导体器件制造装置。
本发明的另一个目的是提供一种能够提高切割精度的半导体器件制造方法和一种执行该方法的半导体器件制造装置。
本发明的这些和其它目的以及创新特点从随后的说明和附图中将变得显而易见。
在本专利说明书中公开的本发明中,典型地简述如下。
本发明在于一种半导体器件制造方法,其包括如下步骤:制备多个多阵列基片,将多个半导体芯片安装在多阵列基片上,对多阵列基片上的半导体芯片进行树脂密封,和对经过树脂密封的多阵列基片中的第一多阵列基片执行图象识别,之后切割该第一多阵列基片,同时执行第二多阵列基片的图象识别。
本发明在于一种半导体器件制造方法,其使用第一处理部分、第二处理部分和输送装置(conveyance means),其中第一处理部分具有成像装置,其适合于识别在具有多个半导体器件形成区域的多阵列基片上形成的标记,第二处理部分用于根据从第一处理部分的图象识别获得的信息用切刀切割多阵列基片,输送装置用于在第一和第二处理装置之间运送多阵列基片,该方法能够同时执行在第二处理部分内对第一多阵列基片的切割和在第一处理部分内对第二多阵列基片的图象识别。
附图说明
图1是显示半导体器件制造装置(组合装置)结构的平面图,其根据本发明的第一实施例执行半导体器件制造方法;
图2是显示图1所示半导体器件制造装置主要部分结构的部分前视图;
图3是显示处理工具的剖面图,其用于图1所示的半导体器件制造装置;
图4是显示多阵列基片芯片安装表面结构的平面图,其用于第一实施例的半导体器件制造方法;
图5是显示图4所示多阵列基片封装表面结构的平面图;
图6是图4所示基片的芯片安装表面器件区域内导电图形的放大平面图;
图7是图5所示基片的封装表面器件区域内导电图形的放大平面图;
图8是显示基于第一实施例变型的多阵列基片芯片安装表面结构的平面图;
图9是显示图8所示多阵列基片封装表面结构的平面图;
图10是显示在根据本发明的第一实施例开始制造半导体器件时基片结构的剖面图;
图11是显示在根据本实施例制造半导体器件期间单元片(die)键合时基片结构的剖面图;
图12是显示在根据本实施例制造半导体器件期间丝线键合时基片结构的剖面图;
图13是显示在本实施例的半导体器件制造期间块模制时基片结构的部分剖面图;
图14是显示在本实施例的半导体器件制造期间球安装(ballmounting)时基片结构的剖面图;
图15是显示在本实施例的半导体器件制造期间球清洗(ballcleaning)时基片结构的剖面图;
图16是显示在本实施例的半导体器件制造期间切割时基片结构的剖面图;
图17是显示根据本发明的第一实施例通过半导体器件的切割处理隔离的半导体器件结构的透视图;
图18是显示组合装置处理时限的时限图,该组合装置执行本发明第一实施例的半导体器件制造方法;
图19是显示根据本实施例进行切割时刀片宽度和电镀电力馈给布线之间位置关系的剖面图和后表面布线图系列;
图20是显示根据第一实施例变型的半导体器件结构的剖面图;
图21是显示根据本发明的第二实施例执行半导体器件制造方法的半导体器件制造系统(分离装置)结构的框图;和
图22是显示基于第二实施例变型的半导体器件制造系统布置的框图。
具体实施方式
在随后的实施例说明中,除非认为需要,否则不再重复解释相同或类似的部分。
尽管本发明是通过适宜地或者在需要时将其分割成数个部分或实施例加以说明的,但是这些划分彼此相关,也就是说,除非明确声明,否则一个是另一个的不同的详细说明或者补充说明。
在下面的实施例说明中,元件的数目、数字数值、数量和范围不是绝对的,除非明确说明或者从原理上显见,否则它们能够被放大或缩小。
本发明的实施例将参考附图详细地加以说明。纵观附图,具有相同功能的项目用共同的符号指代,并且不重复加以说明。
实施例1:
图1以平面图的形式显示了执行根据本发明第一实施例的半导体器件制造方法的半导体器件制造装置(组合装置)的结构,图2以部分前视图的形式显示了图1所示半导体器件制造装置原理部分的结构,图3以剖面图的形式显示了图1所示半导体器件制造装置所用处理工具的结构,图4以平面图的形式显示了第一实施例中半导体器件制造方法所使用的多阵列基片芯片安装表面的结构,图5以平面图的形式显示了图4所示基片封装表面的结构,图6以放大平面图的形式显示了图4所示基片芯片安装表面器件区域内的导电图形,图7以放大平面图的形式显示了图5所示基片封装表面器件区域内的导电图形,图8以平面图的形式显示了基于第一实施例变型的多阵列基片芯片安装表面的结构,图9以平面图的形式显示了图8所示基片封装表面的结构;图10以剖面图的形式显示了在根据本发明的第一实施例开始制造半导体器件时的基片结构;图11以剖面图的形式显示在根据本实施例制造半导体器件期间单元片键合时的基片结构;图12以剖面图的形式显示了在根据本实施例制造半导体器件期间丝线键合时的基片结构;图13以部分剖面图的形式显示了在本实施例的半导体器件制造期间块模制时的基片结构;图14以剖面图的形式显示了本实施例的半导体器件制造期间球安装(ball mounting)时的基片结构;图15以剖面图的形式显示了在本实施例的半导体器件制造期间球清洗(ballcleaning)时的基片结构;图16以剖面图的形式显示了在本实施例的半导体器件制造期间切割时的基片结构;图17以透视图的形式显示了根据本发明的第一实施例通过半导体器件的切割处理隔离的半导体器件结构;图18以时限图的形式显示了执行本发明第一实施例的半导体器件制造方法的组合装置的处理时限的时限图;图19以剖面图和后表面布线图系列的形式显示了根据本实施例进行切割时刀片宽度和电镀电力馈给布线之间的位置关系;图20以剖面图的形式显示了根据第一实施例变型的半导体器件的结构。
根据第一实施例的半导体器件制造方法制造的半导体器件称作球栅阵列(ball grid array)(BGA)9,如图17所示。BGA 9具有许多焊接凸块(solder bumps)3,其作为在封装基片2的后表面2b上布置成多行多列的外部连接(参考图20),并具有半导体芯片1,其安装在封装基片2的主表面2a上。
BGA 9在图4所示具有多个器件区域(半导体器件形成区域)7a的多阵列基片7上制造,并且在树脂密封之后通过切割隔离。
接着,说明切割单元(半导体器件制造装置11),其执行第一实施例的半导体器件制造方法。
图1所示的切割单元11是一个组合装置,由作为第一处理部分的预对准部分11c和作为第二处理部分的切割部分11e组成。因此,它能够在处理一个基片上基片切割位置处的图象的同时,切割另一个基片。
切割单元11包括用于供给多阵列基片7的装载部分11a,用于打印产品编号等的激光标识部分11b,作为第一处理部分的预对准部分11c,其具有适合于识别在基片7上形成的切割标记7c(参考图5)的预对准相机11d(成像装置),作为第二处理部分的切割部分11e,其用于根据通过预对准部分11c的图象识别获得的信息用切刀10切割基片7,用于清洗已切割产品的清洗部分11h,用于检查产品外观(appearance)的外观检查部分11i,用于传递被检产品的卸载部分11j,和作为输送装置用于在预对准部分11c、切割部分11e和其它处理部分之间运送多阵列基片7的xy台11k。
切割部分11e安装有对准相机11g和切割台11f。根据对准相机11g的仅仅几个点(例如两个点)的识别,台11f上的基片7能够用位于相机11g附近的切刀10加以切割。
具体地讲,预对准部分11c执行图象处理以识别多阵列基片7上全部的标记7c,借此由标记的相对位置关系预先确定切割位置。切割部分11e通过用对准相机11g识别仅仅几个参考点并利用由预对准部分11c提供的标记7c的位置信息实现基片7的对准,并且它能够用位于对准相机11g附近的切刀10快速地切割基片7。
本实施例的切割单元11使用特殊的处理工具12,如图3所示,用于运送和处理经过树脂密封的多阵列基片7。具体地讲,在基片7通过装载部分11a给入之后便由工具12支撑,直到经过多个处理之后到达卸载部分11j为止。因此,基片7在工具12的支撑下在切割单元11内进行预对准、切割和输送的处理。
工具12类似于一个盘(plate),具有许多相应于器件区域7a的吸孔(sucking holes)12a。
图3显示了基片7在切割单元11内部的输送状态。由工具12支撑的基片7用传递部分(hand section)12b通过其上面的多孔部件(porous member)加以固定,并且以这种状态被运送。
在通过切割部分11e进行切割时,移开传递部分12b和多孔部件12c,经块模制的部分8通过工具12的吸孔12a从台11f吸上来并固定在台11f上。
接着,说明在本实施例的半导体器件制造方法中使用的多阵列基片7。
图4和图5显示了多阵列基片7的结构,图4显示了基片7的芯片安装表面,图5显示了封装表面(具有焊接凸块3的表面)。本实施例的多阵列基片7是在两个侧面上都形成了布线层的多层基片。
多阵列基片7具有许多的器件区域(半导体器件形成区域)7a,形成了如图4和5所示的矩阵布局,并且每一个器件区域7a都具有形成于两个侧面上的导电图形。
在图4所示的芯片安装侧面上,每个器件区域7a都形成有导电图形,包括电力馈给导电图形(用于电力馈给的电镀布线)2j和虚设(dummy)导电图形2k,如图6的放大图所示,且这些导电图形用于提高基片的刚性和图形密度的均匀性。
此外,还形成了许多用于调整导电图形密度的导电膜除去区域(conductor film removal areas)2i。在器件区域7a的中部形成了弯孔(bent hole)2f。
在对发射电信号的导电图形进行电解电镀时,需要电力馈给导电图形2j,其是电镀布线。导电图形基于电力馈给导电图形2j的电力供应加以电解电镀。
电力馈给导电图形2j跨越每个器件区域7a的边界加以形成。在多阵列基片7的上面,每个器件区域7a的电力馈给导电图形2j相互连接作为相邻器件区域7a外部区域的布线。
由于这个原因,在每个器件区域7a的外部相互连接的电力馈给导电图形2j,在供应了用于电解电镀的电力之后,必须被切割和隔离。
在BGA 9的制造中,在块模制之后将基片7切割成分离器件时,电力馈给导电图形2j被切割,并且导电图形2j以绝缘状态保留在每个器件区域7a内,如图6所示。
在图5所示封装表面的每个器件区域7a中,形成了数种导电图形,包括用于电镀的电力馈给导电图形2j、虚设导电图形2k和凸台(bump lands)2e,如放大图7所示,且这些导电图形用于在芯片安装表面上提高基片的刚性和图形密度的均匀性。凸台2e具有通孔,并且与焊接凸块(solder bumps)3连接。
以这种方式,多阵列基片7以多个布线层的每一层为基础(在本实施例中是芯片安装侧面和封装侧面上的两个层),形成了用于电镀的电力馈给导电图形2j。
多阵列基片7在封装表面的边缘上形成了在切割时使用的对准标记7c。
这些标记7c沿着长度方向和宽度方向以恒定的间隔在相对边缘上成对地形成,从而连接相对标记的线成为了假象的切割线7b。也就是说,它们形成到(form to)基片的边缘。但是,切割线7b并不形成到多阵列基片7。
在块模制之后进行切割时,切割单元11的预对准部分11c识别沿着基片7的边缘形成的标记7c,并且通过根据识别结果连接标记7c对获得切割线7b的相对位置关系,借此确定切刀10的运行线。
切刀10沿着切割线7b运行,借此切割基片7。
图5所示的标记7c呈“H”形,其与每个边缘都垂直。只要能够通过图象识别加以识别,标记7c的形状是任意的。
标记7c优选的是布线导电图形,从而能够简单地、同时地以相同的材料与布线层的导电图形一起形成,标记7c相对于导电图形,例如电力馈给导电图形2j,的位置可以是精确的。
在本实施例的半导体器件制造中,切刀10切割经过块模制的多阵列基片7是从基片7的封装表面(后表面2b)切入的,如图16所示。因此,要求标记7c至少位于基片7的封装表面上,并且在芯片安装表面可以没有,如图4所示。否则,标记7c同时在基片7的芯片安装表面和封装表面上形成,如图8和图9的变型实施例所示。通过在基片的芯片安装表面上形成标记7c,如图8所示,图21所示的单元片键合14和丝线键合15能够使用标记7c,用于通过简单地从芯片安装侧面成像标记7c来引导识别。
多阵列基片7在其边缘上形成了多个用于定位的通孔,如图4、图5、图8和图9所示。
接着,说明本实施例的半导体器件(BGA 9)制造方法。该方法基本上使用多阵列基片7执行块树脂模制以覆盖所有的器件区域7a,其中在多阵列基片7上许多相同尺寸的器件区域7a形成了矩阵布局,并切割基片7以隔离各个BGA 9。
最初,制备许多的多阵列基片7,其每一个都具有由基础材料(base material)构成的树脂部分2h和由导电图形构成的布线部分2d,且各个部分都被阻焊剂(solder resist)的绝缘膜2g覆盖,而不是暴露导电图形,并且形成了许多的器件区域7a,如图10所示。
之后,在基片7的器件区域7a内安装半导体芯片1,如图11所示。
具体地讲,半导体芯片1,其每一个都在其主表面1b上具有许多的焊垫(pad)1a(参考图20),布置在多阵列基片7的器件区域7a上面,且芯片1的后表面1c与施加在器件区域7a上的单元片键合材料5连接。
随后,进行图12所示的丝线键合。具体地讲,每个半导体芯片1都通过丝线键合用丝线4例如金丝线使其焊垫1a与多阵列基片7相应封装基片2的连接终端2c电连接(参考图20)。
多阵列基片7利用树脂成形模21进行树脂密封,树脂成形模21由上模21a和下模21b构成,如图13所示。
上模21a(或者下模21b)形成有空腔21c,其足够地大,能够覆盖所有安装在多阵列基片7器件区域7a内的半导体芯片1。
在各个器件区域7a内都安装有半导体芯片1的多阵列基片7被设置在树脂成形模21的上模21a和下模21b之间,许多的器件区域7a被一个空腔21c覆盖,且基片7通过上模21a和下模21b夹紧。
在这种情况下,密封树脂供给到空腔21c内,从而同时模制所有的半导体芯片1和丝线4。
密封树脂是例如热固性环氧树脂。
因此,形成了经过块模制的部分8,其中半导体芯片1以整一的方式被覆盖,如图14所示。
随后,安装焊接凸块3,如图14所示。
具体地讲,多阵列基片7被放置成使封装基片2的后表面2b朝上,将球安装工具22放到基片7的上面,该球安装工具22通过真空吸引固定许多的焊接凸块3,而后从基片7的上方在每个封装基片2的后表面2b的凸台(bump lands)2e上形成焊接凸块电极。
此时,焊接凸块3基于例如红外回流(infrared reflow)处理被熔化固定。
焊接凸块3的固定可以在块模制之后切割之前进行,或者可以在切割之后进行。
随后,清洗焊接凸块3,如图15所示。
之后,多阵列基片7用切割单元11的切刀10加以切割(参考图1),如图16所示。
具体地讲,被树脂密封的经块模制部分8和基片7一起用切刀10加以切割,从而分离各个器件区域7a。
切割处理使用如图1所示的切割单元11,其中基片7按照装载、激光标记、预对准(图象识别)、切割、清洗和外观检查的顺序加以处理,如图18所示。
最初,第一多阵列基片(基片#1)7从装载部分11a运送到激光标记部分11b进行标记处理。在标记处理之后,第一多阵列基片从装载部分11a运送到预对准部分11c进行标记7c的图象识别。存储标记7c相对位置关系的结果信息。与此处理同时,第二多阵列基片(基片#2)7从装载部分11a运送到激光标记部分11b进行标记处理。
作为第一处理部分的预对准部分11c执行第一多阵列基片(基片#1)7的图象识别。具体地讲,预对准相机11d成像基片7的封装表面,从而识别沿着基片封装表面的边缘形成的所有标记7c。计算并存储标记的位置关系。选择地,确定并存储所有切割线7b,切刀在切割线7a上运行。
在识别标记7c时,估计从标记7c的坐标到某一参考点的距离,或者选择地,累积加和相邻标记7c的距离。
通过预对准部分11c估计出的标记7c的位置数据以如下的状态加以储存,即切割部分11e能够快速读出的状态。
之后,第一多阵列基片7从预对准部分11c运送到切割部分11e,其作为第二处理部分,通过它基片根据标记7c的位置信息加以切割。
具体地讲,对准相机11g准确地识别多阵列基片7的位置(例如,它识别两个标记7c从而精确地识别多阵列基片7的位置),并且基片根据标记7c的位置信息加以切割。
在通过预对准部分11c切割第一多阵列基片7的同时,第二多阵列基片7(基片#2)从激光标记部分11b运送到预对准部分11c进行预对准处理。几乎与此处理同时,第三多阵列基片7从装载部分11a运送到激光标记部分11b进行标记处理。
因此,第一多阵列基片(基片#1)7的切割处理、第二多阵列基片(基片#2)7的预对准处理和第三多阵列基片7的标记处理能够同时地发生,如图18A所示。
这些处理之后,这些多阵列基片7被运送到后续处理部分依次进行清洗和外观检查,最后被运送到卸载部分11j。
在通过切割部分11e对多阵列基片7的切割操作中,切刀10从基片7的封装表面(焊接凸块固定表面)切入。
具体地讲,对于通过预对准部分11c识别的一对标记7c,切刀10从一个标记7c运行到另一个标记7c。该操作对所有的标记7c对加以重复,且切刀10运行完所有的切割线,如图5所示。
切割操作切割电镀电力馈给布线的导电图形2j。
具体地讲,切割操作切割形成于多阵列基片7两个侧面上的电力馈给导电图形2j,如图19所示,导致电力馈给导电图形以绝缘状态保留在每一个器件区域7a内,如图6所示。
本实施例中用于切割的切刀10的宽度(B)必须足够大,以便通过切割操作切割形成于多阵列基片7两个侧面上的电力馈给导电图形2j。
通过使用切刀10的切割操作,多阵列基片7和经过块模制的部分8一起被切割成单独的BGA 9,其每一个都具有形成于封装基片2上的密封部件6,如图17所示。
根据本实施例的切割方案,基于预对准部分(第一处理部分)11c和切割部分(第二处理部分)11e的提供,切割单元11能够同时进行图象识别和切割,借此能够提高切割处理的产量,其中预对准部分具有适合于识别基片7上的标记7c的预对准相机(成像装置)11d,切割部分用于根据对准信息利用切刀10切割基片7。
结果,能够提高半导体器件(BGA 9)的生产率。
根据对所有标记7c的图象处理识别它们的位置,能够提高切割的精度。
接着,说明图20所示的半导体器件,其是第一实施例的变型。该半导体器件是芯片堆叠的BGA 23,其具有堆叠成多个台级(stage)(例如两个台级)的半导体芯片。
这种类型的半导体器件具有更多数目的信号针,导致多阵列基片7具有4个或5个布线层。更多数目的布线层很可能导致布线的宽度和位置更加不一致,使得在基片被切割之后布线间的短路发生得更多,除非提高切割位置的精度。
在这一方面,本实施例的切割方案能够提高切割精度,并且它能够防止布线之间发生短路,甚至对于制造图20所示的半导体器件也是如此,该半导体器件具有含有许多布线层的封装基片(多阵列基片)2。
实施例2:
图21以框图的形式显示了根据本发明第二实施例的半导体器件制造方法所使用的半导体器件制造系统(装置单元)的构型,而图22以框图的形式显示了作为图21系统的变型的半导体器件制造系统的构型。
与第一实施例相对,本实施例的方法所使用的系统分别包括切割单元18和图象识别单元13,而在第一实施例中切割单元11合并了预对准部分11c和切割部分11e。
具体地讲,图21所示的半导体器件制造系统包括图象识别单元12,其识别在多阵列基片7形成的标记7c(参考图5),计算机17,其是存储装置,用于存储通过图象识别单元13的图象识别获得的信息或者从识别结果计算出的信息,用于单元片键合的单元片键合器14,用于丝线键合的丝线键合器15,用于树脂模制的树脂模制单元16,和用于切割经过树脂形成的基片的切割单元18。
本实施例的半导体器件制造方法被设计用于在树脂密封之后、切割处理之前的一个分离处理中根据标记7c通过使用图象识别单元13预先识别多阵列基片7的切割线,从而切割处理唯一地执行切割,借此提高切割的产量。进一步,图象识别单元13还预先识别前导(lead)丝线键合点从而用于丝线键合处理。每个步骤中对准时间减少的结果能够提高半导体器件生产的产量。
例如,图21所示的半导体制造系统在使用图象识别单元13进行基片识别的同时,识别丝线键合引线(lead line)并根据标记7c识别切割的对准点。
图象识别单元13还能够预先识别基片的标识码(例如,条码),从而能够容易而快速地读出相应于各个基片标识码的引线数据和标记数据,其已经被存储在存储装置内,也就是计算机内。
之后,单元片键合器14将半导体芯片安装在多阵列基片7上。
随后,丝线键合器15进行丝线键合。
具体地讲,识别多阵列基片7的标识码,从计算机获取与标识码有关的用于丝线键合的引线位置信息(数据),并且将该位置信息发送给丝线键合器15。
丝线键合器15只是执行用作基片7参考点的引线的对准,并且根据来自计算机17的位置信息在基片7上进行丝线键合。
随后,树脂形成单元16执行树脂密封。
树脂密封之后,切割单元18切割基片7。具体地讲,切割单元18识别基片7的标识码。从计算机17读出相应于标识码的用于切割的标记7的位置信息(数据),并且发送到切割单元18。
切割单元18只是执行用作基片7参考点的标记7的对准,并且根据来自计算机17的切割位置信息对基片7进行切割。
因此,根据先前的使用图象识别单元13对引线位置和标记位置的识别,能够缩短丝线键合处理和切割处理的时间支出,借此能够提高这些处理的产量。
结果,能够提高半导体器件的生产率。
通过基于图象识别单元13的图象处理识别所有标记7c的位置,能够象第一实施例那样提高切割的精度。
图21的半导体器件制造系统可以设计用于利用图象识别单元13对预先在多阵列基片7上形成的单元片键合标记的位置进行识别,并且在单元片键合处理时利用单元片键合器14根据位置信息进行单元片键合。
用于存储由图象识别单元13提供的位置信息或者由识别结果计算出的位置信息的存储器不仅限于计算机17,而是可以是软盘单元或CD-ROM(光盘只读存储器)单元。在这种实例中,记录有位置信息的软盘或CD-ROM放到期望的半导体器件制造单元例如丝线键合器15或者切割单元18中,通过它读出处理所需的数据。
单元片键合位置标记必须存在于多阵列基片7的芯片安装侧面上。一个方案是在基片7的两个侧面上都形成位置标记7c。图象识别单元13识别一个侧面上的全部标记7c,之后,基片7翻转朝下,识别另一侧面上的所有标记7c,借此识别两个侧面上的所有标记7c。另一个方案是在多阵列基片7的两个侧面上都安装预对准相机11d(参考图1),并且用这些相机11d识别基片两个侧面上的标记7c。
本实施例的半导体器件制造方法可以设计用于通过另一个位于半导体器件制造系统外部的设备预先识别多阵列基片7的单元片键合位置标记7c。在导入多阵列基片7和标记7c位置信息(数据)的预备操作之后,进行单元片键合处理、丝线键合处理、树脂形成处理和切割处理,制造半导体器件。
接着,说明根据本实施例第二个变型的半导体器件制造系统,如图22所示。在图21所示的半导体器件制造系统中,当图象识别单元13的工作显著快于切割单元18时(例如快三倍),将三个切割单元18与一个图象识别单元13相连,如图22所示,从而图象识别处理和切割处理转为几乎同时(much in turn around time)。结果,切割处理提高了产量,而图象识别单元13能够完全发挥其能力。
虽然本发明是联系特殊的实施例加以说明的,但是本发明并不仅限于这些实施例,而是显然存在各种改变而不背离本发明的本质。
例如,树脂模制可以这样进行,即用树脂成形模21的各个空腔21c覆盖器件区域7a而后向各个空腔内供给树脂,而不是执行第一实施例所采用的块模制。
半导体芯片1与多阵列基片7之间的电连接可以基于倒装连接(flip-chip connection),而不是第一实施例所采用的丝线连接。
半导体器件,第一实施例中的BGA 9或芯片堆叠BGA 23,可以是其它的类型,例如LGAs(台栅阵列)(land grid arrays),只要它们在多阵列基片7上制造并且在树脂密封之后通过切割加以分离即可。
在本专利说明书中公开的本发明中,主要的有效性简要说明如下。
通过提供第一处理部分和第二处理部分,其中第一处理部分具有适合于识别多阵列基片上的识别标记的成像装置,第二处理部分根据得自于第一处理部分对准处理的位置信息用切刀切割基片,使得同时执行对准和切割成为可能,借此能够提高半导体器件制造中切割处理的产量。

Claims (17)

1.一种通过使用多阵列基片制造半导体器件的方法,该多阵列基片具有多个半导体器件形成区域,所述方法包括如下步骤:
(a)制备多个多阵列基片;
(b)将多个半导体芯片安装在多阵列基片上;
(c)对安装在多阵列基片上的半导体芯片进行树脂密封;和
(d)在步骤(c)之后对多阵列基片中的第一多阵列基片执行图象识别,之后将第一多阵列基片切割成单独的半导体器件,同时,对第二多阵列基片进行图象识别。
2.根据权利要求1的半导体器件制造方法,包括如下步骤:
在步骤(c)之后,将多阵列基片中的第一多阵列基片放置在第一处理部分中执行图象识别,之后将第一多阵列基片移动放置在第二处理部分中,并将第二多阵列基片放置在所述第一处理部分中;和
在所述第二处理部分中将第一多阵列基片切割成单独的半导体器件,同时,在所述第一处理部分中对第二多阵列基片执行图象识别。
3.根据权利要求1的半导体器件制造方法,其中所述图象识别步骤识别多个沿着每个多阵列基片的边缘形成的标记,根据所识别的成对的相对标记确定切刀的运行线,并且沿着所确定的运行线运行所述切刀,借此切割基片。
4.根据权利要求1的半导体器件制造方法,其中所述多阵列基片包括具有多个布线层的多层基片。
5.根据权利要求1的半导体器件制造方法,其中所述多阵列基片形成有电镀电力馈给线,所述电镀电力馈给线通过切片处理而加以切割。
6.根据权利要求1的半导体器件制造方法,其中在所述图象识别中加以识别的所述标记由导电图形构成。
7.根据权利要求1的半导体器件制造方法,其中所述多阵列基片包括具有多个布线层的多阵列基片,每一个布线层都形成有电镀电力馈给线。
8.一种通过使用多阵列基片制造半导体器件的方法,该多阵列基片具有多个半导体器件形成区域,所述方法包括如下步骤:
(a)制备多个多阵列基片,每个基片都形成有半导体器件形成区域;
(b)将多个半导体芯片安装在多阵列基片上;
(c)在半导体芯片和多阵列基片之间进行电连接;
(d)利用树脂成形模的空腔来密封多阵列基片的整个半导体器件形成区域并将密封树脂馈给到该空腔中,借此树脂密封半导体芯片;
(e)在步骤(d)之后对多阵列基片中的第一多阵列基片执行图象识别,之后将第一多阵列基片经过块模制的部分与第一多阵列基片一起切割成单独的半导体器件,同时,对第二多阵列基片进行图象识别。
9.根据权利要求8的半导体器件制造方法,包括如下步骤:
在步骤(e)之后,将多阵列基片中的第一多阵列基片放置在第一处理部分中执行图象识别,之后将第一多阵列基片移动放置在第二处理部分中,并将第二多阵列基片放置在所述第一处理部分中;和
在所述第二处理部分中将第一多阵列基片经过块模制的部分与第一多阵列基片一起切割成单独的半导体器件,同时,在所述第一处理部分中对第二多阵列基片执行图象识别。
10.根据权利要求8的半导体器件制造方法,其中所述半导体芯片安装步骤(b)将半导体芯片堆叠成多个台级。
11.一种通过使用多阵列基片制造半导体器件的方法,该多阵列基片具有多个半导体器件形成区域,所述方法包括如下步骤:
(a)制备多个多阵列基片;
(b)利用图象处理单元识别在多阵列基片上形成的引线或标记;
(c)将多个半导体芯片安装在多阵列基片上;
(d)对安装在多阵列基片上的半导体芯片进行树脂密封;和
(e)在步骤(d)之后利用切割单元根据通过步骤(b)识别确定的切割位置将基片切割成单独的半导体器件。
12.根据权利要求11的半导体器件制造方法,包括如下步骤,即根据通过步骤(b)的识别获得的某些数据对多阵列基片进行除切割之外的其它的期望的制造处理。
13.根据权利要求11的半导体器件制造方法,其中所述多阵列基片每一个都具有一个标识码,所述识别步骤(b)识别引线或标记以及标识码,所述切割以及除切割之外的处理通过使用相应于所识别的标识码的引线或标记数据加以执行。
14.根据权利要求13的半导体器件制造方法,其中通过步骤(b)的识别获得的引线或标记以及标识码的某些数据存储在存储器中,且切割以及除切割之外的其它处理利用从所述存储器中读出的相应于所识别标识码的引线数据或标记数据加以执行。
15.一种通过使用多阵列基片制造半导体器件的方法,该多阵列基片具有多个半导体器件形成区域,所述方法包括如下步骤:
(a)准备多阵列基片和相应于该基片的切割数据;
(b)将多个半导体芯片安装在多阵列基片上;
(c)对半导体芯片进行树脂密封;和
(d)在步骤(c)之后利用切割单元根据在步骤(a)中准备的数据将多阵列基片切割成单独的半导体器件。
16.一种半导体器件制造装置,包括:
第一处理部分,其具有适合于识别在多阵列基片上形成的标记的成像装置,在其上形成多个半导体器件形成区域;
第二处理部分,其根据由所述第一处理部分的图象识别获得的信息用切刀切割该多阵列基片;和
输送设备,其在所述第一处理部分和所述第二处理部分之间载送多阵列基片,
所述装置能够同时执行对放置在所述第二处理部分中的第一多阵列基片的切割和对放置在所述第一处理部分中的第二多阵列基片的图象识别。
17.根据权利要求16的半导体器件制造装置,进一步包括用于固定多阵列基片的处理工具,多阵列基片通过由所述处理工具固定而在所述第一处理部分、所述输送设备和所述第二处理部分中经历处理。
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