CN1649148A - 芯片及使用该芯片的多芯片半导体器件及其制造方法 - Google Patents

芯片及使用该芯片的多芯片半导体器件及其制造方法 Download PDF

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CN1649148A
CN1649148A CNA2005100061383A CN200510006138A CN1649148A CN 1649148 A CN1649148 A CN 1649148A CN A2005100061383 A CNA2005100061383 A CN A2005100061383A CN 200510006138 A CN200510006138 A CN 200510006138A CN 1649148 A CN1649148 A CN 1649148A
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chip
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semiconductor device
embolism
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CN100385665C (zh
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松井聪
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Renesas Electronics Corp
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NEC Corp
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Abstract

提出了用于多芯片半导体器件的芯片及其制造方法，该芯片具有仅仅通过从芯片的前表面的处理(光刻，刻蚀)在芯片的前表面和/或后表面上形成的用于对准的标记，而不增加任何专用的工艺步骤到用于对准的标记的形成工艺。在用于多芯片半导体器件的单个芯片中具有两个或更多导电穿通栓塞的多芯片半导体器件的芯片中，采用一个或多个导电穿通栓塞用于对准的标记，并且该芯片被配置为允许识别用于多芯片半导体器件的芯片的前表面和/或后表面上的用于对准的标记。然后，在导电穿通栓塞的前表面和/或后表面上设置绝缘膜。

Description

芯片及使用该芯片的多芯片半导体器件及其制造方法
本申请基于日本专利申请号2004-020444，因此将其全部公开内容引入作为参考。
技术领域
本发明涉及用于多芯片半导体器件的芯片和采用该芯片的多芯片半导体器件及其制造方法，多芯片半导体器件具有用于对准的标记。
背景技术
近年来，为了形成在计算机和通信设备中的关键性部分经常采用具有超大规模集成电路(VLSI)的半导体芯片(以下简单地称为“芯片”)。在这种芯片的用途中常常采用形成多个芯片的层叠体的结构。这里，当多个芯片用于形成层叠体时，特别的关键点可能是怎样调整各个芯片的位置，或也就是用于对准的方法。
用于在多芯片层叠的半导体器件中建立对准的下列方法是公知的。
日本未决专利号H10-303,364(1998)公开了一种用于建立芯片的对准的方法，其中在用于形成多层层叠体的各个芯片中设置无内置材料的通孔或其中内置有透明材料的通孔，用激光束从下面的方向照射通孔，通过设置在上侧的光探测器接收照射的激光束，然后移动各个芯片，以便获得最大强度的透射光，以实现上芯片和下芯片的对准。
日本未决专利号2000-228,487也公开了一种用于建立芯片的对准的方法，其中当制造具有片上芯片结构的多芯片模块时，通过使用印刷机或激光标记器在芯片的背部上绘制标记，该芯片是面向下方向中键合的倒装芯片，然后采用该标记作为用于实现对准的标记。
日本未决专利号2000-228,488也公开了一种用于建立芯片的对准的方法，其中当制造具有片上芯片结构的多芯片模块时，在面向下的方向中键合的倒装芯片的芯片背部上绘制电极标记，该标记对应于芯片表面上的电极位置，然后采用该标记作为用于实现对准的标记。
日本未决专利号2001-217,387也公开了一种用于建立芯片的对准的方法，其中在将被连接以形成片上芯片结构的各两个芯片的表面的相应位置设置用于对准的标记，然后采用该标记作为用于实现对准的标记。
日本未决专利号2002-76,247也公开了一种用于建立芯片的对准的方法，其中中空虚通孔具有从顶部布置的芯片至底部布置的芯片连续不断地减小的直径，以及各个层的虚通孔的中心被对准，以实现上芯片和下芯片的对准。
发明内容
现在已经发现了如上所述的这些相关技术文献在下列点中还具有改进的空间。
由于日本未决专利号H10-303,364中描述的方法中，在进行对准的同时测量透射光强度的操作是必需的，因此该方法需要如激光的光源，用于接收来自光源的照射光的光探测器，以及用于贴装光源和光探测器的贴装器。当用于对准的通孔的直径较小时，光探测器处接收的可用光强度也较小，因此不能对准。另一方面，当通孔的直径较大时，尽管获得了足够的光强度，但是对准的精度更差。因此，需要用于透射照射光的通孔尺寸的最优化以及光源和光探测器的最优化。而且，该方法除设置穿通电极之外，还需要用于设置能透射光的用于对准的通孔的专用处理步骤，且因此对于其中基本上没有必要具有通孔的多芯片模块的顶层和底层的芯片也应该在其中具有通孔。
如日本未决专利号2000-228,487所述，在芯片的背部上用线印刷机或激光标记器绘制标记的方法在低于1μm的精确级别不能实现精确的定位控制。因此，该方法不能提供足够级别的对准尺寸精度，且因此这种方法中用于精细间距键合的对准是不可能的。类似地，日本未决专利号2000-228488中描述了在对应于芯片表面上的电极位置的芯片的背部上绘制标记的方法不能实现低于1μm的精确级别的精确位置控制。
此外，日本未决专利号2000-228,487和日本未决专利号2000-228,488描述的方法中，采用通过所谓的面向下方法结合上芯片和下芯片的操作，该方法是在同时图像识别下芯片上用于对准的标记和上芯片上的背部标记的同时结合上芯片和下芯片的方法。因此，当层叠具有相同尺寸的芯片时下芯片隐藏在上芯片后面，以致不能识别用于对准的标记，且因此在这种条件下该方法的应用是困难的。
日本未决专利号2001-217,387中描述的方法是在普通倒装芯片键合机中采用的方法。该工艺需要在待结合以形成片上芯片结构的两个芯片的表面上的相应等效位置处分开地形成用于对准的标记。在比1μm更精细的级别中为了精确地控制芯片的后表面上的标记与前表面上用于对准的标记的对应，在分开的处理步骤中分开地提供用于对准的标记的方法是困难的。因此，在芯片被层叠以形成三层或更多层的情况下，该工艺绝对不可能实现1μm或更精细的层叠布置的精度的改进。
如日本未决专利号2002-76,247所述，采用具有连续减小直径的中空虚通孔的方法，对于以1μm或更精细的级别对准具有不同直径的虚通孔的中心，即使虚通孔具有更高的精度，也不能期望提供提高的精度。
总之，现有技术中用于实现对准的方法不可能提供1μm或更精细级别的对准精度，且因此对准具有键合的更精细间距的芯片是不可能的。而且，在某些情况下，为了形成用于对准的标记必须添加额外的工艺步骤。
根据本发明的一个方面，提供一种用于构成具有多个层叠的半导体芯片的多芯片半导体器件的芯片，其包括：衬底；以及由贯穿衬底的导电材料构成的多个导电穿通栓塞，其中多个导电穿通栓塞包括第一导电穿通栓塞和与第一导电穿通栓塞分开地设置的第二导电穿通栓塞，其中第一导电穿通栓塞和第二导电穿通栓塞被配置为在平面图中有可见的区别，并且其中第二导电穿通栓塞是用于对准的标记。
根据本发明的另一方面，提供一种用于多芯片半导体器件的芯片，在用于多芯片半导体器件的一个芯片中包括两个或更多的导电穿通栓塞，其中采用导电穿通栓塞中的一个或多个作为用于对准的标记，并且其中该芯片具有提供可显著地识别用于多芯片半导体器件的芯片的前表面和/或后表面上用于对准的标记的结构。
在本发明的这些方面中，术语“第二导电穿通栓塞是与第一导电穿通栓塞分开地提供”指包括内置在不同的通孔内的这些导电栓塞的结构，并且该术语不包括其中例如导电穿通栓塞的周围被其它导电穿通栓塞围绕和这些导电穿通栓塞设置在一个通孔内的结构。
由于在本发明的芯片中，第一导电穿通栓塞和第二导电穿通栓塞被配置为在平面图中有可见的区别，因此当构成多芯片半导体器件时，可以明确地识别对准标记的位置，以提供精确对准。
而且，用于本发明的多芯片半导体器件的芯片包括用于对准的标记，该标记由导电穿通栓塞构成。因此，可以仅仅用从其表面进行的处理(如光刻，刻蚀等)在芯片的前表面和/或后表面上形成用于对准的标记。
更具体地说，根据本发明的这些方面的芯片还可以包括一个结构，其中在衬底内设置的第一孔内设置第一导电穿通栓塞，并且其中在衬底内设置的第二孔内设置第二导电穿通栓塞，通过刻蚀掉衬底的预定区形成第一和第二孔。本发明的这些方面还包括一个附加的结构，其中通过相同工艺形成第一导电穿通栓塞和第二导电穿通栓塞。
由于通过使用导电穿通栓塞中的一个提供用于在本发明的芯片上对准的标记，因此可以以例如比1μm更精细的精度级别控制其位置和尺寸。因此，如果通过使用以比1μm更精细的精度级别形成的用于对准的标记来对准芯片，那么该芯片可以用比1μm更精细的对准精度级别对准。
这里，如果芯片具有上述结构，那么根据本发明的芯片是令人满意的，并且本发明并不意图限于包括如晶体管等有源元件器件。例如，本发明的芯片也可以包括硅间隔片等。这里，在本说明书中，间隔片是用于在多芯片半导体器件中的每个层叠芯片之间提供电耦合的平板部件，且包括如硅衬底等的衬底和贯穿衬底的穿通电极。穿通电极被电耦合到间隔片的上部上设置的半导体器件的导电部件。而且，该间隔片可以包括具有除如晶体管的有源元件之外的元件的结构，且具体地可以包括例如互连、电容器、电感器、天线等的无源元件，或另外可以包括没有无源元件的结构。
本发明的这些方面还可以包括一个附加的结构，其中第一导电穿通栓塞将衬底的表面上设置的第一导电部件耦合到衬底的另一表面上设置的第二导电部件。第一导电部件和第二导电部件可以设置在芯片上，或可以设置在耦合到该芯片的其它芯片上。当这些部件设置在其它芯片上时，这些部件例如可以布置在面对上述一个表面的表面上，或面对上述其它表面的表面上。
而且，在本发明的这些方面中，第二导电穿通栓塞可以具有不耦合到任意其它导电部件的结构。
本发明的这些方面还可以包括一个附加的结构，其中第二导电穿通栓塞具有不同于第一导电穿通栓塞的二维几何形状。
本发明的这些方面还可以包括一个附加的结构，其中基于芯片上第二导电性导电栓塞的两维布置，第二导电性导电栓塞可以不同于第一导电穿通栓塞。例如，前述的第二导电穿通栓塞可以配置为布置在比前述的第一导电穿通栓塞更靠近衬底周边的位置。而且，多个前述的第一导电穿通栓塞可以布置为形成其栅格型二维布置，以及可以在邻近于布置了前述第一导电穿通栓塞的区域的一侧中以预定的间隔布置多个前述的第二导电穿通栓塞。
根据本发明的另一方面，提供一种用于多芯片半导体器件的芯片键合设备，其中，当通过键合设备层叠用于多芯片半导体器件的芯片时，通过利用用于对准的标记计算多芯片半导体器件的芯片位置，用于多芯片半导体器件的芯片在用于多芯片半导体器件的一个芯片中包括两个或多个导电穿通栓塞并且还包括用于对准的标记采用的一个或多个导电穿通栓塞。
根据用于本发明的多芯片半导体器件的芯片键合设备，当通过采用该键合设备层叠用于多芯片半导体器件的芯片和其它芯片时，可以提高对准精度。例如，可以以比1μm更精细的对准精度级别进行键合。
根据本发明的再一方面，提供一种用于对准用于多芯片半导体器件的芯片的方法，其中，当对准并且然后层叠用于多芯片半导体器件的芯片时，通过利用用于对准的标记对准用于多芯片半导体器件的芯片，用于多芯片半导体器件的芯片在用于多芯片半导体器件的一个芯片中具有两个或更多导电穿通栓塞且包括用于对准的标记采用的一个或多个导电穿通栓塞。
根据用于对准用于本发明的多芯片半导体器件的芯片的方法，由于当对准并且然后层叠用于多芯片半导体器件的芯片时采用由导电性穿通栓塞构成的用于对准的标记，因此可以提高芯片的对准精度。例如，可以用比1μm更精细的对准精度级别对准该芯片。
根据本发明的再一方面，提供一种用于制造用于多芯片半导体器件的芯片的方法，其包括：刻蚀用于多芯片半导体器件的芯片，以形成两个或更多过孔；填充在该刻蚀芯片中形成的两个或更多通孔，以形成具有导电材料的两个或更多过孔；以及在用导电材料填充两个或更多过孔的过程中，通过重处理具有导电材料填充于其中的用于多芯片半导体器件的芯片后表面露出导电材料；其中采用具有在其中填充导电材料的一个或多个导电穿通栓塞作为用于对准的标记，并且其中用于对准的标记和其它导电穿通栓塞之一被配置为在用于多芯片半导体器件的芯片前表面和/或后表面上有可见的区别。
根据用于制造用于本发明的多芯片半导体器件的芯片的方法，用于对准的标记和导电穿通栓塞是在一个工艺中制造的。而且，可以获得具有包括用于对准的标记和其它导电穿通栓塞的结构的芯片，用于对准的标记和其它导电穿通栓塞在芯片的前表面和/或后表面上有可见的区别。因此，通过简单的工艺可以稳定地制造提供改进的对准精度的芯片。例如，如果使用这种用于对准的标记对准芯片，那么可以以比1μm更精细的对准精度级别对准芯片。
在本发明中，为了识别在用于多芯片半导体器件的前述芯片的前表面和/或后表面上用于对准的前述标记，可以增加其布置和几何形状的某些改变。例如，用于对准的标记形状可以是圆形、L形和点状或十字形来提供其标识。而且，通过改变用于对准的标记尺寸和其它导电栓塞的尺寸也可以提供标识。
而且，通过用于对准的标记与导电栓塞的相对位置也可以提供标识。例如，通过采用导电栓塞的具体列作为用于对准的标记或通过添加用于对准的标记短列到导电栓塞的列可以提供标识。另外，一些导电穿通栓塞可以从规则的布置偏离，以形成用于对准的标记的可识别图形。
而且，在本发明中，可以在用于对准的导电标记所采用的穿通栓塞的前表面和后表面上设置用于对准的前述标记，如具有相同几何形状。更具体地，可以最好在芯片的前表面和后表面上都设置具有相同形状的标记，并且该形状可以选自任意形状如圆形、L形、十字形、点状等。具有这种结构，在芯片的前表面和后表面上都可以识别具有相同形状的用于对准的标记，因此防止芯片的错误贴装。在本发明中，可以利用芯片的前表面作为元件形成表面。
在本发明中，用于对准的标记可以具有不对称的几何形状或其不对称的布置。其具体结构可以是例如在芯片的表面上用于对准的前述标记的几何形状或其布置与芯片表面的中心不对称。具有这种结构，芯片的前表面可以不同于其后表面。当间隔片具有穿通电极和还仅仅具有贴装在其上的无源元件，如形成互连，电感器，电容、电阻等时，由于一般对称地布置与导电相关的导电穿通栓塞，因此前表面和后表面难以从其外观区分。在此情况下，如果设置用于通过用于对准的标记来提供芯片的前表面与其后表面的区分的结构，那么可以防止芯片的错误贴装，因此导致连接可靠性的改进。
在本发明中，用于对准的标记所采用的导电穿通栓塞可以具有截面，其最小宽度等于或小于其它导电穿通栓塞的最小宽度，并且其最小宽度可以等于或小于1μm。一般，根据其宽度改变用于填充穿通栓塞的条件，并且上述条件允许在相同条件下通过相同工艺与其它导电穿通栓塞同时形成用于对准的标记。因此，可以减小该制造工艺的负担。此外，当用于对准的标记直径小于其它导电穿通栓塞的直径时，可以加宽实际操作中利用的芯片面积。
在本发明中，可以用绝缘材料覆盖用于对准的标记所采用的导电穿通栓塞的前表面和/或后表面。
此外，在本发明中，该方法还可以包括在用导电材料填充两个或更多过孔之后，在其中填充有导电材料的导电穿通栓塞的一个或多个前表面和/或后表面上形成绝缘膜。
栓塞涂有绝缘材料，以防止金属电镀互连和凸点粘结到用于对准的标记上。因此，从透视观点在俯视用于对准的标记中其形成精度可以保持在光刻的分辩率级别，且因此可以更肯定地抑制对准精度的退化。
绝缘材料典型地可以包括透明材料，诸如例如SiO2，SiON，SiN等。此外，可用的材料不必局限于透明材料，也可以采用着色的材料。具有这种结构，用于对准的标记可以被电绝缘，且因此可以防止如短路的危险。此外，如果采用着色的材料，那么当其有色时，导电栓塞可以更容易从其它导栓塞识别。
在本发明中，用于对准的前述标记可以是用于封装的对准标记，或可以是用于光刻的定位标记。在用于光刻的定位标记的情况下，其最小宽度可以等于或小于其它导电穿通栓塞的最小宽度，并且其最小宽度可以等于或小于1μm。
而且，用于对准的标记所采用的至少部分导电穿通栓塞的电位可以被固定。
通过固定用作用于对准的标记的导电穿通栓塞的至少部分电位可以减小在多芯片半导体器件的操作过程中由芯片发出的噪音，且因此可以带来具有更高可靠性的多芯片半导体器件。
而且，与通过如激光处理或钻孔等提供具有至少几十μm直径的通孔的其它工艺形成通孔的情况相比较，根据本发明通过利用在用于制造芯片的方法中刻蚀通孔的前述工艺中的干法刻蚀可以显著地减小通孔的直径。因此，通过简单的和容易的工艺可以稳定地制造进一步提高对准精度的芯片。
在本发明中，用导电材料填充前述通孔的方法可以是从以下方法构成的组中选择的一种或多种方法：电镀；溅射；CVD；导电树脂涂敷(application)；以及焊料/低熔点金属的熔融。
附图说明
从下面结合附图的详细说明将使本发明的上述及其它目的、优点和特点更明显，其中：
图1A至1D是衬底的剖面图，图示了根据本发明的第一实施例用于多芯片半导体器件的芯片的制造工艺；
图2A和图2B是用于本发明的第一实施例的多芯片半导体器件的芯片的透视图，图示了芯片的结构；
图3是用于本发明的第二实施例的多芯片半导体器件的芯片的平面图，图示了芯片的结构；
图4A至4G是用于本发明的第三实施例的多芯片半导体器件的芯片的平面图，图示了芯片的结构；
图5是流程图，图示了通过使用本发明的第四实施例用于芯片的键合设备来层叠用于多芯片半导体器件的芯片的方法；
图6A，6B和6C是用来层叠用于本发明的第四实施例的多芯片半导体器件的芯片的键合设备的示意性剖面图，示出了键合设备的结构；
图7通过用图6A至6C所示的用于多芯片半导体器件的芯片的键合设备进行装配工艺形成的半导体器件的示意性剖面图；
图8通过用图6A至6C所示的用于多芯片半导体器件的芯片的键合设备层叠芯片形成的晶片上管芯的示意性平面图；
图9通过用图6A至6C所示的用于多芯片半导体器件的芯片的键合设备层叠芯片以形成四层体而形成的多芯片半导体器件的示意性剖面图；
图10通过用图6A至6C所示的用于多芯片半导体器件的芯片的键合设备层叠具有穿通电极间隔片形成的多芯片半导体器件的示意性剖面图；
图11是通过用图6A至6C所示的用于多芯片半导体器件的芯片的键合设备层叠光学器件形成的多芯片半导体器件的示意性剖面图；以及
图12通过用图6A至6C所示的用于多芯片半导体器件的芯片的键合设备层叠包括也具有穿通电极的底芯片而形成的多芯片半导体器件的示意性剖面图。
具体实施方式
现在将参考说明性实施例描述本发明。所属领域的技术人员将认识到使用本发明的讲述可以完成许多选择性的实施例，以及本发明不局限于用于解释性目的而说明的实施例。
如下参考附图进一步详细描述根据本发明的实施例。在所有图中，相同的数字指定图中共同出现的元件，且不再给出其详细描述。在下列实施例中，将描述芯片包括硅衬底的情况。
第一实施例
图2A和图2B是透视图，图示了本实施例的用于多芯片半导体器件的芯片结构。用于图2A和图2B所示的多芯片半导体器件的芯片7是构成多芯片半导体器件的芯片，多芯片半导体器件包括多个层叠的半导体芯片，并且包括衬底1(硅衬底)，和由穿通衬底1的导电材料构成的多个导电穿通栓塞(导电穿通栓塞8和用于对准的标记9至12)。
这些多个导电穿通栓塞包括第一导电穿通栓塞(导电穿通栓塞8)和与导电穿通栓塞8分开地设置的第二导电穿通栓塞(用于对准的标记9至12)。用于对准的标记9至12和导电穿通栓塞8被配置为在平面图中有可见的区别。
导电穿通栓塞8用作将设置在衬底1的一侧中的第一导电部件(未示出)电耦合至设置在衬底1的另一侧中的第二导电部件(未示出)的穿通电极。此外，第二导电穿通栓塞是用于对准的标记。用于对准的标记9至12可以配置为不耦合到衬底1的任何一个表面设置的其它导电部件。
图2A是透视图，图示了采用用于对准的标记9和具有十字形的截面的用于对准的标记10的情况，其中用于对准的标记9是在有色的背景上产生白色十字形间隔的截面的组合。在该说明书中，术语“在有色的背景上产生白色十字形间隔的截面的组合”意味着当四个导电穿通栓塞具有颜色时，构成用于对准的标记的四个导电穿通栓塞产生十字形的截面，不同于周围部分。例如，当芯片的背景颜色是白色并且构成用于对准的标记的导电穿通栓塞的颜色是黑色时，用于对准的标记可以被识别为黑色背景上的白色十字形间隔。
图2B是透视图，图示了用于对准的标记11具有L形和点状的剖面图，以及用于对准的标记12具有圆形截面。
如图2A和图2B所示，如上所述用于对准的标记9至12在芯片的前表面上的形状与其后表面上的形状相同，且因此用于对准的标记9至12可以与其它导电穿通栓塞8完全相同。
尽管图2B图示一些采用具有圆形截面的用于对准的中空圆柱形标记12的情况，但是也可以采用用于对准的实心圆柱形标记12。
图1A至图1D是剖面图，图示了用于多芯片半导体器件的芯片的制造工艺。尽管这里利用剖面图描述提供用作用于在两端对准的标记的穿通栓塞的情况，但是参考图1A至图1D描述的方法也可应用于如上所述的图2A和图2B所示的用于多芯片半导体器件的芯片。
关键点是用于对准的标记也可以通过用于形成在芯片中设置的其它导电穿通栓塞的工艺同时形成，其它导电穿通栓塞诸如具有在芯片之间提供电耦合的便利的栓塞。
首先，如图1A所示，通过用于衬底1表面的光刻工艺将导电穿通栓塞的通孔图形曝光。然后，通过干法刻蚀有选择地除去衬底1上预定位置，以形成用于形成通孔的通孔2。设置多个通孔2。在某些通孔2内内置用作穿通电极的导电穿通栓塞8，在其它通孔2内内置用于对准的标记9至12的导电穿通栓塞。
然后，如图1B所示，用绝缘膜(图中未示出)涂敷图1A中制造的深通孔2，以及通过溅射形成籽晶层(图中未示出)，然后通过电解电镀用导电材料3填充通孔2。在此情况下，用于填充的金属可以适当地选自Cu，Al，Au，W，Ti，Sn，焊料等。另外，导电树脂可以用于通孔2内的填充。
接着，如图1C所示，在研磨衬底1的后表面之后，进行干法刻蚀、干抛光或湿法刻蚀，以在其后表面上露出通孔内填充的金属，因此完成导电穿通栓塞6。导电穿通栓塞6和6′对应于图2A和图2B中的导电穿通栓塞8。
尽管凸点金属电镀可以粘附到用作用于对准的标记的导电穿通栓塞6′，但是可以另外涂敷绝缘膜，且当用绝缘膜涂敷导电穿通栓塞6′时，可以进一步提高栓塞的形成精度，因此可以进一步保持光刻中的较高精度。
然后，如图1D所示，用覆盖绝缘膜4(绝缘膜：SiO2，SiON，SiN等)覆盖用于形成用于对准的标记的通孔的上表面和/或后表面，以提供用于对准的标记的完成形式。在该结构中，用覆盖绝缘膜4覆盖用于对准的标记5不是基本问题，且当标记覆有绝缘膜4时，即使开始形成凸点电镀的形成工艺，也可以避免了电镀金属与覆有覆盖绝缘膜4的区域粘附，且因此从透视观点看在其俯视中保持了在光刻工艺中的分辩率级别的其形成精度的有利效果。
如上所述可以获得用于多芯片半导体器件的芯片。
由于普通导电穿通栓塞6应该具有凸点电镀，因此导电穿通栓塞6之上或之下的覆盖绝缘膜4的区域设有开口。
接下来，将描述通过采用根据本实施例的用于多芯片半导体器件的芯片可获得的有利效果。
在用于图2A或图2B所示的多芯片半导体器件的芯片7的表面内的预定位置处设置对准标记，该对准标记可以容易地与其它穿通栓塞相区别。
对准标记由相同材料和与用于在芯片中形成其它导电穿通栓塞相同的工艺形成。因此，不再需要用于形成对准标记的不希望工艺，由此提供简单而且容易的制造工艺。例如，进行用于形成用于对准的标记的附加工艺，例如用于进行用于芯片的后表面的光刻工艺或用于用激光束形成用于形成对准标记的通孔的工艺。
此外，由于通过刻蚀形成用来形成在其中内置的用于对准的标记9至12的孔，因此与通过激光束形成用于对准标记的通孔的情况相比，可以减小用于对准的标记的直径。具有利用用于定位标记的这种对准标记的结构，在层叠多个芯片的情况下可以提高层叠方向中的其对准精度。因此，可以带来在用于多芯片半导体器件的制造工艺中提供改进的稳定性和可靠性的结构。
例如，当形成以倒装芯片或片上芯片的形式的键合时，可以以比1μm更精细的精度级别进行芯片的对准。此外，由于可以以比1μm更精细的精度进行芯片的对准，因此该工艺也可以应用于具有更精细键合间距的芯片对准。
由于对准标记贯穿图2A或图2B所示的用于多芯片半导体器件的芯片7中的芯片，因此可以在芯片两侧中的相同位置处布置对准标记。
在芯片仅仅在芯片的前表面具有对准标记的情况下，与其前表面上的对准精度相比，用作多芯片半导体器件的介质层的芯片后表面上的对准精度可能被损坏。相反，具有本实施例的结构，可以分别明确地提高布置在介质层芯片的一侧上的芯片和布置在介质层芯片的另一侧上的芯片对准精度。此外，没有必要制备包括用于对准的标记的芯片，该标记具有不同几何形状和尺寸，且因此可以在一个直接的工艺中制造用于对准的标记。
此外，用于提供芯片连接的方法没有限制，且因此可以采用用于提供芯片连接的任意方法，例如面向下、由上下方向成像、红外线透射图像等。
此外，与光透射型对准的情况相比，可以采用较小的对准标记，以及通过使用干法刻蚀工艺可以产生进一步减小直径的通孔，且因此芯片的实际利用面积可以相对更宽阔。
尽管在本实施例中图示了利用芯片的两侧上的对准标记的相同二维几何形状的情况，但是用作对准标记的导电穿通栓塞的二维几何形状在芯片的两侧不必具有相同的几何形状和尺寸，以及也可以设置从芯片的一侧至另一侧具有增加截面的截锥形的对准标记。在芯片的两侧上设置相同二维几何形状的结构，可以更明确地抑制芯片层叠时发生的未对准，以提供对准精度的进一步改进。
而且，具有设置不对称地布置的标记作为用于对准的标记的结构，可以更容易地进行诸如芯片的前表面与后表面的区分或旋转角度的确定的操作。
第二实施例
图3是平面图，图示了用于本实施例的多芯片半导体器件的芯片的结构。图3所示的用于多芯片半导体器件的芯片(芯片13)包括导电穿通栓塞14至16，用于对准的标记17和用于对准的标记18。芯片13可以通过使用例如制造第一实施例中所述的用于多芯片半导体器件的芯片的方法来制造。
在图3中，芯片13的二维几何形状是矩形(在该实施例中是正方形)。
图3中的下部显示的用于对准的标记17和其上部显示的用于对准的标记18图示为不对称地布置在芯片13的表面内(在图中的上部和下部)。更具体地说，设置一种结构，其中用于对准的下标记17和用于对准的上标记18由基本单元构成，基本单元由图2B所示的L形和点状以及圆形对准标记12构成且并排地布置在芯片的周边附近，基本单元的重复数目在相对边缘不同，且因此芯片表面的中心上对准标记的布置是不对称的。由于通过利用基本单元的重复数目可以识别芯片边缘，因此芯片的布置方向可以容易地识别。
在本实施例中，通过在矩形芯片的多个边缘的附近不对称地布置用于对准的标记可以容易地进行芯片13的前和后表面的识别和表面方向中的旋转角度的确定。没有必要指出用于对准的标记17和用于对准的标记18具有与其它导电穿通栓塞14至16不同的二维几何形状，且因此可以与这些栓塞相区别。
而且，在本实施例中，在芯片13的表面上的预定位置处用较高精度稳定地形成可以容易地从其它穿通栓塞识别出来的对准标记。而且，不再需要用于形成对准标记的不需要工艺。因此，本实施例提供能够形成对准标记的结构，类似于第一实施例，通过简单的工艺产生了更高的对准精度。
这里，关于本实施例中的用于对准的下标记17和用于上对准的上标记18，通过用于对准的标记具有不同的二维几何形状或尺寸可以产生提供在表面内的识别对准标记位置的结构。
第三实施例
在第三实施例中，通过利用作为用于对准的标记的导电穿通栓塞与作为衬底表面内的穿通电极的导电穿通栓塞的相对位置产生提供用于对准的标记识别的结构。
图4A至4G是平面图，图示了本实施例的用于多芯片半导体器件的芯片结构。在图4A至4G中，示出了导电穿通栓塞和对准标记，未示出衬底。可以通过例如使用制造用于多芯片半导体器件的芯片的任意前述方法制造图4A至4G所示的用于多芯片半导体器件的芯片。
图4A至图4D图示了通过形成具有与导电穿通栓塞相同的二维几何形状的对准标记，以及利用用于布置导电穿通栓塞的位置和用于布置对准标记的位置之间的相对关系提供标识的例子。在图4A至图4D中，导电穿通栓塞19，21，23或25布置为在衬底表面内形成正方形网格。然后，一些栓塞从规则的布置中分立，以形成用于可以识别的对准标记的图形20，22和24。
更具体地说，在图4A和图4B中的导电穿通栓塞19和导电穿通栓塞21的网格布置中分别提供缺陷部分，且分别利用邻近于缺陷部分的栓塞作为用于对准的标记20和用于对准的标记22。
在图4C和图4D中，在一组网格-布置的导电穿通栓塞23和一组网格布置的导电穿通栓塞25的侧边中分别布置一组用于对准的标记24和一组用于对准的标记26，并且组24和26中的栓塞具有与组23和25中的栓塞相同的几何形状，以及组24和26中的栓塞数目分别小于组23和25的栓塞数目。
图4E至图4G图示了在分别以正方形网格形式(在图的下部中)布置的导电穿通栓塞27，29和31的衬底表面内的侧边中形成与导电穿通栓塞不同几何形状的用于对准的标记28，30和32的例子。尽管导电穿通栓塞27，29和31的截面是正方形，但是用于对准的标记28，30和32的截面是矩形。
因而，通过布置导电穿通栓塞和用于对准的标记可以容易地进行芯片的前和后表面的区分或旋转角度的确定。因此，类似于第一和第二实施例，不再需要用于形成对准标记的不需要工艺，并且可以通过本实施例中的简单且容易的方法稳定地制造具有提高对准精度的对准标记。
在如上所述的第一、第二和第三实施例中，用于对准标记的导电穿通栓塞可以具有其截面的最小宽度等于或小于其它导电穿通栓塞的最小宽度。作为这种结构的例子，图4F所示的二维结构图示了可以产生第三实施例的这些部分。
一般，根据其宽度改变用于填充穿通栓塞的条件，并且上述条件允许在相同条件下通过相同工艺与其它导电穿通栓塞同时形成用于对准的标记。因此，可以减小该制造工艺的负担。
尽管本实施例描述了采用用于对准的标记在芯片之间提供对准的情况，但是该标记可以用作用于形成互连的光刻法工艺中的对准标记，其中互连提供在导电穿通栓塞上形成的凸点电镀的相互耦合。当用于对准的标记用作用于光刻工艺的定位标记时，其最小宽度可以等于或小于其它导电穿通栓塞的最小宽度，以及考虑到定位精度，其最小宽度等于或小于1μm。具有这种结构。可以带来对准精度的进一步提高。
第四实施例
在第四实施例中，将描述用于层叠上述实施例中描述的用于多芯片半导体器件的芯片的方法和在该装配中采用的键合设备。
图5是流程图，图示了根据本实施例通过使用用于芯片的键合设备层叠用于多芯片半导体器件的芯片的方法。图6A，6B和6C是示意性剖面图，示出了用于层叠用于多芯片半导体器件的芯片的键合设备的结构。
图6A，6B和6C所示的键合设备33包括贴装头34，贴装器35，照相机36，照相机37和载物台38。上芯片39保持在连接到贴装器35的贴装头34中。载物台38支持下芯片40。设置照相机36和照相机37，以便分别使上芯片39的下表面和下芯片40的上表面成像。
将根据图5描述用于层叠芯片的工艺，图6A，6B和6C图示了在图5所述的工艺中在如图6A，6B和6C所示的下芯片40上的预定位置上贴装上芯片39的情况。
(1)管芯贴装
上芯片39和下芯片40被切割，并且将切割的下芯片40贴装在载物台38上，将切割的上芯片39贴装在键合设备33的贴装头34上(S1)。在该情况下，上芯片39和下芯片40中的至少任意一个是上述实施例所示的芯片，并且假定该芯片包括导电穿通栓塞且用于后表面对准的标记是可见的。
(2)用于对准的标记成像
通过照相机36和37分别从上方向拾取下芯片40的上表面，以及从下方向拾取上芯片39的下表面(S2)。可用的照相机的类型没有特别限制，只要可以进行如下所述图像处理。
(3)图像处理
在一个芯片上的至少两个位置上进行包括用于对准的标记的部分芯片的图像处理，以获得芯片平面中的中心位置(S3)。图6A示出了当确定芯片的坐标(中心位置)的工艺完成时的条件。
(4)移动
贴装头34或载物台38的XY轴被精确地移动，以精确地重合芯片39和40的位置(S4)。图6B图示了芯片移到用于提供连接的位置的条件。
(5)连接
贴装头34被垂直地降低，以使上芯片39连接到下芯片40(S5)。在此情况下，它被配置为具有精确地控制施加到凸点的负载的能力。图6C示出了提供这种连接的条件。
(6)加热/压缩键合/超声波连接
通过使用取决于采用的凸点的类型和贴装器结构的最佳方法在芯片之间粘结凸点(S6)。
(7)贴装头分离
贴装头34被升高，以从那里分开，尽管图6A，6B或6C中未示出(S7)。此后，如果芯片的层叠进一步继续(S8中的“是”)，那么它返回步骤1，并且进行对应于第三层或之上层的芯片装配。如果芯片的层叠完成(在S8中的“否”)，那么该工艺前进至基本封装工艺如封装模块(在插入板上贴装)等(S9)。
在上述工艺中，当在其上贴装的芯片之一是除第一至第三实施例描述的芯片之外的芯片时，可以通过例如识别芯片上形成的预定互连结构进行步骤3中的芯片位置的理解。
在本实施例中，在通过采用上述实施例中描述的芯片来层叠多个芯片的情况下，可以提高其对准精度。
由于芯片上的有效表面(其上形成元件的表面)与常规结构中的其它芯片的有效表面相对，所以层叠限于形成双层。另一方面，通过采用根据本实施例的方法形成三层或更多层的装配工艺成为可能。
例如，考虑到具有导电穿通栓塞的器件作为上芯片39，仅仅在芯片的前表面上具有用于对准的标记的情况下，或在利用孔或透明通孔作为用于对准的标记的情况下，不能照原样使用用于提供片上芯片键合的方法，并且在这些情况中，需要具有非标准结构的贴装器，如在头部具有用于透射光的透明孔的贴装器。
但是，另一方面，根据键合本实施例的用于多芯片半导体器件的芯片的方法，由于在芯片的前表面和后表面上设置了由导电穿通栓塞构成的用于对准的标记，所以可以精确地进行芯片两侧的对准。因此，通过重复与用于形成片上芯片双层的工艺相同的工艺可以获得具有多层体的多芯片半导体器件。如果通过不同的照相机36和37分别拾取待层叠的芯片的相对表面，那么显著地表现出该有利的效果。
第五实施例
在第五实施例中，将描述可以通过使用上述实施例描述的键合设备层叠用于多芯片半导体器件的芯片获得的多芯片半导体器件。在构成本实施例的多芯片半导体器件的芯片中，用于对准的标记结构假定为上述实施例中所示的结构。
图7是通过层叠用于多芯片半导体器件的两个芯片41和42形成的多芯片半导体器件的示意性剖面图。
在图7中，在用于多芯片半导体器件的芯片41中设置用于对准的标记43和导电穿通栓塞44。用于多芯片半导体器件的芯片42具有大于用于多芯片半导体器件的芯片41的芯片表面面积，并且用于多芯片半导体器件的芯片42是耦合在用于多芯片半导体器件的芯片41上的凸点。
采用用于对准的标记43，以比1μm更精细的精度在芯片表面内提供用于多芯片半导体器件的芯片41和用于多芯片半导体器件的芯片42的对准，然后键合这些对准的芯片，以获得多芯片半导体器件。这里，尽管在图中未示出，但是通过互连层或芯片上的凸点来电耦合到电源线或地线可以固定用于对准的标记43的任意电位。通过固定用于对准的标记43的电位，可以减小多芯片半导体器件在工作中发出的噪音。
图8是平面图，图示了具有包括晶片上层叠芯片结构的多芯片半导体器件。更具体地，图8图示了对应于下芯片的晶片45上布置分立芯片46并层叠芯片的结构。因而，下芯片本身不必是分立芯片并且晶片45也可以照原样应用。通过在晶片45上布置分立芯片46和层叠分立芯片完成多芯片模块之后，可以进行切割。而且，本实施例也可以应用于上芯片和下芯片都未必是分立芯片和照原样层叠多个晶片的情况。
另外，在层叠多个有源元件以形成多层体(三层或更多)的情况下，或在层叠没有诸如具有贴装在其上的穿通电极的间隔片等有源元件的情况下也可以应用根据上述实施例的用于多芯片半导体器件的芯片的键合设备。
下面将描述这种实施例。
图9是剖面图，图示了层叠多个有源元件以形成多层体的多芯片半导体器件的结构。
该剖面图图示了层叠芯片45至48以形成四层体的结构，且对于顶芯片45和底芯片48无导电穿通栓塞。对应于中间层的芯片46和芯片47包括导电穿通栓塞53和用于对准的标记54。此外，芯片45和芯片46通过凸点55电耦合，而元件形成表面(有效表面)49和元件形成表面50互相相对。而且，芯片46至48通过凸点55在某条件下电耦合，而在相同方向(在图中向上的方向)定向各个元件形成表面50至52。
这种多层状结构可以应用于相似类型的存储器多层叠层、不同类型的存储器的多层叠层、具有存储器和逻辑电路的混合贴装叠层、具有不同功能的逻辑电路的多层叠层以及具有不同衬底(Si和化合物半导体等)的LSI芯片的多层叠层。
因而，当芯片的层叠的层数目超过三层时，在芯片的前表面和后表面上比1μm更精细的对准是必需的，并且如果芯片包括上述实施例的用于对准的标记54，那么可以精确地进行其对准，而且可用的层数不受限制。
图10是剖面图，图示了多芯片半导体器件的结构，包括层叠的衬底，该衬底没有在其上贴装的诸如具有穿通电极的间隔片等有源元件。
图10中所示的多芯片半导体器件包括用于多芯片半导体器件的芯片57，具有穿通电极59的间隔片以及用于多芯片半导体器件的芯片56，通过凸点61电耦合以所述顺序从底部层叠所有这些芯片。在用于多芯片半导体器件的芯片56和用于多芯片半导体器件的芯片57中分别设置的元件形成表面62，并且元件形成表面63位于面对具有中间层的穿通电极58的间隔片的其各个侧边上。
这里，具有穿通电极58的间隔片指具有除在其上贴装的晶体管以外的元件(无源元件如互连、电容器、电感器、天线等)的半导体芯片。除上述之外，对于具有难以区分的前和后表面的芯片可以利用用于对准的标记60的不对称二维布置，如图10所示具有穿通电极58的间隔片。具有这种结构，具有穿通电极58的间隔片可以没有错误地更明确地贴装间隔片的前表面的预定位置处，间隔片具有用于其后表面的穿通电极58。
图11是剖面图，图示了具有在LSI芯片上贴装的光学器件的实施例。
图11所示的多芯片半导体器件包括用于具有在芯片上贴装的光学器件的多芯片半导体器件的芯片64，且具有一个结构，其中这些芯片通过凸点70在预定位置处电耦合。具有在其上贴装光学器件的芯片64包括导电穿通电极68和用于对准的标记69。用于多芯片半导体器件的芯片65的元件形成表面66和具有在其上贴装的光学器件的芯片64的光接收/光发射表面67设置在相同侧边上(图中的上侧)。
在半导体器件具有图11所示结构的情况下，由于功能的困难使半导体器件不能具有面向下的键合结构，即使在双层组件的情况下，在后表面上也需要用于对准的标记69。即使采用这种器件，通过使用上述实施例描述的结构在由芯片的前表面的处理中可以在芯片64的后表面上形成用于对准的标记69，且因此在此情况下本实施例也是有效的。
图12是剖面图，图示了底部芯片也具有穿通电极的实施例。
这里，图示了封装芯片为倒装球栅阵列(FCBGA)型封装的例子。图12所示的多芯片半导体器件包括在FCBGA衬底74上的用于多芯片半导体器件的芯片73、用于多芯片半导体器件的芯片72以及用于多芯片半导体器件的芯片71，所有这些芯片以所述顺序从底部布置并通过凸点81电耦合。用于多芯片半导体器件的芯片72对应于底层并且用于多芯片半导体器件的芯片73对应于包括导电穿通栓塞79和对准标记80的中间层。用于多芯片半导体器件的芯片71和用于多芯片半导体器件的芯片72的元件形成表面76和元件形成表面77分别相互相对。此外，在其相同侧边(在图中的上部)设置用于多芯片半导体器件的芯片73的元件形成表面78和用于多芯片半导体器件的芯片72的元件形成表面77。而且，在FCBGA衬底74的后表面上设置焊球75。
在图12中，用于对准的标记80被用于底部半导体芯片73和FCBGA衬底74的对准。除上之外，“FCBGA”是倒装球栅阵列的缩写，且是提高多管脚和更精细间距的封装的封装类型。
在上述实施例中图示的用于多芯片半导体器件的芯片包括用于对准的标记，并且可以以比1μm更精细的对准精度级别使用这种用于对准的标记来对准芯片。用于叠层芯片以形成多层体的层的可用数目不受限制，以及可以以比1μm更精细的精度级别进行布置。尽管根据优选实施例已经描述了本发明，但是对于所属领域的技术人员来说在此包含的公开仅仅用于本发明的说明性目的是显而易见的，且在不脱离发明的范围和精神的条件下，可以适当地采用他各种配置的结构或工艺。
例如，尽管上述实施例说明了为具有硅衬底的芯片设置对准标记的情况，但是上述实施例中描述的配置也可以广泛地应用于要求以更高的精度进行对准的其它类型的半导体芯片、衬底等。另外，上述实施例中描述的配置也可以应用于化合物半导体衬底或光学电路衬底(硅，石英)。
很明显本发明不局限于上述实施例，在不脱离本发明的范围和精神的条件下可以进行修改和改变。

Claims (20)

1.一种用于构成具有多个层叠半导体芯片的多芯片半导体器件的芯片，其包括：
衬底；以及
由贯穿所述衬底的导电材料构成的多个导电穿通栓塞，
其中所述的多个导电穿通栓塞包括第一导电穿通栓塞和与所述的第一导电穿通栓塞分开地设置的第二导电穿通栓塞，
其中所述的第一导电穿通栓塞和所述的第二导电穿通栓塞被配置为在平面图中有可见的区别，以及
其中所述第二导电穿通栓塞是用于对准的标记。
2.根据权利要求1的芯片，其中所述的第一导电穿通栓塞将所述衬底表面上设置的第一导电部件耦合到所述衬底的另一表面上设置的第二导电部件。
3.根据权利要求1的芯片，其中在所述衬底内设置的第一孔内设置所述第一导电穿通栓塞，以及其中在所述衬底内设置的第二孔内设置所述第二导电穿通栓塞，通过刻蚀掉所述衬底的预定区形成所述第一孔和所述第二孔。
4.一种用于多芯片半导体器件的芯片，在用于该多芯片半导体器件的一个芯片中包括两个或更多导电穿通栓塞，其中采用一个或多个所述导电穿通栓塞作为用于对准的标记，以及其中该芯片具有在用于所述多芯片半导体器件的所述芯片的前表面和/或后表面上提供可见地识别用于对准的所述标记的能力的结构。
5.根据权利要求4的芯片，其中用于对准的所述标记被配置为通过用于对准的所述标记的二维几何形状提供可见地识别的能力。
6.根据权利要求4的芯片，其中用于对准的所述标记配置为通过用于布置用于对准的所述标记与用于布置所述导电穿通栓塞的位置的相对位置提供可见地识别的能力。
7.根据权利要求4的芯片，其中在具有相同几何形状的所述芯片的前表面和后表面上设置用于对准的所述标记。
8.根据权利要求4的芯片，其中用于对准的所述标记具有其不对称的几何形状或不对称的布置。
9.根据权利要求4的芯片，其中用于对准的标记的所述导电穿通栓塞具有等于或小于其它导电穿通栓塞的最小宽度的其截面的最小宽度。
10.根据权利要求4的芯片，其中用于对准的所述标记采用的所述导电穿通栓塞的前表面和/或后表面覆有绝缘材料。
11.根据权利要求4的芯片，其中用于对准的所述标记是用于贴装的对准标记。
12.根据权利要求5的芯片，其中用于对准的所述标记是用于光刻工艺的定位标记。
13.根据权利要求12的芯片，其中用于光刻工艺的所述定位标记具有截面，截面的最小宽度等于或小于其它导电穿通栓塞的最小宽度，并且其最小宽度等于或小于1μm。
14.根据权利要求4的芯片，其中用于对准的所述标记所采用的至少部分所述导电穿通栓塞的电位被固定。
15.一种多芯片半导体器件，包括根据权利要求1的芯片和其它芯片的叠层形式，
其中所述第一导电穿通栓塞耦合到所述的其它芯片的导电部件，所述的其它芯片邻近所述芯片。
16.一种多芯片半导体器件，包括根据权利要求4的芯片和其它芯片的层叠形式，其中所述导电穿通栓塞耦合到所述的其它芯片的导电部件，所述的其它芯片邻近所述芯片。
17.一种用于多芯片半导体器件的芯片键合设备，其中，当通过所述键合设备层叠用于多芯片半导体器件的芯片时，通过利用用于对准的下述标记计算所述多芯片半导体器件的芯片位置，用于多芯片半导体器件的芯片包括用于多芯片半导体器件的一个芯片中的两个或更多导电穿通栓塞并且还包括用于对准的标记所采用的一个或多个所述导电穿通栓塞。
18.一种用于对准用于多芯片半导体器件的芯片的方法，其中当对准并且然后层叠用于多芯片半导体器件的芯片时，通过利用用于对准的下述标记对准用于所述多芯片半导体器件的所述芯片，用于多芯片半导体器件的芯片具有用于多芯片半导体器件的一个芯片中的两个或更多导电穿通栓塞并且包括用于对准的标记所采用的一个或多个所述导电穿通栓塞。
19.一种用于制造用于多芯片半导体器件的芯片的方法，包括：
刻蚀用于多芯片半导体器件的芯片，以形成两个或更多通孔；
用导电材料填充在所述刻蚀所述芯片中形成的所述两个或更多通孔；以及
通过在用所述导电材料填充所述两个或更多通孔的过程中重处理用于多芯片半导体器件的所述芯片的后表面来露出所述导电材料，用于多芯片半导体器件的所述芯片具有填充在其中的所述导电材料；
其中采用具有填充在其中的所述导电材料的一个或多个所述导电穿通栓塞作为用于对准的标记，以及
其中用于对准的所述标记和所述导电穿通栓塞中的其他的一个被配置为在用于多芯片半导体器件的所述芯片的前表面和/或后表面上在平面视图中有可见的区别。
20.根据权利要求19的方法，还包括在用所述导电材料的所述填充两个或更多通孔之后，在具有填充在其中的所述导电材料的一个或多个导电通孔的前表面和/或后表面中形成绝缘膜。
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