CN102386168A - 具有基板通孔(tsv)的基板中的对准标记 - Google Patents

具有基板通孔(tsv)的基板中的对准标记 Download PDF

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CN102386168A
CN102386168A CN2011102587882A CN201110258788A CN102386168A CN 102386168 A CN102386168 A CN 102386168A CN 2011102587882 A CN2011102587882 A CN 2011102587882A CN 201110258788 A CN201110258788 A CN 201110258788A CN 102386168 A CN102386168 A CN 102386168A
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substrate
alignment mark
tsv
conduction
conductive component
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CN102386168B (zh
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章鑫
蔡方文
林俊成
邱文智
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种装置，其包括基板和对准标记，所述对准标记包括穿透所述基板的导电基板通孔(TSV)。本发明还公开了一种形成该器件的方法。通过本发明的方法和器件，基板上的基板通孔对准的准确度高。

Description

具有基板通孔(TSV)的基板中的对准标记
技术领域
本发明涉及一种器件，具体的说，本发明涉及一种具有基板通孔的基板中的对准标记。
背景技术
为了形成三维(3D)集成电路结构，使用基板通孔(TSVs)将晶片的正面部件电连接到背面部件。例如，在正面上，可能有互连结构和金属凸块。在背面上，可能有金属凸块和再分配线。为了准确地互相对准正面部件和背面部件，需要实施双面对准。
一般，首先在晶片上形成正面部件，然后通过背面研磨以减薄晶片中的硅基板直到暴露出TSVs。将正面对准标记合并到正面部件中。为了定位正面对准标记，使用红外线(IR)对准系统从背面实施双面对准，其中IR对准系统发射的红外光穿透减薄了的硅基板，以到达正面对准标记。然后通过蚀刻到背面层和硅基板中，在晶片的背面制作背面对准标记。
由于IR对准系统的局限，以及进一步由于研磨了的硅基板的厚度变化，双面对准的准确度低，并且失准(轴心差misalignment)可高达约2μm。
发明内容
针对现有技术，本发明提供了一种器件，包括：基板；以及第一对准标记，所述第一对准标记包括穿透所述基板的第一导电基板通孔(TSV)。根据本发明所述的器件，其特征在于，所述第一对准标记包括多个穿透所述基板的第一导电TSV。
根据本发明所述的器件，其特征在于，所述多个第一导电TSV排列在矩形区域中。
根据本发明所述的器件，其特征在于，所述多个第一导电TSV对准成相互交叉的两条线。
根据本发明所述的器件，其特征在于，进一步包括在所述基板的背面上方的导电部件，其中所述导电部件非电连接到所述第一导电TSV。
根据本发明所述的器件，其特征在于，所述第一导电TSV是电浮置的。
根据本发明所述的器件，其特征在于，进一步包括在所述基板的背面上的介电层，并且其中所述第一导电TSV穿透所述介电层。
根据本发明所述的器件，其特征在于，所述基板为半导体基板，并且其中没有有源器件形成在所述半导体基板的相反表面上。
根据本发明所述的器件，其特征在于，所述基板为半导体基板，并且其中在所述半导体基板的正面上形成有源器件。
根据本发明所述的器件，其特征在于，进一步包括在所述基板的正面上的第二对准标记，其中所述第二对准标记包括金属层。
根据本发明所述的器件，其特征在于，进一步包括第二导电TSV，所述第二导电TSV穿透所述基板并且为非电浮置的。
根据本发明所述的器件，其特征在于，所述第一导电TSV和所述第二导电TSV具有基本相同的高度。
根据本发明所述的器件，其特征在于，所述第一导电TSV和所述第二导电TSV具有基本相同的顶视形状。
根据本发明所述的器件，其特征在于，进一步包括位于所述基板的背面上并且与所述第二导电TSV电连接的导电部件，其中所述导电部件包括再分配线和金属凸块中的至少一种。
一种形成器件的方法，所述方法包括：提供基板；在所述基板中形成第一导电基板通孔(TSV)和第二导电基板通孔(TSV)；以及在所述基板的背面上形成导电部件并且所述导电部件通过使用所述第一导电TSV作为对准标记与所述第二导电TSV电连接。根据本发明所述的方法，其特征在于，所述导电部件包括再分配线和金属凸块中的至少一种。
根据本发明所述的方法，其特征在于，所述导电部件非电连接到所述第一导电TSV。
根据本发明所述的方法，其特征在于，进一步包括在所述基板的正面上形成附加的对准标记。
根据本发明所述的方法，其特征在于，进一步包括在所述基板的正面上形成互连结构，其中所述互连结构非电连接到所述第一导电TSV。
通过本发明的方法和器件，基板上的基板通孔对准的准确度高。
附图说明
为了更好地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1到图7为根据实施例的制造和使用对准标记的中间阶段的横截面图；
图8示出了正面对准标记的顶视图；
图9A到图9G示出了由基板通孔(TSVs)形成的各种对准标记；
图10示出了用于形成TSVs的光刻掩模；以及
图11A到图11D示出了由沟槽型TSVs形成的各种对准标记。
具体实施方式
下面，详细讨论本发明优选实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式，而不用于限制本公开的范围。
根据实施例提供了新颖的双面对准标记以及其形成方法。根据实施例示出了制造双面对准标记的中间阶段。然后论述了实施例的变化。在各个附图和示出的实施例中，相同的附图编号用于标示出相同的元件。
参考图1，提供了包括基板10的晶片2。在一个实施例中，基板10为半导体基板(如凸块硅基板，尽管其可包括其它半导体材料例如III族元素，IV族元素，和/或V族元素)。集成电路器件(可包括晶体管)可形成在基板10的正表面10a上。在可选的实施例中，晶片2为中介层基板或封装基板，其中可不包括有源器件(例如晶体管)。然而，晶片2中可包括无源器件，例如晶体管和电容器。因此基板10可由半导体材料(如硅)形成或由介电材料形成。
在基板10的上方形成互连结构12(包括金属线和其中形成的通孔)，而且可将互连结构12与集成电路器件电连接。金属线和通孔可由铜或铜合金形成，而且可使用公知的镶嵌(damascene)工艺形成。互连结构12可包括公知的层间介电层(ILD)11和金属间介电层(IMDs)，该金属间介电层形成在ILD11的上方。
对准标记14形成在基板10的正面上，例如，可在第一级金属层(底部IMD层)中形成，尽管可在其它级金属层中形成。图8中示出了示例性对准标记14的顶视图。除了图8中所示的形状，对准对准标记14还可具有其他不同的形状。
将基板通孔(TSVs)20形成在基板10中，并且从基板10的正表面10a延伸到基板10中。取决于使用先通孔方法还是后通孔方法形成TSVs20，在互连结构12中TSVs20可延伸到ILD11(用于覆盖有源器件)中，而不延伸到IMD层中。可选地，TSVs20可穿透基板10，ILD11，以及可能穿透互连结构12。将隔离层22形成在TSVs20的侧壁上，并且使每个TSVs20与基板10电绝缘。隔离层22可由通常使用的介电材料例如氮化硅，氧化硅(例如，四乙基邻硅酸盐(TEOS)氧化物)等等形成，。
TSVs20包括功能性TSVs20A和对准标记TSVs20B。尽管只示出了一个对准标记TSV20B，但是还可以有多个对准标记TSVs20B，如图9A到图9G和图11A到图11D所示。可使用功能性TSVs20A将基板10正表面上的导电部件电连接到基板10背面上的导电部件。对准标记TSVs20B用于将晶片2的背面上的部件与晶片2正面上的部件对准。对准标记TSVs20B和对准标记14互相对准。在一个实施例中，功能性TSVs20A与对准标记TSVs20B同时形成。在可选的实施例中，通过单独的形成工艺在不同的时间形成功能性TSVs20A与对准标记TSVs20B。而且，功能性TSVs20A可与对准标记TSVs20B具有相同的直径，相同的间距，和/或相同的高度。可选地，功能性TSVs20A可与对准标记TSVs20B具有不同的直径，间距，和/或高度。然后在晶片2的正表面上形成金属凸块18。
参照图2，例如通过粘合剂25(其可为紫外线(UV)胶水)将晶片2连接到载体27上。接着，如图3所示，实施背面研磨以除去基板10的多余部分。可以进一步实施蚀刻，以削减(薄化，lower)基板10的背表面10b，使得TSVs20从背表面10b突出出来。
在图4中，形成钝化层24以覆盖基板10的背表面10b和TSVs20。在一个示例性实施例中，钝化层24包括氮化硅层24a和在氮化硅层24a上方的氮氧化硅层24b，尽管钝化层24可由不同的材料形成和/或具有不同的结构。
接着，使用图案化的光刻胶，蚀刻钝化层24的部分，暴露出TSVs20(包括功能性TSVs20A和对准标记TSVs20B)的末端。然后除去图案化的光刻胶，形成图5所示的结构。因此暴露的对准标记TSVs20B可用作对准标记32，在背面部件(如RDLs和/或金属凸块)的形成中，对准标记32用于对准，使得将晶片2的背面上的背面部件准确地对准到期望位置，以及对准到正面对准标记14。
图6示出了凸块底部金属化(UBM)层28的形成，例如可将其以覆盖的方式形成在钝化层24上和暴露的TSVs20上。可使用溅射法或其它合适的方法形成UBM层28。UBM层28可包括阻挡层28a和阻挡层28a上的种子层28b。在一些实施例中，阻挡层28a包括Ti层，Ta层，TiN层，TaN层或其组合物，尽管也可使用其它材料。在一些实施例中，种子层28b包括铜。
图7示出了晶片的背面上示例性背面部件的形成，其中背面部件可包括金属层，金属凸块，钝化层，微凸块，和/或类似物。在图7所示的示例性实施例中，背面部件30代表金属凸块和/或再分配线(redistribution line)(RDLs)。可以理解尽管只示出了一层金属凸块/RDLs，但是可以有一层或多层的RDLs以及在RDLs上方并与RDLs连接的金属凸块。在一个示例性实施例中，部件30的形成包括在UBM层28的上方形成掩模(未示出)，同时通过掩模中的开口暴露出UBM层28的一部分。然后实施电镀以将导电材料电镀到开口中以形成背面部件30。然后除去掩模，蚀刻UBM层28上最初被掩模覆盖的部分。还暴露出对准标记TSVs20B，并且对准标记TSVs20B可用于在附加部件(如背面部件30上方的RDLs和/或金属凸块)的形成中对准。
图9E到图9G示出了示例性对准标记32的顶视图，每一个对准标记32都由多个对准标记TSVs20B形成。当将多个对准标记TSVs20B分组以形成对准标记32时，可将多个对准标记TSVs20B排列成具有长度L和宽度W的矩形区域(也标记为32)，其中矩形区域可以没有功能性TSVs。长度L和宽度W可介于约50μm到约400μm之间，并且可介于约100μm到约200μm之间。
因此，矩形区域可具有比约400μm×400μm小或比约200μm×200μm小的顶视面积。
在图9A到图9G中，可将对准标记TSVs20B排列成不同的图案。例如，在图9A和图9F中，对准标记TSVs20B与相互交叉的线36A和36B对准。在图9B，图9C和图9G中，对准标记TSVs20B与终止在公共点40的线38A和38B对准。图9D和图9E示出了其它示例性图案。
图10示出了用于形成TSVs20的示例性光刻掩模33，其中，除了为了形成功能性TSVs20的图案20A’，在光刻掩模33中形成对准标记图案32’。对准标记图案32′限定了对准标记TSVs20B的图案，同时图案20A′限定了功能性TSVs20A的图案。
图11A到图11D示出了可选的实施例，其中对准标记32由沟槽型TSVs20B形成，沟槽型TSVs20B除了具有圆形的顶视形状，可具有其它形状，包括但不限于矩形，十字形以及其组合形状。可将沟槽型TSVs20B与功能性TSVs20A在同一时间或不同时间形成。类似的，沟槽型TSVs20B也穿透基板10。
通过使用实施例，可在功能性TSVs形成的同一时间形成对准标记。因此，节约了在传统对准标记形成工艺中产生的成本，传统对准标记形成工艺中包括形成光刻胶用于限定晶片2背面上的背面对准标记的图案，蚀刻晶片2用于形成背面对准标记，以及脱去光刻胶的步骤都被省去。而且，改进了形成对准标记的准确度。在传统对准标记形成技术中，轴心差可高达约2μm。然而在实施例中，轴心差减少至小于1μm。
根据实施例的部件包括基板，以及含有穿透基板的导电TSV的对准标记。
根据又一实施例的部件包括具有正表面和背表面的半导体基板；穿透半导体基板的功能性TSV；在半导体基板的正表面的有源器件；在半导体基板的正表面上包括多个金属层的互连结构；接触半导体基板的背表面的介电层；以及包括多个TSVs的对准标记。多个TSVs穿透半导体基板和介电层，其中没有再分配线和金属凸块在半导体基板的背面上以及与多个TSVs电连接。
根据实施例的部件包括具有正表面和背表面的半导体基板；在半导体基板中并且从正表面延伸到背表面的功能性TSV；在半导体基板的正表面上包括多个金属层的互连结构；在半导体基板的正表面上的对准标记；接触半导体基板的背表面的介电层；以及多个穿透半导体基板的TSVs。没有再分配线和金属凸块在半导体基板的背面上形成以及与多个TSVs电连接。
根据实施例的部件包括提供基板；在基板中形成第一和第二导电TSV；以及在基板的背面上形成导电部件并且与第二导电TSV电连接。使用第一导电TSV作为对准标记来实施形成导电部件的步骤。没有形成附加的导电部件以电连接到第一导电TSV并且在同一级作为导电部件。
根据实施例的部件包括提供基板；在基板中形成功能性TSV和多个TSVs，其中将多个TSVs分组以形成对准标记；在基板的正面上形成互连结构；研磨基板的背面直到暴露出功能性TSV和对准标记；形成接触基板的背表面，功能性TSV以及对准标记的介电层；蚀刻介电层以暴露出功能性TSV和对准标记；形成凸块底部金属化(UBM)层以覆盖介电层并且接触功能性TSV和对准标记；以及在功能性TSV上方直接形成导电部件并且该导电部件与功能性TSV电连接，其中形成导电部件的步骤通过使用用于对准的对准标记来实施。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种器件，包括：
基板；以及
第一对准标记，所述第一对准标记包括穿透所述基板的第一导电基板通孔(TSV)。
2.根据权利要求1所述的器件，其特征在于，所述第一对准标记包括多个穿透所述基板的第一导电TSV。
3.根据权利要求2所述的器件，其特征在于，所述多个第一导电TSV排列在矩形区域中。
4.根据权利要求2所述的器件，其特征在于，所述多个第一导电TSV对准成相互交叉的两条线。
5.根据权利要求1所述的器件，其特征在于，进一步包括在所述基板的背面上方的导电部件，其中所述导电部件不与所述第一导电TSV电连接。
6.根据权利要求1所述的器件，其特征在于，所述第一导电TSV是电浮置的。
7.根据权利要求1所述的器件，其特征在于，进一步包括在所述基板的背面上的介电层，并且其中所述第一导电TSV穿透所述介电层。
8.根据权利要求1所述的器件，其特征在于，所述基板为半导体基板，并且其中没有有源器件形成在所述半导体基板的相反表面上。
9.一种形成器件的方法，所述方法包括：
提供基板；
在所述基板中形成第一导电基板通孔(TSV)和第二导电基板通孔(TSV)；以及
在所述基板的背面上形成导电部件并且所述导电部件通过使用所述第一导电TSV作为对准标记与所述第二导电TSV电连接。
10.根据权利要求9所述的方法，其特征在于，进一步包括在所述基板的正面上形成互连结构，其中所述互连结构不与所述第一导电TSV电连接。
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