TWI620299B - 用於封裝的對準標記設計 - Google Patents

用於封裝的對準標記設計 Download PDF

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TWI620299B
TWI620299B TW103138308A TW103138308A TWI620299B TW I620299 B TWI620299 B TW I620299B TW 103138308 A TW103138308 A TW 103138308A TW 103138308 A TW103138308 A TW 103138308A TW I620299 B TWI620299 B TW I620299B
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Taiwan
Prior art keywords
alignment mark
communication
device die
pillars
shaping material
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TW103138308A
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TW201545305A (zh
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黃立賢
陳憲偉
蕭景文
葉德強
鄭心圃
余振華
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台灣積體電路製造股份有限公司
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Abstract

封裝包含裝置晶粒、將位於其中的該裝置晶粒塑形之塑形材料、穿透該塑形材料的連通柱，以及穿透該塑形材料的對準標記。重佈線係位於該塑形材料的一側上。該重佈線係電性耦合至該連通柱。

Description

用於封裝的對準標記設計
本揭露涉及一種用於封裝的對準標記設計。
現代電路的製程典型需要數個步驟。首先，在半導體晶圓上形成積體電路，該半導體晶圓含有多個相同的半導體晶片，其各自包括積體電路。而後，從該晶圓切割下該半導體晶片，並且將其封裝。封裝製程有兩個主要目的：保護精緻的半導體晶片，並且將內部積體電路連接至外部接腳(pin)。
隨著對於更多功能之需求增加，因而發展層疊封裝(package-on-package，PoP)技術，接合二或多個封裝以擴展封裝的整合能力。由於高度整合，元件之間的連接路徑縮短而改良所得PoP封裝的電子效能。使用PoP技術，使得封裝設計更具彈性並且較簡單。亦縮短上市時間。
根據本申請案揭示內容的一些實施方式，封裝包含裝置晶粒、塑形位於其中的該裝置晶粒之塑形材料、穿透該塑形材料的連通柱、以及穿過該塑形材料的對準標記。重佈線係位於該塑形材料的一側 上。該重佈線係電性耦合至該連通柱。
根據本申請案揭示內容的一些其他實施方式，封裝包含裝置晶粒，其具有金屬柱於該裝置晶粒的表面上，複數個連通柱環繞該裝置晶粒，以及對準標記。該對準標記係電性浮接。塑形材料塑形該裝置晶粒、該對準標記以及該複數個連通柱。第一複數個重佈線係位於該塑形材料的第一側上。第二複數個重佈線係位於該塑形材料的第二側上，該第二側係與該第一側對立。該第一複數個重佈線係透過該複數個連通柱而電性耦合至該第二複數個重佈線。
根據本申請案揭示內容的其他實施方式，方法包含同時形成連通柱與對準標記，以及放置裝置晶粒相鄰於該連通柱與該對準標記。使用該對準標記用於對準而進行該放置步驟。該方法進一步包含於塑形材料中塑形該連通柱、該對準標記以及該裝置晶粒，並且進行平面化作用，以暴露該連通柱、該對準標記以及該裝置晶粒的金屬柱。形成複數個重佈線以電性連接至該連通柱以及該裝置晶粒的該金屬柱。
20‧‧‧載體
22‧‧‧釋放層/黏著層
24‧‧‧介電層
26、26A、26B‧‧‧重佈線(RDL)
28‧‧‧介電層
30、30A、30B‧‧‧開口
32‧‧‧連通柱
32A‧‧‧連通柱/對準標記
32B‧‧‧連通柱
34‧‧‧設計區域
36‧‧‧裝置晶粒
38‧‧‧金屬柱
40‧‧‧頂部介電層
42‧‧‧鈍化層
45‧‧‧晶粒附接膜(DAF)
44‧‧‧塑形材料
46‧‧‧介電層
48‧‧‧開口
50‧‧‧重佈線(RDL)
52‧‧‧介電層
54‧‧‧開口
56‧‧‧重佈線(RDL)
57‧‧‧介電層
59‧‧‧開口
60‧‧‧凸塊下金屬層(UBM)
62‧‧‧電性連接器
64‧‧‧載體
66‧‧‧黏著劑
68‧‧‧膠帶
70‧‧‧辨識標記
72‧‧‧開口
74‧‧‧槽
76‧‧‧焊料區
78‧‧‧虛線區
100‧‧‧封裝
102‧‧‧封裝
104‧‧‧切割線
106‧‧‧槽
200‧‧‧封裝
202‧‧‧裝置晶粒
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之各方面。注意，根據產業之標準實施方式，各種特徵並非依比例繪示。實際上，為了清楚討論，可任意增大或縮小各種特徵的尺寸。
圖1至14係根據一些實施方式說明在製造封裝的中間階段之橫切面圖式與俯視圖。
圖15至19係根據一些實施方式說明包含穿孔與對準標記之範例封裝的俯視圖。
圖20係根據一些實施方式說明形成封裝的流程之圖式。
以下揭示內容提供許多不同的實施方式或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施方式，亦可包含在該第一與第二特徵之間形成其他特徵的實施方式，因而該第一與第二特徵可並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施方式與/或所討論架構之間的關係。
再者，本申請案可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向)，並且可相應解釋本申請案使用的空間對應描述。
圖1至14係根據實施方式說明在封裝製造的中間階段之橫切面圖式與俯視圖。圖1至14所示之步驟亦概示於圖20所示之製程流程300中。在後續討論中，參閱圖20所示之製程步驟，說明圖1至14所示之製程步驟。
圖1說明載體20與形成於該載體20上的釋放層22。載體20可為玻璃載體、陶瓷載體或類似物。載體20可具有圓的俯視形狀，並且可為矽晶圓的尺寸。例如，載體20可具有8吋直徑、12吋直徑或類似者。釋放層22可由聚合物為基礎之材料(例如，光熱轉換(LTHC)材料)形成，可由在後續步驟中形成的上層結構沿著載體20而將其移除。在一些實施方式中，釋放層22係由環氧化合物為基礎的熱釋放材料形成。在其他實施方式中，釋放層22係由紫外線(UV)膠形成。釋放層22可為 液體並且硬化。在其他實施方式中，釋放層22係層疊膜，並且層疊於載體20上。釋放層22的頂部表面被推平，並且具有高程度的共平面性。在釋放層22上形成介電層24。在一些實施方式中，介電層24係由聚合物形成，其亦可為光敏材料，例如聚苯并噁唑(polybenzoxazole，PBO)、聚亞醯胺、苯并環丁烯(BCB)、或類似物，可使用光微影蝕刻製程而輕易將其圖案化。在其他實施方式中，介電層24可由例如氮化矽之氮化物、例如氧化矽之氧化物、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜之磷矽酸鹽玻璃(BPSG)、或類似物形成。
參閱圖2，在介電層24上方形成重佈線(RDL)26。由於RDL 26係位於裝置晶粒36的背面(backside)上，因而亦稱為背面RDL(圖5A)。RDL 26可包含RDL 26B，並且可包含或可不包含RDL 26A，若形成RDL 26A，擇其將電耦合至後續行程的對準標記。RDL 26的形成可包含在介電層24上方形成晶種層(未繪示)，在該晶種層上方形成例如光阻之圖案化的遮罩(未繪示)，而後在暴露的晶種層上形成金屬電鍍。而後，移除圖案化的遮罩以及該圖案化遮罩所覆蓋的部分之晶種層，留下RDL 26，如圖2所示。在一些實施方式中，該晶種層係包括鈦層與位於該鈦層上方之銅層。例如，可使用物理蒸氣沉積(PVD)形成該晶種層。例如，可使用無電電鍍而進行該電鍍。
參閱圖3，在RDL 26上，形成介電層28。介電層28的底部表面可與RDL 26與介電層24的頂部表面接觸。在一些實施方式中，可由聚合物形成介電層28，該聚合物可為光敏材料，例如PBO、聚亞醯胺、BCB或類似物。在其他實施方式中，介電層28係由例如氮化矽之氮化物、例如氧化矽之氧化物、PSG、BSG、BPSG或類似物而形成。而後，將介電層28圖案化，於其中形成開口30。因此，透過介電層28中的開口30而暴露RDL 26。開口30包含30B，並且可包含或可不包含 30A。例如，如果不形成RDL 26A，則亦不形成開口30A。
參閱圖4A，形成金屬柱32(包含32A與32B)。在本申請案的說明內容中，由於金屬柱32穿透後續形成的塑形材料，因此金屬柱32亦稱為連通柱(through-via)32。根據本發明的一些實施方式，藉由電鍍形成連通柱32。連通柱32的電鍍可包含在層28上方，形成覆蓋晶種層(blanket seed layer)(未繪示)，並且延伸至開口30中，形成且圖案化光阻(未繪示)，以及在透過該光阻中的該開口而暴露之部分的晶種層上，電鍍連通柱32。而後，移除該光阻以及該光阻所覆蓋之該部分的晶種層。連通柱32的材料可包含銅、鋁或類似物。連通柱32為桿狀。連通柱32的俯視形狀可為圓形、矩形、正方形、六邊形或類似者。
連通柱32係包含32A與32B。圖4B係說明連通柱32A與32B的俯視圖。在一些實施方式中，連通柱32B配置為列與欄。最外面連通柱32B的外部邊界可定義區域34，此後，其亦稱為設計區域34。設計區域34外部不形成連通柱32B與RDL，並且設計區域34外部不放置裝置晶粒。連通柱32B係作為連通柱32B之對立端上的電性互耦合特徵(electrically inter-coupling features)。另一方面，連通柱32A係作為對準標記，並且因而有時稱為對準標記32A。連通柱32A可不作為裝置與特徵的電性耦合。
根據本發明的一些實施方式，連通柱32A係位於設計區域34外部。根據其他實施方式，連通柱32A亦可位於設計區域34內部。在一些實施方式，為了易於辨識，連通柱32A可具有不同於連通柱32B的俯視形狀以及/或不同的尺寸。例如，如圖4B所示，連通柱32A為矩形或正方形的俯視形狀，而連通柱32B為圓形的俯視形狀。
圖5係說明裝置晶粒36的置放位置。裝置晶粒36係經由晶粒附接膜(die-attach film，DAF)45而貼附至介電層28，該晶粒附接膜45可為黏著膜。裝置晶粒36可為邏輯裝置晶粒，其包含邏輯電晶體於其中。 在一些範例實施方式中，裝置晶粒36係設計用於行動應用的晶粒，並且可為電源管理積體電路(power management integrated circuit，PMIC)、收發器(TRX)晶粒或是類似物。雖然本申請案係說明一種裝置晶粒36，但是可在介電層28上方，放置更多裝置晶粒。
在一些範例實施方式中，形成金屬柱38(例如銅柱)作為裝置晶粒36的最頂部分，其中金屬柱38係電性耦合至裝置晶粒36中例如電晶體之積體電路裝置。在一些實施方式中，聚合物填充相鄰金屬柱38之間的間隙，以形成頂部介電層40，其中頂部介電層40亦可位於鈍化層42的頂部並且接觸鈍化層42。在一些實施方式中，可由PBO形成聚合物層40。在一些實施方式中，鈍化層42包括氮化矽、氮氧化矽、氧化矽、或其多層。
接著，在裝置晶粒36上，將塑形材料44塑形。塑形材料44填充相鄰連通柱32之間的間隙以及連通柱32與裝置晶粒36之間的間隙。塑形材料44可包含塑形化合物、塑形底膠(underfill)、環氧化合物或樹脂。塑形材料44的頂部表面係高於金屬柱38的頂端。
接著，進行例如化學機械拋光(CMP)步驟或研磨步驟之平面化，以薄化塑形材料44直到暴露連通柱32與金屬柱38。研磨使得連通柱32的頂端實質上與金屬柱38的頂部表面齊平(共平面)，並且與塑形材料44的頂部表面實質上共平面。
圖5B概示說明圖5A中的結構之俯視圖。在裝置晶粒36的置放中，對準標記32A係用以對準裝置晶粒36的位置，以確保將裝置晶粒36放置於理想的位置，以及確保裝置晶粒36不會由其預期的位置與方向偏移或旋轉。藉由決定裝置晶粒36相對於對準標記32A的位置之相對位置，而進行該對準。
圖5C係說明包含放置在載體20上的更多裝置晶粒36與連通柱32之俯視圖，其俯視圖為圓形。類似於裝置晶粒的形成，根據本發明之 實施方式所形成的結構被鋸為複數個封裝，各自包含裝置晶粒36與其周圍連通柱32。可透過對準相同封裝內之相應的對準標記32A，而對準各個裝置晶粒36的放置。
參閱圖6，形成介電層46。在一些實施方式中，介電層46係由例如PBO、聚亞醯胺或類似物之聚合物而形成。在其他實施方式中，介電層46係由氮化矽、氧化矽或類似物而形成。在介電層46中形成開口，以暴露連通柱32B以及金屬柱38。可透過光微影蝕刻製程而進行開口48的形成。根據本發明揭示內容之實施方式，連通柱32A上方，不形成開口，因此，不暴露連通柱32A。在其他實施方式中，可經由一些開口48而暴露連通柱32A。
根據一些實施方式，亦使用對準標記32A作為對準標記，而進行開口48的形成，使得開口48可正確對準個別連通柱32與金屬柱38。
接著，參閱圖7，形成重佈線(RDL)50以連接至金屬柱38與連通柱32B。RDL 50亦可互連金屬柱38與連通柱32B。RDL 50包含在介電層46上方的金屬軌跡(金屬線)，以及穿孔延伸至開口48中以電性連接至連通柱32B與金屬柱38。在一些實施方式中，在電鍍製程中形成RDL 50，其中每一個RDL 50包含晶種層(未繪示)以及位於該晶種層上方的電鍍金屬材料。可由相同或不同的材料形成該晶種層與該電鍍材料。RDL 50可包括金屬或包含鋁、銅、鎢及其合金之金屬合金。
參閱圖8，在RDL 50與介電層46上方，形成介電層52。可使用聚合物形成介電層52，該聚合物可與介電層46之材料相同。例如，介電層52可包括PBO、聚亞醯胺、BCB或類似物。或者，介電層52可包含非有機介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽或類似物。亦於介電層52中形成開口54，以暴露RDL 50。可透過光微影蝕刻製程而進行開口54的形成。
圖9係說明RDL 56的形成，其係透過開口54(圖8)而電連接至RDL 50。可採用與形成RDL 50類似的方法與材料而形成RDL 56。由於RDL 50與56位於裝置晶粒36的正面(front-side)上，因而亦稱為正面RDL。
如圖10所示，形成附加介電層57，用以覆蓋RDL 56與介電層52，該附加介電層57可為聚合物。介電層57亦可與用於形成介電層46與52相同之聚合物。而後，在介電層57中形成開口59，以暴露RDL 56的金屬墊部分。
圖11係根據一些範例實施方式說明凸塊下金屬層(Under-Bump Metallurgy，UBM)60與電性連接器62的形成。UBM 60的形成可包含沉積與圖案化。電性連接器62的形成可包含將焊球置放在UBM 60之暴露部分上，而後將該焊球回流。在其他實施方式中，電性連接器62的形成包含進行電鍍步驟，在RDL 56的上方形成焊料區，而後將該焊料區回流。電性連接器62亦可包含金屬柱或是金屬柱與焊料蓋，其亦係可透過電鍍而形成。在本申請案的說明內容中，包含裝置晶粒36、連通柱32、塑形材料44、以及塑形材料44對側上的對應RDL與介電層之組合結構稱為封裝100，其可為具有圓形俯視形狀的複合晶圓。
接著，封裝100係自載體20脫離。亦自封裝100移除黏著層22。所得到的結構如圖12所示。可藉由將例如UV光或雷射的光投射在黏著層22上，以分解黏著層22而進行該脫離。在一些實施方式中，封裝100進一步透過黏著劑66而貼附至載體64，其中電性連接器62面對且可接觸該黏著劑66。
而後，將膠帶68貼附至暴露的介電層24上。而後，在膠帶68上進行雷射標記，形成辨識標記70。辨識標記70因而成為膠帶68的凹處，並且可攜帶個別封裝的辨識資訊。辨識標記70可包含字母、數字或是其他可辨識的圖案。可透過雷射鑽孔而進行辨識標記70的形成。
參閱圖13，在膠帶68與介電層24中形成開口72，因而將RDL 56的金屬墊部分暴露至開口72。可透過雷射鑽孔或是光微影蝕刻製程而進行開口72的形成。
在後續步驟中，自封裝100移除載體64與黏著劑66。進行晶粒切割步驟(die saw step)，將封裝100鋸成複數個封裝102，其各自包含裝置晶粒36、連通柱32B以及對準標記32A。根據一些實施方式，在晶粒切割步驟中，保持槽(kerve)74不靠近對準標記32A。據此，所得到的封裝102包含對準標記32A與連通柱32B。
圖14係說明封裝102與另一封裝200的接合。根據一些實施方式，透過焊料區76進行該接合，其係將RDL 26B中的金屬墊接合至上方封裝200中的金屬墊。在一些實施方式中，封裝200包含裝置晶粒202，其可為記憶體晶粒，例如靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒或是類似物。在一些範例實施方式中，該記憶體晶粒亦可接合至封裝基板204。
在圖13或14所示之封裝102中，對準標記32A可與封裝102與200中的積體電路裝置電性絕緣。在一些實施方式中，對準標記32A可為電氣浮接(electrically floating)。根據一些實施方式，如圖14所示，連通柱32A可實體連接至一些金屬特徵，例如RDL 26A。在其他實施方式中，不形成虛線區78中的金屬特徵。這可藉由不形成圖2中的RDL 26A與圖3中的開口30A而達成。當不形成金屬特徵RDL 26A時，對準標記32A的對立表面(所示之頂部表面與底部表面)整體不與任何傳導特徵接觸。再者，每一個對準標記32A以及電性連接至該對準標記32A的所有傳導特徵(例如RDL 26A)整體可藉由介電層與塑形材料44而完全在封裝102內部絕緣。
圖15係概示說明封裝100(圖13)與封裝100中的封裝102之俯視圖。為了顯示連通柱32B與對準標記32A的細節，誇大封裝102的相對 尺寸(相對於封裝100的尺寸)。如圖15所示，藉由切割線(scribe line)104而將封裝102彼此分離，其係切割槽(sawing kerve)必須穿過的區域。實際的槽如106所示，並且比切割線104更窄。設計槽106與切割線104的寬度，使得封裝100的切割具有變化而槽106仍在切割線104之內。
對準標記32A係位於切割線104的外部，因而不會被切割。這是有利的，因為對準標記32A的高度等於裝置晶粒36的厚度(圖13)並且具有大體積，因而對準標記32A可不利地影響切割製程。另一方面，對準標記32A係位於設計區域34的外部，因而在對準製程中可被輕易辨識。
根據一些實施方式，直徑D1(或是連通柱32B的長度與寬度)係在約150微米至約300微米的範圍中。對準標記32A的長度L1與寬度W1係在約100微米至約300微米的範圍中。對準標記32A與切割線104之間的距離D2與D3係等於或大於對準標記32A的個別長度L1與寬度W1。然而，可理解本申請案說明內容中的值係僅作為範例，並且可改為不同的值。
在圖15所示的實施方式中，在每一個封裝102中，有兩個對角放置的對準標記32A，其中該對準標記32A係與封裝102的對立角相鄰。圖16係根據其他實施方式說明封裝102的俯視圖，其中形成兩個對準標記32A相鄰於封裝102的兩個角，其中該兩個角係由封裝102之相同邊緣所形成的相鄰角。在圖17的實施方式中，形成對準標記32A相鄰於封裝102之四個角的每一個角。
圖18係根據其他實施方式說明封裝102的俯視圖，其中封裝102包含二或多個裝置晶粒。例如，在所示的封裝102中，有兩個裝置晶粒36，各自受到形成環狀的複數個連通柱32B包圍。結合的設計區域34包含裝置晶粒36與各自的周圍連通柱32B於其中。同樣地，對準標 記32A係放置於該結合的設計區域34之外部。
在圖18中，兩個裝置晶粒36係對準平行於個別封裝102之邊緣的直線。圖19係說明封裝102的俯視圖，其中裝置晶粒36係未對準(misaligned)。在這些實施方式中，設計區域34並非簡單的矩形區。更確切而言，設計區域34包含兩個彼此結合的矩形區。
在圖15至19的各個圖式中，對準標記32A係亦作為形成個別封裝102中的對準。關於該對準製程，可參閱圖6與7。
圖20係概示說明圖1至11之製程的流程圖。該流程簡述於此。該流程的細節可參閱圖1至14的說明內容。在步驟302中，在載體上形成背面RDL 26，如圖1至3所示。在圖20的流程之步驟304中，形成連通柱32B與對準標記32A，以連接背面RDL 26，以及個別的形成製程係如圖4A與4B所示。在圖20的流程之步驟306中，放置裝置晶粒36，以及個別的形成製程係如圖5A、5B與5C所示。使用對準標記32A用於對準而進行裝置晶粒36的放置。在圖20的流程之步驟308與310中，形成正面RDL 50與56，以及個別的形成製程係如圖6至9所示。亦可使用對準標記32A用於對準而進行底部介電層中開口的形成。在圖20的流程之步驟312中，形成UBM 60與焊料區62，以及個別的形成製程係如圖10與11所示。在圖20的流程之步驟314中，膠帶68係附貼至個別封裝的背面，以及個別的形成製程係如圖12所示。在圖20的流程之步驟316中，以形成的UBM與焊料區形成開口。切割該封裝，並且進行進一步的接合製程。個別的形成製程係如圖13與14所示。
本發明揭示內容的實施方式具有一些有利的特徵。藉由形成該複數個封裝各自的對準標記，可正確地置放該裝置晶粒。因而，實質上排除或是至少降低該裝置晶粒相對於該連通柱的偏移與旋轉。再者，同時形成該對準標記與該連通柱(用於電性連接)，因而不造成額外的製造成本。
前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍，以及熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本申請案揭示內容之精神與範圍。

Claims (10)

  1. 一種半導體封裝，其包括：裝置晶粒；塑形材料，其塑形位於其中的該裝置晶粒；複數個連通柱，其穿透該塑形材料；對準標記，其穿透該塑形材料；以及重佈線，其係位於該塑形材料的一側上，其中該重佈線係電性耦合至該複數個連通柱，其中該對準標記包括與該塑形材料之表面齊平的表面；該複數個連通柱定義設計區域，該裝置晶粒係位於該設計區域中，以及該對準標記係位於該設計區域的外部。
  2. 如請求項1所述之半導體封裝，其中該對準標記係電性浮接，或該對準標記的表面與該連通柱的表面齊平。
  3. 如請求項1所述之半導體封裝，其中該對準標記包括與該裝置晶粒的金屬柱之表面齊平的表面，其中該對準標記之該表面的整體係與介電材料接觸。
  4. 如請求項1所述之半導體封裝，其中該複數個連通柱各自將位在該塑形材料之對側上的傳導特徵互連。
  5. 一種半導體封裝，其包括：裝置晶粒，其包括位於該裝置晶粒之表面上的金屬柱；複數個連通柱，其係包圍該裝置晶粒；對準標記，其中該對準標記係電性浮接；塑形材料，其係塑形位於其中的該裝置晶粒、該對準標記以及該複數個連通柱，其中該對準標記包括與該塑形材料之表面齊平的表面；第一複數個重佈線，其係位於該塑形材料的第一側上；以及第二複數個重佈線，其係位於該塑形材料的第二側上，該第二側係與該第一側對立，其中該第一複數個重佈線係透過該複數個連通柱而電性耦合至該第二複數個重佈線。
  6. 如請求項5所述之半導體封裝，其中該對準標記包括與該複數個連通柱之第一表面齊平的第一表面，以及與該複數個連通柱之第二表面齊平的第二表面。
  7. 如請求項5所述之半導體封裝，其中該對準標記的表面係與該金屬柱的表面齊平，或該對準標記相較於該封裝中的所有連通柱係最接近該封裝的一角。
  8. 一種半導體封裝之製造方法，其包括：同時形成複數個連通柱與對準標記，該複數個連通柱定義設計區域；置放裝置晶粒相鄰於該連通柱與該對準標記，其中係使用該對準標記用於對準而進行該置放，該裝置晶粒係位於該設計區域中，以及該對準標記係位於該設計區域的外部；於塑形材料中塑形該連通柱、該對準標記以及該裝置晶粒；進行平面化作用，以暴露該連通柱與該對準標記，其中該對準標記包括與該塑形材料之表面齊平的表面；以及形成第一複數個重佈線，其係電性連接至該連通柱。
  9. 如請求項8所述之半導體封裝之製造方法，進一步包括：在形成該第一複數個重佈線之前，形成介電層，以覆蓋該成形材料、該裝置晶粒、該連通柱以及該對準標記；以及形成暴露該連通柱的開口，其中該第一複數個重佈線延伸至該開口中，以連接至該連通柱，以及其中使用該對準標記用於對準而進行形成該開口。
  10. 如請求項8所述之半導體封裝之製造方法，其中該平面化作用造成暴露該裝置晶粒的金屬柱，以及該第一複數個重佈線之一係電性連接至該金屬柱。
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