TWI426582B - 半導體裝置之製造方法及使用於其中之半導體製造裝置 - Google Patents

半導體裝置之製造方法及使用於其中之半導體製造裝置 Download PDF

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TWI426582B
TWI426582B TW100104680A TW100104680A TWI426582B TW I426582 B TWI426582 B TW I426582B TW 100104680 A TW100104680 A TW 100104680A TW 100104680 A TW100104680 A TW 100104680A TW I426582 B TWI426582 B TW I426582B
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substrates
semiconductor device
processing unit
manufacturing
cutting
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TW100104680A
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TW201125077A (en
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Renesas Electronics Corp
Renesas Northern Japan Semiconductor Inc
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Description

半導體裝置之製造方法及使用於其中之半導體製造裝置
本發明係關於半導體製造技術，特別是關於應用在一次成形後之切割之產能提升有效之技術。
先前之基板之分割方法係，於複數之電子零件集合之狀態於其上形成配線圖案之際，以與配線圖案同一方法形成成為分割標準之基準標記，將上述基準標記作為基準分割複數電子零件(例如，參照專利文獻1)。
又，先前，形成複數個電子零件，且為形成樹脂之母基板所成之電子裝置，具備用於單片化之切割時之辨識標記(例如，參照專利文獻2)。
[專利文獻1]
特開平11-274357號公報(圖4)
[專利文獻2]
特開2002-246336號公報(圖2)
發明所欲解決之課題
本發明者為，於使用可取多數個之基板之半導體裝置之組裝，研究於樹脂密封後進行切割單片化之組裝之結果，發現如下之問題點。
即，樹脂密封後，於藉由切割切斷基板之際，有需要將顯示基板之切割位置之對準用標記自動辨識，惟由於辨識與切割之基台為同一基台，各無法同時進行辨識與切割，於生產性有產生損失之問題。
再者，若減少自動辨識點之數圖謀產能提升則，切斷定位精度降低，可取多數個之基板為多層配線基板之情形，由於內部配線之線寬之分散或位置偏移之量大，有引起配線短路不良之可能性之問題。
特別是，因多針化而使多層配線基板之配線層數增加則，由於容易產生配線短路不良，因此，無法避免因減少自動辨識點，使工程可靠度之降低。
再者，對配線施以鍍敷之際，採用相對成本較低之電解鍍敷之情形為多，於施以電解鍍敷之配線，於各配線層需要有供電用配線。此種情形，於樹脂密封後之切割時(單片化時)需將該供電用配線確實地切斷，惟因多針化而使多層配線基板之配線層數增加則，由於在層間之供電用配線之位置偏移量變大，配線短路不良之可能性變大而成問題。
本發明之目的係在於提供圖謀產能提升之半導體裝置之製造方法及其使用於其中之半導體製造裝置。
又，本發明之其他目的係提供圖謀提升切割精度之半導體裝置之製造方法及其使用於其中之半導體製造裝置。
本發明之前述及其他目的與新穎之特徵，將以本說明書之記述及所附圖面可明瞭。
 解決課題之手段
於本案所揭示之發明之中，將代表性者之概要簡單地說明則如下。
即，本發明係，具有：準備複數之可取多數個之基板之步驟；於前述可取多數個之基板搭載半導體晶片之步驟；將搭載於前述複數可取多數個之基板之複數半導體晶片樹脂密封之步驟；於前述樹脂密封步驟後，對前述複數可取多數個之基板之中第1可取多數個之基板進行圖像辨識，其後，藉由切割前述第1可取多數個之基板單片化的同時，圖像辨識第2可取多數個之基板之步驟。
又，本發明係，具有：第1處理部，其設有可辨識形成於具有複數半導體裝置之形成區域之可取多數個之基板之辨識用標記之照相手段；第2處理部，根據前述第1處理部圖像辨識取得之資訊將前述可取多數個之基板藉由刀片切割；搬送手段，其係將前述可取多數個之基板於前述第1處理部與前述第2處理部間搬送，可同時處理配置於前述第2處理部之第1可取多數個之基板之切割，及配置於前述第1處理部之第2可取多數個之基板之圖像處理。
於以下之實施形態有特別需要時以外以同一或同樣的部分之說明原則上不重複。
再者，於以下之實施形態方便上有其必要時，分割為複數節或實施形態說明，惟除了特別明示之情形，該等並非互相無關係者，一邊係另一邊之一部分或全部之變形例、詳細、補足說明等關係。
又，於以下之實施形態，言及要素之數等(包含個數、數值、量、範圍等)之情形，特別明示之情形及原理上明顯地限定於特定數之情形等之外，並非限定於該特定之數者，亦可為特定之數以上或以下者。
以下，將本發明之實施形態根據圖面詳細地說明。再者，於為說明實施形態之全圖，具有同一功能之零件附以同一符號，省略其反覆說明。
(實施形態1)
圖1為顯示用於本發明之實施形態1之半導體裝置之製造方法之半導體製造裝置(一體機)之構造之一例之平面圖。圖2為顯示於圖1之半導體製造裝置之要部之構造之一例之剖面圖。圖3為顯示於圖1之半導體製造裝置之夾具之構造之一例之剖面圖。圖4為顯示用於本發明之實施形態1之半導體裝置之製造方法之可取多數個之基板之晶片搭載側之面之構造之一例之平面圖。圖5為顯示於圖4之可取多數個之基板之實裝面之構造之一例之平面圖。圖6為顯示於圖4之基板之晶片搭載側之面之元件區域之導體圖案之一例之放大平面圖。圖7為顯示於圖5之基板之實裝面之元件區域之導體圖案之一例之放大平面圖。圖8為顯示於本發明之實施形態1之變形例之可取多數個之基板之晶片搭載側之面之構造之平面圖。圖9為顯示於圖8之可取多數個之基板之實裝面之構造之平面圖。圖10為顯示於本發明之實施形態1之半導體裝置之組裝開始時之基板構造之一例之剖面圖。圖11為顯示於本發明之實施形態1之半導體裝置之組裝之黏晶時之基板構造之一例之剖面圖。圖12為顯示於本發明之實施形態1之半導體裝置之組裝之打線時之基板構造之一例之剖面圖。圖13為顯示於本發明之實施形態1之半導體裝置之組裝之一次成形時之基板構造之一例之剖面圖。圖14為顯示於本發明之實施形態1之半導體裝置之組裝之搭載球時之基板構造之一例之剖面圖。圖15為顯示於本發明之實施形態1之半導體裝置之組裝之清洗球時之基板構造之一例之剖面圖。圖16為顯示於本發明之實施形態1之半導體裝置之組裝之切割時之基板構造之一例之剖面圖。圖17為顯示於本發明之實施形態1之半導體裝置之製造方法之切割所單片化之半導體裝置之構造之一例之立體圖。圖18為顯示於本發明之實施形態1之半導體裝置之製造方法之一體機之各處理之時機之一例之時程圖。圖19為顯示於本發明之實施形態1之切割時之刀片厚與供電用鍍敷配線之位置關係之一例之剖面圖與背面側配線圖，圖20為顯示於本發明之實施形態1之變形例之半導體裝置之構造之剖面圖。
藉由本實施形態1之半導體裝置之製造方法所組裝之半導體裝置係，如圖17所示稱為BGA(Ball Grid Array：球閘陣列)9，其外部連接用電極之複數銲錫凸塊3，於密封基板2之背面2b(參照圖20)上以複數列/複數行構成之矩陣狀排列者，並且於密封基板2之主面2a上搭載半導體晶片1。
又，BGA9為，如圖4所示，利用形成有複數元件區域(半導體元件區域)7a之可取多數個之基板7組裝，於樹脂密封後藉由切割單片化以形成者。
其次，說明用於本實施形態1之半導體裝置之切割裝置(半導體製造裝置)11。
示於圖1之切割裝置11係第1處理部之預對準部11c，與第2對準部之切割部11e成一體之製造裝置，因此，具有可將基板切割位置之圖像處理，與基板之切割一並同時處理之功能。
說明切割裝置11之構造則，係由：供給可取多數個之基板7之供應部11a；對產品進行標識號碼等標記之雷射標記部11b；設有可辨識形成於可取多數個之基板7而為切割之複數之辨識用標記7c(參照圖5)之預對準相機(照相手段)11d之第1處理部之預對準部11c；根據以預對準部11c圖像辨識所取得之資訊將可取多數個之基板7以刀片10切割之第2處理部之切割部11e；，將切割後之產品清洗之清洗部11h；對產品之外觀進行檢查之外觀檢查部11i；將檢查後之產品退出之退出部11j；將可取多數個之基板7於預對準部11c與切割步11e間及其他處理部間搬送之搬送手段之XY基台11k所成。
再者，於切割部11e，設置有對準用之對準相機11g與切割用基台11f。於對準相機11g，可藉由僅辨識數處(例如，2處)，馬上用配置於其附近之刀片10於基台11f上進行切割。
即，如圖2所示，於預對準部11c與先將可取多數個之基板7之所有標記7c藉由圖像處理，藉由該等之相對的位置關係導出切割處。因此，於切割部11e，僅藉由對準相機11g辨識成為基準點之數處，且藉由利用前述預對準部11c所導出之標記7c之相對的位置關係資訊，完成可取多數個之基板7之對準，可以配置於對準相機11g附近之刀片10迅速地進行切割。
又，於本實施形態1之切割裝置11，於將已樹脂密封之可取多數個之基板7進行搬送及各處理之際，使用如圖3所示之專用的夾具12。即，可取多數個之基板7係藉由夾具12保持之狀態由導入部11a供給，其後，經各處理直到再度回到退出部11j以夾具12保持。因此，於切割裝置11內之預對準或切割及搬送等之各處理，以夾具12保持可取多數個之基板7之狀態進行。
夾具12，係為盤狀者，形成有對應於各元件區域7a之複數吸引孔12a。
又，圖3為顯示可取多數個之基板7於切割裝置11內搬送中之狀態者，藉由夾具12保持之可取多數個之基板7，藉由配置於其上方之手部12b經由多孔質構件12c挾持，以該狀態搬送。
再者，於切割部11e進行切割之際，將手部12b及多孔質構件12c脫離，經由夾具12之吸引孔12a由基台11f將一次成形部8吸引，吸著保持於基台11f上。
其次，說明用於本實施形態1之半導體裝置之製造方法之可取多數個之基板7。
圖4、圖5為顯示可取多數個之基板7之構造者，圖4為顯示可取多數個之基板7之晶片搭載側之面，圖5為顯示實裝面(安裝銲錫凸塊3之面)。本實施形態1之可取多數個之基板7係，於基板之表背兩面形成配線層之多層配線基板。
如圖4及圖5所示，於可取多數個之基板7有以矩陣配置形成複數個半導體裝置形成區域之元件區域7a，各個面之各元件區域7a形成有對應於面之導體圖案。
於如圖4所示晶片搭載側之面之各個元件區域7a，形成有如圖6之放大圖所示之供電用導體圖案(供電用鍍敷配線)2j及虛設用導體圖案2k等複數導體圖案，將基板之剛性提高的同時，可圖導體圖案之密度均勻化。
再者，作為導體圖案之密度調整用，形成有複數之導體膜去除區域2i。又，元件區域7a之中央附近形成有開口2f。
再者，於供電用鍍敷配線之供電用導體圖案2j係，對進行電氣信號之傳達之導體圖案施以鍍敷之際採用電解鍍敷之情形成需要者。即，藉由電解鍍敷法對導體圖案進行電解鍍敷之際經由供電用導體圖案2j進行供電施以電解鍍敷。
因此，於供電用導體圖案2j係，跨於各元件區域7a其內側與外側形成，於可取多數個之基板7上，各元件區域7a之複數供電用導體圖案2j於鄰接之元件區域7a之外側之區域作為配線聯繫。
因此，於形成電解鍍敷之供電後，需將於各元件區域7a之外側連接之供電用導體圖案2j切斷，使個別之供電用導體圖案2j呈絕緣之狀態。
於此，於BGA9之組裝，於一次成形後之切割之單片化時，藉由與切割一起將供電用導體圖案2j切斷，如圖6所示，於各元件區域7a殘留之供電用導體圖案2j呈個別絕緣之構造。
又，如圖5所示於實裝面之各個元件區域7a，如圖7之放大圖所示，形成有供電用鍍敷配線之供電用導體圖案2j，虛設用導體圖案2k及凸塊區域2e等複數之導體圖案，與晶片搭載側之面同樣地可提高基板的剛性，並且可圖導體圖案之密度之均勻化。再者，於凸塊區域2e上配置有貫通孔，並且連接有銲錫凸塊3。
如此地於可取多數個之基板7，於複數之配線層(於本實施形態1為晶片搭載面側與實裝面側2層)分別形成有供電用鍍敷配線之供電用導體圖案2j。
又，如圖5所示，於可取多數個之基板7之實裝面，在長邊方向及寬邊方向之各個兩端部形成有於切割之際為對準之辨識用之標記7c。
該標記7c，係以相對之兩端成一對者，將相對之兩端之標記7c以假想線連接則成切割線7b的方式於基板之長邊方向及寬邊方向於各別之兩端部以等間隔附之。即，附於基板之周緣部。惟於可取多數個之基板7未附有切割線7b。
因此，於一次成形後之切割，首先，藉由以切割裝置11之預對準部11c辨識形成於可取多數個之基板7之周緣部之複數標記7c，基於該辨識結果連接相對之一對標記7c，導出刀片10之行進線即切割線7b之相對位置關係。
其後，沿著前述行進線(切割線7b)使刀片10行進切割可取多數個之基板7。
再者，示於圖5之標記7c係為H字型，配置於短邊側之H字成橫向，另一方面，基板之長邊側之H則呈縱向。惟，關於標記7c之形狀，只要是可以圖像辨識可辨識之形狀而並非限定於H字型，可為H字型以外之形狀。
再者，標記7c，以配線之導體圖案形成為佳。即，藉由以導體圖案形成，於形成各配線層之導體圖案之際，可於該形成步驟一起形成，可容易地不多加手續以與導體圖案相同材料形成。
再者，由於與導體圖案以同層形成，各不會對導體圖案產生偏離，可提高供電用導體圖案2j等導體圖案之位置精度形成各標記7c。
又，於本實施形態1之半導體裝置之組裝，藉由於一次成形後之切割將可取多數個之基板7單片化之際，如圖16所示，由於使刀片10由可取多數個之基板7之實裝面(背面2b)側進入，故標記7c至少需形成於可取多數個之基板7之實裝面，如圖4所示，於可取多數個之基板7之晶片搭載側之面可不形成標記7c。
惟，如圖8及圖9之變形例所示，亦可於可取多數個之基板7之搭載側之面與實裝面之兩邊形成標記7c。如圖8所示藉由於可取多數個之基板7之搭載側之面形成標記7c，於圖21所示黏晶機14或打線機15等以標記7c或配線作為圖案辨識用利用之際，可容易地將標記7c由搭載面側照相，可順利地進行標記7c之辨識處理。
又，如圖4、圖5、圖8及圖9所示，於可取多數個之基板7之周緣部形成有定位用之貫通孔7d。
其次，說明於本實施形態1之半導體裝置(BGA9)之製造方法。
再者，本實施形態之BGA9之製造方法係，使用複數之元件區域7a以矩陣配置聯繫形成之可取多數個之基板7，於可取多數個之基板7區隔形成之複數同尺寸之元件區域7a以一次覆蓋之狀態將樹脂成形，其後，藉由切割單片化製造BGA9者。
首先，準備具有：基材2h等樹脂部與導體圖案之配線部2d，並且前述導體圖案之露出部以外之處以絕緣膜之防焊油墨2g覆蓋，且於個別形成複數元件區域7a之基板之如圖10所示複數可取多數個之基板7。
其後，於複數之可取多數個之基板7之元件區域7a進行搭載半導體晶片1之如圖11所示晶片貼裝。
即，配置於主面1b(參照圖20)上具有複數墊1a之半導體晶片1於可取多數個之基板7之各個元件區域7a上，將半導體晶片1之背面1c與於個別之元件區域7a塗布之黏晶材5接合。
接著，進行如圖12所示打線接合。
其時，將半導體晶片1之墊1a，與對應於此之可取多數個之基板7之各密封基板2之連接端子2c(參照圖20)，以金線等線4打線接合將兩者電性連接。
其後，如圖13所示，於樹脂成形模具21之上模具21a與下模具21b進行樹脂密封。
再者，於樹脂成形模具21之上模具21a(下模具21b亦可)，形成有可取多數個之基板7之複數元件區域7a個別搭載之複數之半導體晶片1以一次覆蓋之大的模穴21c。
於此，如圖13所示，於樹脂成形模具21之上模具21a與下模具21b間，將於個別之元件區域7a之搭載半導體晶片1之可取多數個之基板7安裝，以一個模穴21c一次覆蓋複數可取多數個之基板7a後，以上模具21a與下模具21b將可取多數個之基板7夾住。
接著，以此狀態於模穴21c供給密封用樹脂將複數半導體晶片1或線4等一次成形。
再者，作為前述密封用樹脂，使用例如，環氧系之熱硬化樹脂等。
藉此，將複數半導體晶片1以一體覆蓋形成如圖14所示一次形成部8。
其後，如圖14所示，進行銲錫凸塊3之搭載。
於此，於可取多數個之基板7之密封基板2之背面2b側朝向上方，將複數銲錫凸塊3真空吸著保持之球搭載用夾具22配置於其上方，藉此，由可取多數個之基板7之上方於各密封基板2之背面2b上之複數凸塊區域2e上形成銲錫凸塊電極。
此時，將銲錫凸塊3，藉由例如紅外線迴銲等熔融安裝於各凸塊區域2e。
再者，關於銲錫凸塊3之安裝，亦可於一次成形後之切割前進行，或者，亦可於切割後進行。
接著，如圖15所示，進行銲錫凸塊3之清洗。
其後，如圖16所示，利用切割裝置11(參照圖1)之切斷用之刀片10進行切割。
於此，使用刀片10將樹脂密封形成之一次成形部8與可取多數個之基板7，以元件區域7a單位分割單片化。
於切割步驟，由於使用如圖1所示本實施形態1之切割裝置11，如圖18所示導入、雷射標記、預對準(圖像辨識)、切割、清洗及外觀檢查之順序進行處理。
首先，將第1片可取多數個之基板(第1可取多數個之基板)7由導入部11a送至雷射標記部11b做標記處理。處理後，將第1片之可取多數個之基板7搬送至預對準部11c，於此，進行標記7c之圖像辨識，將標記7c之相對位置關係資料化儲存。與此並進，將第2片之可取多數個之基板(第2可取多數個之基板)7由導入部11a送至雷射標記部11b，於此進行標記處理。
於第1處理部之預對準部11c，進行第1片之可取多數個之基板(第1可取多數個之基板)7之圖像辨識。即，將可取多數個之基板7以預對準相機11d由其實裝面照相，辨識形成於基板之實裝面之周緣部之所有標記7c將其相對位置算出作為資料儲存，或者，導出所有刀片10應行進之所有切割線7b將其結果作為資料儲存。
再者，於辨識標記7c時，對複數標記7c之各個，可將各個標記7c之座標做為由特定基準點之距離換算資料化，又，亦可將標記7c間之間隔累積於座標資料換算資料化。
又，以預對準部11c辨識導出之各標記7c之位置之資訊以可迅速地以切割部11e讀取之狀態儲存。
其後，將第1片之可取多數個之基板7由預對準部11c送至第2處理部之切割部11e，於此基於前述導出之各標記7c之位置資訊進行切割。
此時，首先，藉由對準相機11g，將可取多數個之基板7之位置正確地辨識(例如，將2處左右之標記7c以對準相機11g辨識，將可取多數個之基板7之位置正確地把握)，其後，基於各標記7c之位置資訊進行切割。
又，與預對準部11c之切割並進，將第2片之可取多數個之基板7(第2可取多數個之基板)由雷射標記部11b送至預對準部11c，於此進行預對準處理。再者，與該等略同時，將第3片之可取多數個之基板7由導入部11a送至雷射標記部11b，於此進行標記處理。
因此，如圖18所示A部所示，可將第1片之可取多數個之基板(第1可取多數個之基板)7之切割處理，第2片之可取多數個之基板(第2可取多數個之基板)7之預對準處理，及第3片之可取多數個之基板7之標記處理並進進行。
再者，將各個可取多數個之基板7各處理後，依序搬送至下流之處理部各個處理，即，將清洗、外觀檢查依序進行搬送至退出部11j。
再者，於切割部11e，由可取多數個之基板7之實裝面(銲錫凸塊安裝面)側使刀片10進入進行切割。
此時，以預對準部11c辨識之複數之相對之一對標記7c之位置，使刀片10由一邊的標記7c之位置至另一邊之標記7c之位置行進，將此對所有成對標記7c進行，例如，如圖5所示成沿著切割線7b使刀片10行進。
再者，藉由切割將供電用鍍敷配線之供電用導體圖案2j切斷。
即，如圖19所示將形成於可取多數個之基板7之表背兩面之供電用導體圖案2j與切割一起切斷，藉此，如圖6所示，使殘留於各元件區域7a之供電用導體圖案2j呈各個絕緣之構造。
於此，於本實施形態1之切割之刀片10之厚(B)需為可將形成於可取多數個之基板7表背兩面之供電用導體用圖案2j與切割同時切斷之長度。
由以上，藉由使用刀片10之切割將可取多數個之基板7及一次成形部8單片化，如圖17所示形成於密封基板2上形成密封體6之BGA9。
如此地，於本實施形態1之切割，於切割裝置11設有可辨識形成於可取多數個之基板7之辨識用標記7c之預對準相機(照相手段)11d之預對準部(第1處理部)11c；根據以預對準部11c圖像辨識所取得之資訊將可取多數個之基板7以刀片10切割之切割部(第2處理部)11e，由於可將圖像辨識及切割並行處理，故可圖謀於切割步驟之產能提升。
其結果，可圖謀半導體裝置(BGA9)之生產性之提升。
又，將所有標記7c圖像處理藉由將該位置辨識，可提高切段精度，可圖謀切割精度之提升。
其次，說明如圖20所示本實施形態1之變形例之半導體裝置。如圖20所示半導體裝置係，具有積層複數段(例如2段)半導體晶片1之構造之晶片積層型BGA23。
如此之晶片積層型之半導體裝置，由於針數多，可取多數個之基板7之配線層之數亦多4層或5層。當配線層之數增加則，容易發生配線寬幅之分散或配線位置之偏移等，若不提高切割位置精度，則容易引起基板切斷後之配線短路不良。
因此，於本實施形態1之切割，由於可圖謀切割精度之提升，對如圖20所示組入具有多的配線層之密封基板(多層配線基板)2之半導體裝置之組裝亦可防止因切割之短路不良。
(實施形態2)
圖21為顯示用於本發明之實施形態2之半導體裝置之製造方法之半導體製造系統(個別體機)之一例之構成區塊圖，圖22未顯示本發明之實施形態2之變形例之半導體製造系統之構成區塊圖。
本實施形態2並非如實施形態1之切割裝置11具有預對準部11c與切割部11e者，而係說明切割裝置18與圖像辨識裝置13作為個別體具備之半導體製造裝置系統之半導體裝置之製造方法。
示於圖21之半導體製造系統，係由形成於可取多數個之基板7(參照圖5)之辨識用標記7c之圖像辨識裝置13；將圖像辨識裝置13所辨識之資訊(資料)或者，由辨識結果算出之資訊儲存之儲存手段之電腦17；進行黏晶之黏晶機14；進行打線接合之打線機15；進行樹脂成形之數之成形裝置16；及對樹脂成形後之基板進行切割之切割裝置18所成。
即，於本實施形態2之半導體裝置之製造方法，與樹脂密封後之切割步驟分開藉此於上述步驟，將圖像辨識裝置13將可取多數個之基板7之切割處以標記7c等辨識預先辨識，於樹脂密封後之切割步驟，僅進行切割以圖謀於切割步驟之產能提升的同時，藉由圖像辨識裝置13將配線等之打線接合用接合點辨識，可將藉由該辨識之接合點之資訊用於打線接合時之資料，於各步驟可將對準之時間縮短可圖謀半導體裝置之製造步驟之產能提升。
例如，於如圖21所示半導體製造系統，於使用圖像辨識裝置13之基板辨識之際，藉由辨識各配線，進行打線接合用之配線辨識，且藉由辨識標記7c等亦進行切割用之對準位置辨識。
再者，藉由圖像辨識裝置13亦將基板之ID(例如，由條碼所成)辨識，藉由將對應於前述ID之配線或標記7c之資訊儲存於電腦17等儲存手段，可將對應於各個基板之資料容易且迅速之讀取。
其後，利用黏晶機14進行對可取多數個之基板7之晶片搭載。
其後，利用打線接合機15進行打線接合。
此時，首先，辨識可取多數個之基板7之ID，將對應於該ID之打線接合用配線位置資訊(資料)由電腦17取出的同時，將該位置資訊傳送至打線機15。
於打線機15，只要進行成為可取多數個之基板7之基準點之配線之對準，根據由電腦17所傳送之前述位置資訊進行可取多數個之基板7之打線接合。
其後，利用樹脂成形裝置16進行樹脂密封。
於前述樹脂密封後，例用切割裝置18進行以切割之單片化。此時，首先，藉由切割裝置18將可取多數個之基板7之ID辨識，將對應於該ID之為切割之標記7c之位置資訊(資料)由電腦17的同時將該位置資訊傳送至切割裝置18。
於切割裝置18，只要進行成為可取多數個之基板7之基準點之標記7c之對準，根據由電腦17所傳送之前述切割用位置資訊以切割進行可取多數個之基板7之單片化。
因此，藉由以圖像辨識裝置13預先進行將配線或標記7c等之位置辨識，可縮短於打線接合步驟或切割步驟之對準時間，可圖謀於各個步驟之產能提升。
其結果，可圖謀半導體裝置之生產性。
再者，與實施形態1同樣地，將所有標記7c等以圖像辨識裝置13圖像處理將該等之位置辨識，可提高切斷精度，可圖謀切割精度之提升。
再者，於如圖21之半導體製造系統，藉由於可取多數個之基板7形成黏晶用之專用標記，於利用圖像辨識裝置13之位置辨識，亦進行黏晶用之專用標記之位置辨識，亦可利用該位置資訊於黏晶步驟使用黏晶機14進行黏晶。
又，作為儲存以圖像辨識裝置13所辨識之資訊，或者，由辨識結果算出之資訊之儲存手段，不限於電腦17，亦可使用磁碟裝置(F/D)或CD(光碟)-ROM(Read Only Memory：唯讀記憶體)裝置等，於此情形，將寫入有以圖像辨識裝置13辨識之資訊，或者，由辨識結果算出之資訊之F/D或CD-ROM以打線接合機15或切割裝置18等搬送至特定半導體製造裝置，於前述半導體製造裝置由F/D或CD-ROM取出所需資料進行所望處理。
再者，黏晶用之位置辨識之專用標記，需附於可取多數個之基板7之晶片搭載側之面，於此情形，如圖8、圖9所示於可取多數個之基板7之表背兩面，例如將位置辨識用之標記7c，於圖像辨識裝置13，將可取多數個之基板7之表背面之中任一方之面之標記7c全部變事後，亦可將基板之正反面反轉，其後，將另一面之標記7c全部辨識以辨識表背兩側之所有標記7c，又，亦可於可取多數個之基板7之表背兩側配置預對準相機11d(參照圖1)，利用兩側之預對準相機11d將可取多數個之基板7之表背兩面之標記7c。
又，於本實施形態2之半導體裝置之製造方法，亦可於半導體製造系統之外部預先進行可取多數個之基板7之切割用之位置辨識之標記7c之位置辨識，藉此，將可取多數個之基板7與其切割用之標記7c之位置情報(資訊)送入(準備)，進行黏晶、打線接合、樹脂成形及切割等各處理組裝半導體裝置。
其次，說明如圖22所示本實施形態2之變形例之半導體製造裝置，於如圖21所示半導體製造系統圖像辨識裝置13之處理能力較切割裝置18遠高之情形(例如高三倍左右之情形)，如圖22所示，藉由對1台圖像辨識裝置13連接3台切割裝置18，可進行圖像辨識處理與切割處理之TAT(Turn Around Time：作業完成時間)之合併，可提升切割步驟之產能之同時，亦可充分將圖像辨識裝置13之能力發揮。
以上，將由本發明者所做發明基於本發明之實施形態具體地說明，惟本發明並非限定於前述發明之實施形態者，以不脫逸該要旨之範圍可有種種變更未言即是。
例如，於前述實施形態1，以樹脂密封為一次成形之情形說明，惟於本發明之半導體裝置之製造方法，亦可以採用將各個元件區域7a以樹脂成形模具21之1個模穴21c覆蓋注入之密封用樹脂之個別成形之製造方法。
又，於前述實施形態1，以半導體晶片1與可取多數個之基板7之電性連接為線連接之情形說明，惟不限於前述配線，亦可為覆晶片連接等。
再者，於前述實施形態1，說明半導體裝置為BGA9或者晶片積層型BGA23之情形，惟前述半導體裝置，只要是利用可取多數個之基板7組裝，且於樹脂密封後之單片化以切割進行者，亦可為LGA(Land Grid Array：基板柵格陣列)等其他半導體裝置。
發明之效果
於本案所揭示之發明之中，由代表性者所得之效果簡單地說明如下。
藉由具有：設有可辨識形成於具有複數半導體裝置之形成區域之可取多數個之基板之辨識用標記之照相手段之第1處理部；及根據前述第1處理部圖像辨識取得之資訊將前述可取多數個之基板藉由刀片切割之第2處理部；可將對準與切割並進處理，可圖謀於半導體裝置之組裝切割步驟之產能提升。
1．．．半導體晶片
1a．．．墊
1b．．．主面
1c．．．背面
2．．．密封基板
2a．．．主面
2b．．．背面
2c．．．連接端子
2d．．．配線部
2e．．．凸塊區域
2f．．．開口
2g．．．防焊油墨
2h．．．基材
2i．．．導體膜去除區域
2j．．．供電用導體圖案(供電用鍍敷配線)
2k．．．虛設用導體圖案
3．．．銲錫凸塊
4．．．線
5．．．黏晶材
6．．．密封體
7．．．可取多數個之基板
7a．．．元件區域(半導體裝置形成區域)
7b．．．切割線
7c．．．標記
7d．．．貫通孔
8．．．一次成形部
9．．．BGA(半導體裝置)
10．．．刀片
11．．．切割裝置(半導體製造裝置)
11a．．．導入部
11b．．．雷射標記部
11c．．．預對準部(第1處理部)
11d．．．預對準相機(照相手段)
11e．．．切割部(第2處理部)
11f．．．基台
11g．．．對準相機
11h．．．清洗部
11i．．．外觀檢查部
11j．．．退出部
11k．．．XY基台(搬送手段)
12．．．夾具
12a．．．吸引孔
12b．．．手部
12c．．．多孔質構件
13．．．圖像辨識裝置
14．．．黏晶機
15．．．打線接合機
16．．．樹脂成形裝置
17．．．電腦(儲存手段)
18．．．切割裝置
21．．．樹脂成形模具
21a．．．上模具
21b．．．下模具
21c．．．模穴
22．．．球搭載用夾具
23．．．晶片基層形BGA(半導體裝置)
圖1為顯示用於本發明之實施形態1之半導體裝置之製造方法之半導體製造裝置(一體機)之構造之一例之平面圖。
圖2為顯示於圖1所示之半導體製造裝置之要部之構造之一例之剖面圖。
圖3為顯示於圖1所示之半導體製造裝置之夾具之構造之一例之剖面圖。
圖4為顯示用於本發明之實施形態1之半導體裝置之製造方法之可取多數個之基板之晶片搭載側之面之構造之一例之平面圖。
圖5為顯示於圖4所示之可取多數個之基板之實裝面之構造之一例之平面圖。
圖6為顯示於圖4所示之基板之晶片搭載側之面之元件區域之導體圖案之一之放大平面圖。
圖7為顯示於例圖5所示之基板之實裝面之元件區域之導體圖案之一例之放大平面圖。
圖8為顯示於本發明之實施形態1之變形例之可取多數個之基板之晶片搭載側之面之構造之平面圖。
圖9為顯示於圖8所示之可取多數個之基板之實裝面之構造之平面圖。
圖10為顯示於本發明之實施形態1之半導體裝置之組裝開始時之基板構造之一例之剖面圖。
圖11為顯示於本發明之實施形態1之半導體裝置之組裝之黏晶時之基板構造之一例之剖面圖。
圖12為顯示於本發明之實施形態1之半導體裝置之組裝之打線時之基板構造之一例之剖面圖。
圖13為顯示於本發明之實施形態1之半導體裝置之組裝之一次成形時之基板構造之一例之剖面圖。
圖14為顯示於本發明之實施形態1之半導體裝置之組裝之搭載球時之基板構造之一例之剖面圖。
圖15為顯示於本發明之實施形態1之半導體裝置之組裝之清洗球時之基板構造之一例之剖面圖。
圖16為顯示於本發明之實施形態1之半導體裝置之組裝之切割時之基板構造之一例之剖面圖。
圖17為顯示於本發明之實施形態1之半導體裝置之製造方法之切割所單片化之半導體裝置之構造之一例之立體圖。
圖18為顯示於本發明之實施形態1之半導體裝置之製造方法之一體機之各處理之時機之一例之時程圖。
圖19為顯示於本發明之實施形態1之切割時之刀片厚與供電用鍍敷配線之位置關係之一例之剖面圖與背面側配線圖。
圖20為顯示於本發明之實施形態1之變形例之半導體裝置之構造之剖面圖。
圖21為顯示用於本發明之實施形態2之半導體裝置之製造方法之半導體製造系統(個別體機)之一例之構成區塊圖。
圖22為顯示於本發明之實施形態2之變形例之半導體製造系統之構成區塊圖。
7．．．基板
10．．．刀片
11．．．切割裝置(半導體製造裝置)
11a．．．導入部
11b．．．雷射標記部
11c．．．預對準部(第1處理部)
11d．．．預對準相機(照相手段)
11e．．．切割部(第2處理部)
11f．．．基台
11g．．．對準相機
11h．．．清洗部
11i．．．外觀檢查部
11j．．．退出部
11k．．．XY基台(搬送手段)

Claims (8)

  1. 一種半導體裝置之製造方法，其特徵在於：該半導體裝置係利用具有複數半導體裝置形成區域之可取多數個之基板所組裝者，其製造方法具有下列步驟：(a)準備複數可取多數個之基板；(b)分別於前述複數可取多數個之基板上搭載複數半導體晶片；(c)將已搭載在各前述複數可取多數個之基板之前述複數半導體晶片進行樹脂密封；(d)將前述複數可取多數個之基板中之第1可取多數個之基板置於第1處理部內；(e)使用前述第1處理部內之預對準相機，對前述第1可取多數個之基板進行圖像辨識；(f)將前述第1可取多數個之基板從前述第1處理部移載至第2處理部之基台，並將前述複數可取多數個之基板中之第2可取多數個之基板置於前述第1處理部內；以及(g)在前述第2處理部內將前述第1可取多數個之基板切割成個別半導體裝置，並同時在前述第1處理部內對前述第2可取多數個之基板進行圖像辨識；其中，各前述複數可取多數個之基板係包含：周緣部、於平視圖中以矩陣配置之形式設於前述周緣部內側之複數元件領域、前述複數元件領域中設於相鄰元件領域間之切割線、以及形成於前述周緣部之與前述切割線重疊之假想 線上的複數標記；於前述第1處理部內，藉由使用前述預對準相機，辨識形成於各前述複數可取多數個之基板之用於辨識前述切割線之前述複數標記，而獲得第1情報；於前述第2處理部內，藉由使用前述第2處理部之對準相機，辨識於前述第1處理部內已辨識之前述複數標記中之數處，而獲得成為對位之基準之第2情報；藉由利用前述第1情報與前述第2情報，將前述複數可取多數個之基板切割成個別半導體裝置；使用前述對準相機辨識之前述標記之數量，係少於使用前述預對準相機辨識之前述標記之數量。
  2. 如申請專利範圍第1項之半導體裝置之製造方法，其中各前述複數可取多數個之基板係具有複數配線層之多層配線基板。
  3. 如申請專利範圍第1項之半導體裝置之製造方法，其中於各前述複數可取多數個之基板形成有供電用鍍敷配線，藉由切割將前述供電用鍍敷配線切斷。
  4. 如申請專利範圍第1項之半導體裝置之製造方法，其中於前述圖像辨識時所辨識之前述複數標記係由導體圖案所形成。
  5. 如申請專利範圍第1項之半導體裝置之製造方法，其中各前述複數可取多數個之基板係具有複數配線層之多層配線基板，於各前述複數配線層形成有供電用鍍敷配線。
  6. 如申請專利範圍第1項之半導體之製造方法，其中於前述 第2處理部內，辨識前述複數標記中之2處。
  7. 如申請專利範圍第1項之半導體裝置之製造方法，其進一步包含前述複數可取多數個之基板之第3可取多數個之基板之標記處理，前述第3可取多數個之基板之前述標記處理，係與在前述第2處理部內切割前述第1可取多數個之基板、以及在前述第1處理部內對前述第2可取多數個之基板進行前述圖像辨識同時進行。
  8. 如申請專利範圍第1項之半導體裝置之製造方法，其中所製造的前述半導體裝置係一球閘陣列裝置。
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