FR2799306B1 - Procede d'isolation de puce de circuit integre par depot de matiere sur la face active - Google Patents

Procede d'isolation de puce de circuit integre par depot de matiere sur la face active

Info

Publication number
FR2799306B1
FR2799306B1 FR9912651A FR9912651A FR2799306B1 FR 2799306 B1 FR2799306 B1 FR 2799306B1 FR 9912651 A FR9912651 A FR 9912651A FR 9912651 A FR9912651 A FR 9912651A FR 2799306 B1 FR2799306 B1 FR 2799306B1
Authority
FR
France
Prior art keywords
integrated circuit
insulating
circuit chip
active face
depositing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9912651A
Other languages
English (en)
Other versions
FR2799306A1 (fr
Inventor
Philippe Patrice
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Priority to FR9912651A priority Critical patent/FR2799306B1/fr
Priority to PCT/FR2000/002751 priority patent/WO2001026151A1/fr
Priority to AU76725/00A priority patent/AU7672500A/en
Publication of FR2799306A1 publication Critical patent/FR2799306A1/fr
Application granted granted Critical
Publication of FR2799306B1 publication Critical patent/FR2799306B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/76151—Means for direct writing
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    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L2924/14—Integrated circuits
FR9912651A 1999-10-04 1999-10-04 Procede d'isolation de puce de circuit integre par depot de matiere sur la face active Expired - Fee Related FR2799306B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR9912651A FR2799306B1 (fr) 1999-10-04 1999-10-04 Procede d'isolation de puce de circuit integre par depot de matiere sur la face active
PCT/FR2000/002751 WO2001026151A1 (fr) 1999-10-04 2000-10-04 Procede d'isolation de puce de circuit integre par depot de matiere sur la face active
AU76725/00A AU7672500A (en) 1999-10-04 2000-10-04 Method for insulating an integrated circuit chip by substance deposit on the active surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9912651A FR2799306B1 (fr) 1999-10-04 1999-10-04 Procede d'isolation de puce de circuit integre par depot de matiere sur la face active

Publications (2)

Publication Number Publication Date
FR2799306A1 FR2799306A1 (fr) 2001-04-06
FR2799306B1 true FR2799306B1 (fr) 2003-09-19

Family

ID=9550784

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9912651A Expired - Fee Related FR2799306B1 (fr) 1999-10-04 1999-10-04 Procede d'isolation de puce de circuit integre par depot de matiere sur la face active

Country Status (3)

Country Link
AU (1) AU7672500A (fr)
FR (1) FR2799306B1 (fr)
WO (1) WO2001026151A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101882A (zh) * 2006-07-05 2008-01-09 阎跃军 基板树脂封装方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1211354A (en) * 1966-12-01 1970-11-04 Gen Electric Improvements relating to passivated semiconductor devices
DE2348323A1 (de) * 1973-09-26 1975-04-03 Licentia Gmbh Integrierte festkoerperschaltung mit einer vielzahl von bauelementen in einem gemeinsamen halbleiterkoerper
GB2120861B (en) * 1982-05-27 1985-10-02 Vladimir Iosifovich Livshits Process for manufacturing panels to be used in microelectronic systems
JP2980495B2 (ja) * 1993-09-07 1999-11-22 株式会社東芝 半導体装置の製造方法
JP2581017B2 (ja) * 1994-09-30 1997-02-12 日本電気株式会社 半導体装置及びその製造方法
FR2740935B1 (fr) * 1995-11-03 1997-12-05 Schlumberger Ind Sa Procede de fabrication d'un ensemble de modules electroniques pour cartes a memoire electronique
FR2761498B1 (fr) * 1997-03-27 1999-06-18 Gemplus Card Int Module electronique et son procede de fabrication et carte a puce comportant un tel module
FR2761497B1 (fr) * 1997-03-27 1999-06-18 Gemplus Card Int Procede de fabrication d'une carte a puce ou analogue
DE19845296A1 (de) * 1998-09-03 2000-03-16 Fraunhofer Ges Forschung Verfahren zur Kontaktierung eines Schaltungschips

Also Published As

Publication number Publication date
WO2001026151A1 (fr) 2001-04-12
AU7672500A (en) 2001-05-10
FR2799306A1 (fr) 2001-04-06

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