AU6001599A - Semiconductor device and method of manufacture thereof - Google Patents

Semiconductor device and method of manufacture thereof

Info

Publication number
AU6001599A
AU6001599A AU60015/99A AU6001599A AU6001599A AU 6001599 A AU6001599 A AU 6001599A AU 60015/99 A AU60015/99 A AU 60015/99A AU 6001599 A AU6001599 A AU 6001599A AU 6001599 A AU6001599 A AU 6001599A
Authority
AU
Australia
Prior art keywords
manufacture
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU60015/99A
Inventor
Katsuo Arai
Shinya Koike
Ichio Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of AU6001599A publication Critical patent/AU6001599A/en
Abandoned legal-status Critical Current

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    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
AU60015/99A 1999-10-01 1999-10-01 Semiconductor device and method of manufacture thereof Abandoned AU6001599A (en)

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JP2004179345A (en) * 2002-11-26 2004-06-24 Fujitsu Ltd Substrate sheet material for semiconductor and manufacturing method therefor, and molding method using the substrate sheet material and method for manufacturing semiconductor device
DE10333841B4 (en) * 2003-07-24 2007-05-10 Infineon Technologies Ag A method of producing a benefit having semiconductor device locations arranged in rows and columns and methods of making a semiconductor device
JP2007234881A (en) * 2006-03-01 2007-09-13 Oki Electric Ind Co Ltd Semiconductor device laminating semiconductor chips, and its manufacturing method
CN101101882A (en) * 2006-07-05 2008-01-09 阎跃军 Substrate resin packaging method
CN100411124C (en) * 2006-08-01 2008-08-13 上海凯虹电子有限公司 CSP packaging technique
CN112103210B (en) * 2020-08-13 2023-03-31 上饶市广丰时代科技有限公司 Chip bonding process equipment for semiconductor chip packaging

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JP3621182B2 (en) * 1996-02-23 2005-02-16 株式会社シチズン電子 Manufacturing method of chip size package
JP3137322B2 (en) * 1996-07-12 2001-02-19 富士通株式会社 Semiconductor device manufacturing method, semiconductor device manufacturing mold, and semiconductor device

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