FR2704690B1 - A method of encapsulating semiconductor chips, device obtained by this method and application to the interconnection of pellets in three dimensions. - Google Patents

A method of encapsulating semiconductor chips, device obtained by this method and application to the interconnection of pellets in three dimensions.

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Publication number
FR2704690B1
FR2704690B1 FR9304962A FR9304962A FR2704690B1 FR 2704690 B1 FR2704690 B1 FR 2704690B1 FR 9304962 A FR9304962 A FR 9304962A FR 9304962 A FR9304962 A FR 9304962A FR 2704690 B1 FR2704690 B1 FR 2704690B1
Authority
FR
France
Prior art keywords
method
chips
pellets
interconnection
dimensions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9304962A
Other languages
French (fr)
Other versions
FR2704690A1 (en
Inventor
Val Christian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thales SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales SA filed Critical Thales SA
Priority to FR9304962A priority Critical patent/FR2704690B1/en
Publication of FR2704690A1 publication Critical patent/FR2704690A1/en
Application granted granted Critical
Publication of FR2704690B1 publication Critical patent/FR2704690B1/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
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    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02333Structure of the redistribution layers being a bump
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02371Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
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    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06524Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06551Conductive connections on the side of the device
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    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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Abstract

According to the method of the invention, conductive leads are directly wired onto a semiconductor wafer carrying a large number of chips, the wafer is bonded to a resilient film and cut to separate each chip, after which the film is stretched to space the chips; the totality of the chips and leads are then held in an insulating material such as a polymerizable resin, and, after polishing, metal plating is applied over the leads to connect them to the sides of the chips; the assembly is then cut in order to separate the chips.
FR9304962A 1993-04-27 1993-04-27 A method of encapsulating semiconductor chips, device obtained by this method and application to the interconnection of pellets in three dimensions. Expired - Fee Related FR2704690B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9304962A FR2704690B1 (en) 1993-04-27 1993-04-27 A method of encapsulating semiconductor chips, device obtained by this method and application to the interconnection of pellets in three dimensions.

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR9304962A FR2704690B1 (en) 1993-04-27 1993-04-27 A method of encapsulating semiconductor chips, device obtained by this method and application to the interconnection of pellets in three dimensions.
JP6523941A JPH07509104A (en) 1993-04-27 1994-04-15
EP94913654A EP0647357A1 (en) 1993-04-27 1994-04-15 Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection
PCT/FR1994/000427 WO1994025987A1 (en) 1993-04-27 1994-04-15 Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection

Publications (2)

Publication Number Publication Date
FR2704690A1 FR2704690A1 (en) 1994-11-04
FR2704690B1 true FR2704690B1 (en) 1995-06-23

Family

ID=9446488

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9304962A Expired - Fee Related FR2704690B1 (en) 1993-04-27 1993-04-27 A method of encapsulating semiconductor chips, device obtained by this method and application to the interconnection of pellets in three dimensions.

Country Status (4)

Country Link
EP (1) EP0647357A1 (en)
JP (1) JPH07509104A (en)
FR (1) FR2704690B1 (en)
WO (1) WO1994025987A1 (en)

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US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7943952B2 (en) 2006-07-31 2011-05-17 Cree, Inc. Method of uniform phosphor chip coating and LED package fabricated using method
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8167674B2 (en) 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
US8337071B2 (en) 2005-12-21 2012-12-25 Cree, Inc. Lighting device
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US9093616B2 (en) 2003-09-18 2015-07-28 Cree, Inc. Molded chip fabrication method and apparatus
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9166126B2 (en) 2011-01-31 2015-10-20 Cree, Inc. Conformally coated light emitting devices and methods for providing the same

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JP4422380B2 (en) * 1999-10-01 2010-02-24 株式会社ルネサステクノロジ A method of manufacturing a semiconductor device
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AT311604T (en) * 2000-06-20 2005-12-15 Nanonexus Inc Test system of integrated circuits
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
DE10137184B4 (en) * 2001-07-31 2007-09-06 Infineon Technologies Ag A method for manufacturing an electronic component having an electronic component and Kuststoffgehäuse
DE10149689A1 (en) 2001-10-09 2003-04-10 Philips Corp Intellectual Pty Electrical/electronic component has lateral, rear cover materials at least partly of electrically conductive material and/or of electrically conductive material in layers but in connected manner
JP4688679B2 (en) * 2003-09-09 2011-05-25 三洋電機株式会社 Semiconductor module
US20050104027A1 (en) * 2003-10-17 2005-05-19 Lazarev Pavel I. Three-dimensional integrated circuit with integrated heat sinks
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7217583B2 (en) 2004-09-21 2007-05-15 Cree, Inc. Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US10295147B2 (en) 2006-11-09 2019-05-21 Cree, Inc. LED array and method for fabricating same
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8723332B2 (en) 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
WO2009017758A2 (en) * 2007-07-27 2009-02-05 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
EP2186131A2 (en) 2007-08-03 2010-05-19 Tessera Technologies Hungary Kft. Stack packages using reconstituted wafers
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
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FR2704690A1 (en) 1994-11-04
WO1994025987A1 (en) 1994-11-10

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