WO1994025987A1 - Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection - Google Patents

Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection Download PDF

Info

Publication number
WO1994025987A1
WO1994025987A1 PCT/FR1994/000427 FR9400427W WO9425987A1 WO 1994025987 A1 WO1994025987 A1 WO 1994025987A1 FR 9400427 W FR9400427 W FR 9400427W WO 9425987 A1 WO9425987 A1 WO 9425987A1
Authority
WO
WIPO (PCT)
Prior art keywords
pellets
characterized
conductors
material
stack
Prior art date
Application number
PCT/FR1994/000427
Other languages
French (fr)
Inventor
Christian Val
Original Assignee
Thomson-Csf
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR93/04962 priority Critical
Priority to FR9304962A priority patent/FR2704690B1/en
Application filed by Thomson-Csf filed Critical Thomson-Csf
Publication of WO1994025987A1 publication Critical patent/WO1994025987A1/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02333Structure of the redistribution layers being a bump
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02371Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06524Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06551Conductive connections on the side of the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06589Thermal management, e.g. cooling
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

According to the method of the invention, conductive leads are directly wired onto a semiconductor wafer carrying a large number of chips, the wafer is bonded to a resilient film and cut to separate each chip, after which the film is stretched to space the chips; the totality of the chips and leads are then held in an insulating material such as a polymerizable resin, and, after polishing, metal plating is applied over the leads to connect them to the sides of the chips; the assembly is then cut in order to separate the chips.

Description

METHOD FOR PACKAGING OF TABLETS SEMICONDUCTOR DEVICE OBTAINED BY THE METHOD AND APPLICATION TO CONNECTING TABLETS IN THREE DIMENSIONS

The present invention relates to a method for encapsulating semiconductor chips as well as the resulting device, each pellet containing such an electronic component, an integrated circuit or a sensor. It also relates to the application of such encapsulation interconnection in three dimensions of these pellets.

The achievement of current electronic systems, both civilian and military, must take into consideration requirements of ever greater compactness, since the number of increasingly higher circuits implemented.

In this sense, it has already been proposed to produce integrated circuit stacks called "three dimensions" such as described in French patent application No. 2670323 in the name of Thomson-CSF. In this embodiment, the pellets are stacked after having been provided with connection son oriented side faces of the stack, and are then made integral with each other, using for example a resin; interconnections pellets are then performed on the faces of the stack.

The present invention aims to change this process in particular to make it more easily integrated realization in a semiconductor factory and reduce the cost.

More specifically, according to the method of the invention, cable drivers, son for example, directly on a semiconductor washer carrying a large number of pellets; the washer being bonded to an elastic film, the washer is sawn to individualize the pellets and then the film was stretched so as to separate the pellets; then secures all pellets and son in an insulating material, polymerizable resin, for example, then, after polishing, is carried out of metal deposits over the son so as to connect them to the sides of the pellets; then cutting the assembly so as to separate the pellets: are then obtained pellets encapsulated in a coating forming a casing, provided with connections. For application "three-dimensional", we proceed to the stack of the previous cases, the latter being simply glued together with a spacer disposed between each wafer and the next, then the interconnects are formed on the faces side of the stack thus obtained, e.g. as described in the aforementioned patent application.

Other objects, features and results of the invention will become apparent from the following description, given by way of example and illustrated by the accompanying drawings, which show:

- Figure 1 a process embodiment of the invention;

- Figures 2 to 4a and 5, the different patterns seen in section, illustrating different steps of the method according to the invention;

- Figure 4b, a view of the diagram of Figure 4a; - Figures 6 and 7 are diagrammatic sectional views of variants of the invention.

On these figures, the same references refer to the same elements. Moreover, the clarity of the drawings, the real scale has not been respected.

Figure 1 represents one embodiment of the method according to the invention.

The first step, referenced 10, is to attach (e.g., adhere) on an elastic film, a semiconductor material washer (also known under the English name of "wafer"), wherein a large number was carried out in pellets (commonly of the order of several hundreds), each containing an integrated circuit or discrete component; the film is for example a polymer-type self-adhesive. The second step, referenced 11, is to wire electrical conductors, son or ribbons, each of the bonding pads of each of the pellets contained in the washer.

The result of these operations is illustrated in Figure 2. In the latter figure, there is shown a semiconductor washer 1 wherein a pellet was identified 21. The washer 1 is mounted on the elastic film 2. On each spotted pads, referenced 22, of the washer 1 are connected to conductors 23, e.g. son. These may be connected vertically by means of the technique known as "bail bonding" and of melting the end of the wire 23 for a small ball 24, facilitating its connection to the pad 22. Other techniques may be employed, as illustrated by example below in Figure 7. after fixation, the son 23 are each cut at a predetermined height, which can be for example 150 to 200 microns, for a wire diameter of approximately 25-30 .mu.m, a washer thickness of about 500 microns and film 2 of about 200 microns, for example.

The next step (12, Figure 1) is to saw the washer 2 preferably over its entire thickness, so as to individualize the pellets such as 21.

The next step, referenced 13, is to uniformly stretch the elastic film (2); this has the effect to spread the pellets (21) from each other and that a regular basis. It should be noted that step 11 of wiring son on the washer (1) may be, in an alternative embodiment, only performed after this step 13 stretching of the elastic film (2).

The next step, referenced 14, is to bond the pellets and their connecting son and coat all in an electrically insulating material, for example an organic resin, epoxy or polyimide, by a technique of casting or molding for example, material then being, if necessary, polymerized.

The result of this step is illustrated in Figure 3. In this figure, there is the film 2 on the pellets 21, now individualized and separated from each other. The pellets 21 and their conductors 23 are embedded in an insulating material 25 which also penetrates into the gaps 26 between pellets.

The next step, referenced 15, is to polish the upper surface (27, Figure 3) of the coating material 25 so as to obtain a flat surface on which the sections 23 are flush son.

The thickness of the coating material 25 depends on that of the washer 1 and the materials involved, in particular for thermo-mechanical reasons. For example, for a washer 400 to 500 .mu.m in thickness, the material 25 may be about 150 microns.

The next step (16, Figure 1) is to remove the elastic film 2.

This suppression can be achieved for example by taking off the film. In an alternative embodiment, the procedure for polishing the rear face of the assembly, marked 28 in Figure 3, that is to say the face opposite to the face 27 to remove the film 2 and / or thin the pellets 21 in order to reduce its thickness and size, which can be particularly advantageous in the application described hereinafter stacking encapsulated pellets in three dimensions.

In an alternative embodiment, it does not remove the elastic film 2, which then makes it possible to isolate and / or to protect the rear face 28 of the pellet.

The next step, referenced 17, is to make connections between each of the conductors 23 in what will become the side face of the pellets after separation, these connections being formed by metallizations on the top side 27 above the inter-pellet gap .

Figures 4a and 4b illustrate this step, seen respectively in section and from above.

4a represents the pellets 21 with their son 23 embedded in the material 25. The upper face 27 of the door assembly of the metallizations 30 above the son 23, metallizations that connect each of the son 23 in the gap 26 between pellets .

These metallizations can affect various forms as illustrated in the top view of Figure 4b may connect a wire 23 to the inter-chip area 26, connect together two son 23 different pellets or connect further includes a wire 23 to an area 31, subsequently used for testing the pellets, for example.

Making connections 30 may be made by any known means, for example, depositing a metal layer and subsequent etching of this layer. The deposition can be a metal coating such as gold, nickel and gold, nickel and copper-gold, copper and gold, made for example by vacuum sputtering, possibly reloaded electrochemically.

Subsequent etching may be for example a photogravure. Alternatively, a so-called reverse photoengraving may be used, that is to say leaving the metal everywhere except around the conductors, the latter for achieving further electromagnetic shielding.

The last step of the embodiment of the encapsulated pellets (step 18 in Figure 1) consists in the separation of the pellets. This separation is achieved by cutting the material 25 between the pellets, for example using a diamond saw. Are then obtained semiconductor chips each coated on five of their faces in an insulating material forming the housing, this latter being provided with connections (metallizations 30) testable and manipulated.

When one wants to achieve with pellets and encapsulated a stack in three dimensions (step 19, Figure 1), there is recessed in a guide for aligning two of the side faces of the housings, thereby simplifying positioning problems relative housings . Between the housings are arranged adhesive layers, such as a polymerizable resin, for example. then press the assembly and optionally the polyméhse, so that the interlock.

This is illustrated in Figure 5 where we find the pellets 21 and potting material 25, separated from each other by an adhesive layer 32. In an alternative embodiment, is used for the elastic film 2, an adhesive material -or tackified by a approprié- treatment that leaves in place, thus avoiding the interposition of the layers 32. in each of the end faces of the stack, there is further a sealing layer 42 non-adhesive, which is attached via a layer 32. in an alternative embodiment (not shown), the cover layers 42 may be adhesive on one of their faces, thus preventing layer 32. the metallizations 30 connect each of the conductors 23 to the wafer 35 of the stack.

The next step (20, Figure 1) is to interconnect together the various wafers of the stack and to connect, if necessary, to pads, called stack pads, allowing their connection to external circuits. These interconnections are formed on the faces of the stack, for example as described in the abovementioned French patent application. In Figure 5, by way of example there is shown the different connections 30 all interconnected with a metallization 33 arranged on the side of the stack and extending (34) for example on one or both end faces of the stack. In the latter case, one of the faces can be used to test while the other is used for mounting the stack on a printed circuit, for example.

In another alternative embodiment (not shown) can be realized at the same time several stacks, these possibly being separated from each other further by a non-adhesive tab. The interconnections of the pellets by the side faces of the stack can then be performed in a collective manner simultaneously for all the stacks.

In another embodiment, one can improve the cooling of the pellets in operation by inserting heat sinks between the housings, possibly connected to a radiator.

In the example shown in Figure 6, include lozenges

21, their conductors 23 and the coating material 25. The connections 30 connecting the son 23 to one of the side faces of the wafer are directed so as to disengage one of the faces, for example the left side on the Fig. A heat sink 38, metallic layer, for example, copper or aluminum nitride, or diamond, is disposed between each wafer 21 via an adhesive layer 36. The left side face of the stack is for example glued, by means of an adhesive layer 39, thermally conductive preferably, a radiator 37, which is thus in thermal contact with the drains 38. for clarity of the diagram, the adhesive layers 36 n have not been shaded although section views.

7 shows, in sectional view, an alternative embodiment of step 11 of Figure 1, namely the wiring conductors on the washer.

In this figure, there is the washer 1 mounted on the elastic film 2 and bearing pads 22, on which it is desired wire conductor 23. In this variant, we equip the upper face of the washer 1 circuit type substrate pieces printed 39, preferably at least one per chip, the circuit board 39 being attached to the washer using for example an adhesive layer 40. the printed circuit 39 carries at least one metallization 41. in this variant, the conductor 23 is not cut but it is curved so as to be connected again to the metallization 41 carried by the printed circuit 39. Furthermore, the conductor 23 can be connected vertically to the pad 22 as shown in the previous figures or well as shown in Figure 7, connected horizontally as in metallization 41.

All subsequent operations of the process according to the invention are conducted in the same manner, the conductor 23 being cut during polishing of the coating material (step 15) so as to be flush as above on the upper face of the pellet.

The method described above and the obtained devices have a number of advantages including the fact that it is possible to treat a large number of wafers simultaneously (all those which belong to the same washer), and this with techniques known in the semiconductor industry, easily integrated into a production line of semiconductor circuits, which dramatically reduces the cost of the encapsulated pellet and which, by the techniques used to obtain very reduced dimensions, particularly by the coating material, which can typically represent an increase in the area (of the wafer) of less than 1%. In addition, the encapsulation mode is well suited to a stack "three dimensional", and collectively achieved simply with cost advantages that result.

Claims

1. A method of encapsulation of semiconductor chips, characterized in that it comprises the following steps: - wiring conductors (23) on the connection pads (22) of the pellets (21), the latter being contained in one washer (1) of semiconductor material;
- cutting the washer to individualize the pellets, the washer being fixed to an elastic film (2); - stretching the elastic film so as to separate the pellets;
- coupling and conductive coating and pellets with a material (25) electrically insulating;
- polishing of the coating material so as to be flush with the conductors; - realization of the coating material connections (30) connecting the conductors to the sides of the pellets;
- separation of the pellets.
2. Method according to claim 1, characterized in that the coating material (25) is a polymerizable resin.
3. Method according to one of the preceding claims, characterized in that it further comprises, after the polishing step, a step of removal of the elastic film (2).
4. semiconductor chip (21) having connection pads (22), characterized in that it comprises conductors (23) connected on its pads, the chip and its leads are coated with an insulating material ( 25), such that the conductors are flush with the surface (27) of insulating material, and it further comprises on the latter surface of the electrical connections (30) connecting the conductors to the sides of the pellet.
5. A tablet according to claim 4, characterized in that each of the conductors (23) is formed by a wire or a ribbon.
6. A method of interconnecting pellets obtained by the process according to claim 1, characterized in that it further comprises the steps of: - stacking the separated pellets and securing the stack;
- realization of the interconnection of the connections of the pellets on the faces of the stack.
7. A method according to claim 6, characterized in that the stack of separate pellets is achieved by arranging between the pellets a layer of the material capable of adhering to one another.
8. A device comprising pellets according to claim 4, characterized in that the pellets (21) are stacked and separated by a layer (2, 32) of a material ensuring their mutual adhesion and further comprising interconnections (33) carried by the faces of the stack, interconnecting the connections (30) of the pellets.
PCT/FR1994/000427 1993-04-27 1994-04-15 Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection WO1994025987A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR93/04962 1993-04-27
FR9304962A FR2704690B1 (en) 1993-04-27 1993-04-27 A method of encapsulating semiconductor chips, device obtained by this method and application to the interconnection of pellets in three dimensions.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6523941A JPH07509104A (en) 1993-04-27 1994-04-15
EP94913654A EP0647357A1 (en) 1993-04-27 1994-04-15 Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection

Publications (1)

Publication Number Publication Date
WO1994025987A1 true WO1994025987A1 (en) 1994-11-10

Family

ID=9446488

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR1994/000427 WO1994025987A1 (en) 1993-04-27 1994-04-15 Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection

Country Status (4)

Country Link
EP (1) EP0647357A1 (en)
JP (1) JPH07509104A (en)
FR (1) FR2704690B1 (en)
WO (1) WO1994025987A1 (en)

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003032387A1 (en) 2001-10-09 2003-04-17 Koninklijke Philips Electronics N.V. Electrical or electronic component and method of producing same
US6791171B2 (en) * 2000-06-20 2004-09-14 Nanonexus, Inc. Systems for testing and packaging integrated circuits
US7276783B2 (en) 2001-07-31 2007-10-02 Infineon Technologies Ag Electronic component with a plastic package and method for production
US7622805B2 (en) 2003-09-09 2009-11-24 Sanyo Electric Co., Ltd. Semiconductor module including circuit component and dielectric film, manufacturing method thereof, and application thereof
JP2010534951A (en) * 2007-07-27 2010-11-11 テッセラ,インコーポレイテッド Reconstituted wafer stacking packaging with after application pad extending portion
JP2010536171A (en) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー Stacked package that the use of recycled wafer
US8349654B2 (en) 2006-12-28 2013-01-08 Tessera, Inc. Method of fabricating stacked packages with bridging traces
US8426957B2 (en) 2006-10-10 2013-04-23 Tessera, Inc. Edge connect wafer level stacking
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US8466542B2 (en) 2009-03-13 2013-06-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
US8476774B2 (en) 2006-10-10 2013-07-02 Tessera, Inc. Off-chip VIAS in stacked chips
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
US8629543B2 (en) 2007-06-11 2014-01-14 Invensas Corporation Electrically interconnected stacked die assemblies
US8680687B2 (en) 2009-06-26 2014-03-25 Invensas Corporation Electrical interconnect for die stacked in zig-zag configuration
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
US8729690B2 (en) 2004-04-13 2014-05-20 Invensas Corporation Assembly having stacked die mounted on substrate
US8884403B2 (en) 2008-06-19 2014-11-11 Iinvensas Corporation Semiconductor die array structure
US8912661B2 (en) 2009-11-04 2014-12-16 Invensas Corporation Stacked die assembly having reduced stress electrical interconnects
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US9305862B2 (en) 2008-03-12 2016-04-05 Invensas Corporation Support mounted electrically interconnected die assembly
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3065309B1 (en) 1999-03-11 2000-07-17 沖電気工業株式会社 A method of manufacturing a semiconductor device
JP4422380B2 (en) * 1999-10-01 2010-02-24 株式会社ルネサステクノロジ A method of manufacturing a semiconductor device
DE10023539B4 (en) * 2000-05-13 2009-04-09 Micronas Gmbh A method for manufacturing a component
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
US7915085B2 (en) 2003-09-18 2011-03-29 Cree, Inc. Molded chip fabrication method
US20050104027A1 (en) * 2003-10-17 2005-05-19 Lazarev Pavel I. Three-dimensional integrated circuit with integrated heat sinks
US7217583B2 (en) 2004-09-21 2007-05-15 Cree, Inc. Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension
JP5614766B2 (en) 2005-12-21 2014-10-29 クリー インコーポレイテッドCree Inc. Lighting device
US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
US7943952B2 (en) 2006-07-31 2011-05-17 Cree, Inc. Method of uniform phosphor chip coating and LED package fabricated using method
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US10295147B2 (en) 2006-11-09 2019-05-21 Cree, Inc. LED array and method for fabricating same
US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8167674B2 (en) 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
CN102144176B (en) 2008-09-08 2013-11-06 皇家飞利浦电子股份有限公司 Production method of radiation detector with a stack of converter plates and interconnect layers
FR2940521B1 (en) 2008-12-19 2011-11-11 3D Plus Method for mass production of electronic modules for surface mounting
US9166126B2 (en) 2011-01-31 2015-10-20 Cree, Inc. Conformally coated light emitting devices and methods for providing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257119A1 (en) * 1986-08-22 1988-03-02 Ibm Deutschland Gmbh Integrated wiring system for VLSI
DE3719742A1 (en) * 1987-06-12 1988-12-29 Siemens Ag Arrangement and method for separation of the semiconductor chips contained in a wafer whilst maintaining their order
WO1990011629A1 (en) * 1989-03-17 1990-10-04 Cray Research, Inc. Memory metal electrical connector
FR2645681A1 (en) * 1989-04-07 1990-10-12 Thomson Csf Vertical interconnection device for integrated-circuit chips and its method of manufacture
WO1991000619A1 (en) * 1989-06-30 1991-01-10 Raychem Corporation Flying leads for integrated circuits
WO1992017901A1 (en) * 1991-03-27 1992-10-15 Integrated System Assemblies Corporation Multichip integrated circuit module and method of fabrication

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257119A1 (en) * 1986-08-22 1988-03-02 Ibm Deutschland Gmbh Integrated wiring system for VLSI
DE3719742A1 (en) * 1987-06-12 1988-12-29 Siemens Ag Arrangement and method for separation of the semiconductor chips contained in a wafer whilst maintaining their order
WO1990011629A1 (en) * 1989-03-17 1990-10-04 Cray Research, Inc. Memory metal electrical connector
FR2645681A1 (en) * 1989-04-07 1990-10-12 Thomson Csf Vertical interconnection device for integrated-circuit chips and its method of manufacture
WO1991000619A1 (en) * 1989-06-30 1991-01-10 Raychem Corporation Flying leads for integrated circuits
WO1992017901A1 (en) * 1991-03-27 1992-10-15 Integrated System Assemblies Corporation Multichip integrated circuit module and method of fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
11th IEEE/CHMT Intl.Electronics Manufacturing Technology Symposium, San Francico, USA, September 16-18, 1991, p. 80-84, C. MEISSER: "Modern Bonding Processes for Large-Scale *

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6791171B2 (en) * 2000-06-20 2004-09-14 Nanonexus, Inc. Systems for testing and packaging integrated circuits
US7276783B2 (en) 2001-07-31 2007-10-02 Infineon Technologies Ag Electronic component with a plastic package and method for production
WO2003032387A1 (en) 2001-10-09 2003-04-17 Koninklijke Philips Electronics N.V. Electrical or electronic component and method of producing same
US8304289B2 (en) 2003-09-09 2012-11-06 Sanyo Electric Co., Ltd. Semiconductor module including circuit component and dielectric film, manufacturing method thereof, and application thereof
US7622805B2 (en) 2003-09-09 2009-11-24 Sanyo Electric Co., Ltd. Semiconductor module including circuit component and dielectric film, manufacturing method thereof, and application thereof
US8729690B2 (en) 2004-04-13 2014-05-20 Invensas Corporation Assembly having stacked die mounted on substrate
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US8426957B2 (en) 2006-10-10 2013-04-23 Tessera, Inc. Edge connect wafer level stacking
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US9899353B2 (en) 2006-10-10 2018-02-20 Tessera, Inc. Off-chip vias in stacked chips
US8461673B2 (en) 2006-10-10 2013-06-11 Tessera, Inc. Edge connect wafer level stacking
US9378967B2 (en) 2006-10-10 2016-06-28 Tessera, Inc. Method of making a stacked microelectronic package
US8476774B2 (en) 2006-10-10 2013-07-02 Tessera, Inc. Off-chip VIAS in stacked chips
US9048234B2 (en) 2006-10-10 2015-06-02 Tessera, Inc. Off-chip vias in stacked chips
US8349654B2 (en) 2006-12-28 2013-01-08 Tessera, Inc. Method of fabricating stacked packages with bridging traces
US8629543B2 (en) 2007-06-11 2014-01-14 Invensas Corporation Electrically interconnected stacked die assemblies
US8723332B2 (en) 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
JP2010534951A (en) * 2007-07-27 2010-11-11 テッセラ,インコーポレイテッド Reconstituted wafer stacking packaging with after application pad extending portion
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8461672B2 (en) 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
JP2010536171A (en) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー Stacked package that the use of recycled wafer
US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
US9252116B2 (en) 2007-09-10 2016-02-02 Invensas Corporation Semiconductor die mount by conformal die coating
US9824999B2 (en) 2007-09-10 2017-11-21 Invensas Corporation Semiconductor die mount by conformal die coating
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
US9305862B2 (en) 2008-03-12 2016-04-05 Invensas Corporation Support mounted electrically interconnected die assembly
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US9508689B2 (en) 2008-05-20 2016-11-29 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8884403B2 (en) 2008-06-19 2014-11-11 Iinvensas Corporation Semiconductor die array structure
US8466542B2 (en) 2009-03-13 2013-06-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
US8680687B2 (en) 2009-06-26 2014-03-25 Invensas Corporation Electrical interconnect for die stacked in zig-zag configuration
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
US9490230B2 (en) 2009-10-27 2016-11-08 Invensas Corporation Selective die electrical insulation by additive process
US8912661B2 (en) 2009-11-04 2014-12-16 Invensas Corporation Stacked die assembly having reduced stress electrical interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9666513B2 (en) 2015-07-17 2017-05-30 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US9859257B2 (en) 2015-12-16 2018-01-02 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board

Also Published As

Publication number Publication date
EP0647357A1 (en) 1995-04-12
JPH07509104A (en) 1995-10-05
FR2704690B1 (en) 1995-06-23
FR2704690A1 (en) 1994-11-04

Similar Documents

Publication Publication Date Title
US7977763B2 (en) Chip package with die and substrate
US6309915B1 (en) Semiconductor chip package with expander ring and method of making same
US8046912B2 (en) Method of making a connection component with posts and pads
US6566168B2 (en) Semiconductor package having implantable conductive lands and method for manufacturing the same
US6246114B1 (en) Semiconductor device and resin film
US7485490B2 (en) Method of forming a stacked semiconductor package
US6004867A (en) Chip-size packages assembled using mass production techniques at the wafer-level
US7993941B2 (en) Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
US6060778A (en) Ball grid array package
US7573136B2 (en) Semiconductor device assemblies and packages including multiple semiconductor device components
US6949834B2 (en) Stacked semiconductor package with circuit side polymer layer
US6753616B2 (en) Flip chip semiconductor device in a molded chip scale package
KR100419352B1 (en) Chip scale surface mount package for semiconductor device and process of fabricating the same
US8115297B2 (en) Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US6124637A (en) Carrier strip and molded flex circuit ball grid array and method of making
USRE39603E1 (en) Process for manufacturing semiconductor device and semiconductor wafer
US5373627A (en) Method of forming multi-chip module with high density interconnections
US8241964B2 (en) Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
US9478486B2 (en) Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
US7344917B2 (en) Method for packaging a semiconductor device
US6316287B1 (en) Chip scale surface mount packages for semiconductor device and process of fabricating the same
US4494688A (en) Method of connecting metal leads with electrodes of semiconductor device and metal lead therefore
US8912648B2 (en) Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
EP0567814B1 (en) Printed circuit board for mounting semiconductors and other electronic components
US8021930B2 (en) Semiconductor device and method of forming dam material around periphery of die to reduce warpage

Legal Events

Date Code Title Description
AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

WWE Wipo information: entry into national phase

Ref document number: 1994913654

Country of ref document: EP

ENP Entry into the national phase in:

Ref country code: US

Ref document number: 1994 351407

Date of ref document: 19941227

Kind code of ref document: A

Format of ref document f/p: F

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 1994913654

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1994913654

Country of ref document: EP