JPH07509104A - Method for encapsulating semiconductor chips, device obtained by this method, and application to three-dimensional chip interconnection - Google Patents
Method for encapsulating semiconductor chips, device obtained by this method, and application to three-dimensional chip interconnectionInfo
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- JPH07509104A JPH07509104A JP6523941A JP52394194A JPH07509104A JP H07509104 A JPH07509104 A JP H07509104A JP 6523941 A JP6523941 A JP 6523941A JP 52394194 A JP52394194 A JP 52394194A JP H07509104 A JPH07509104 A JP H07509104A
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Abstract
(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 半導体チップを封止する方法、この方法によって得られる装置、及び3次元のチ ップの相互接続への適用本発明は、各々が例えば電子部品、集積回路又はセンサ を含んでいる半導体チップを封止する方法及びこの方法によって得られる装置に 関する。さらに本発明は、このような封入をこれらチップの3次元相互接続へ適 用することに関する。[Detailed description of the invention] A method for encapsulating a semiconductor chip, a device obtained by this method, and a three-dimensional chip Application to the interconnection of chips, each for example an electronic component, an integrated circuit or a sensor. A method for encapsulating a semiconductor chip containing a semiconductor chip and a device obtained by this method related. Furthermore, the present invention applies such encapsulation to three-dimensional interconnections of these chips. related to use.
民間用及び軍事用共に最近の電子システムでは、より多(の回路が用いられてい ることから、コンパクト化のより強い要求を考慮に入れて構成する必要がある。Modern electronic systems, both civil and military, use more and more circuitry. Therefore, it is necessary to take into account the stronger demand for compactness.
この点を考オして、例えば、THOMSON−C3Fを出願人とする仏閣特許出 願第2,670,323号に記載されているように、集積回路の「3次元」スタ ック(積み重ね)と称されるものを作成することが既に提案されている。この構 成によれば、スタックの側面に向かう接続ワイヤを設けた後に複数のチップがス タックされ、次いでこれらチップが例えば樹脂によって一体化される。チップの 相互接続は、その後、スタックの側面上で行われる。Taking this point into consideration, for example, a Buddhist patent with THOMSON-C3F as the applicant may be issued. As described in Application No. 2,670,323, "three-dimensional" stacks of integrated circuits It has already been proposed to create what are called stacks. This structure According to the authors, multiple chips are stacked together after providing connecting wires going to the sides of the stack. The chips are then tacked together, for example by resin. of chips Interconnects are then made on the sides of the stack.
本発明の目的は、特に半導体工場においてより容易に実施できるようにかつコス トが低減されるようにこの方法を修正することにある。The purpose of the present invention is to make it easier and more cost-effective to implement, especially in semiconductor factories. The objective is to modify this method so that the costs are reduced.
即ち、本発明の方法によれば、例えばワイヤであるリードは多数のチップを設け た半導体ウェハに直接的に配線され、このウェハは可撓性フィルムに接着されて おり、このウェハは各チップに分割させるべくスクライビングされ、チップを分 離すべく可撓性フィルムが引き伸ばされる。リード及びチップのアセンブリは次 いで例えば重合可能な樹脂である絶縁材料内に一体化され、研磨の後、ワイヤを チップの側面に結合すべくこれらワイヤ上に金属デポジションがなされる。アセ ンブリは次いでチップを分離すべく切断され、これにより、パッケージを構成す る封止材料内に封止され接続導体を有するチップが得られる。「3次元」への適 用として、上述したパッケージは各チップとその次のものとの間に配置された挿 入物によって単純に接着されてスタックされ、次いでこのようにして得られたス タックの側面に例えば前述の仏閣特許出願に記載されているように相互接続がな される。That is, according to the method of the present invention, a lead, which is a wire, for example, is provided with a large number of chips. wired directly onto a semiconductor wafer, which is then glued to a flexible film. This wafer is then scribed to separate each chip. The flexible film is stretched to separate. The lead and tip assembly is as follows. The wire is then integrated into an insulating material, for example a polymerizable resin, and after polishing the wire is Metal depositions are made on these wires to bond to the sides of the chip. Ace The assembly is then cut to separate the chips, thereby making up the package. A chip is obtained which is encapsulated in a encapsulating material and has connecting conductors. Suitability for “3D” For applications, the package described above has an insert placed between each chip and the next one. are simply glued and stacked by the container, and then the strips thus obtained are If the sides of the tack do not have interconnections as described in the above-mentioned Buddhist Patent Application, for example, be done.
本発明のその他の目的、特徴となる構成及び作用効果は、次の添付の図面によっ て説明される実施例の以下の記載から明らかとなるであろう。Other objects, characteristic configurations, and effects of the present invention are illustrated in the accompanying drawings below. It will become clear from the following description of the embodiments described.
図1は、本発明による方法の実施例を表しており、図2〜図4a及び図5は、本 発明による方法の種々のステップを説明する種々の断面図であり、図4bは°、 図4aの平面図であり、 図6及び図7は、本発明の変更態様の概略的な断面図である。FIG. 1 represents an embodiment of the method according to the invention, and FIGS. 4b illustrates various cross-sectional views illustrating various steps of the method according to the invention, FIG. FIG. 4a is a plan view of FIG. 4a; 6 and 7 are schematic cross-sectional views of a modification of the invention.
これら種々の図において、同一の参照符号は同一の要素に関連している。さらに 、より分かりやすくするため、図面は実尺では示されていない。In these various figures, the same reference numbers relate to the same elements. moreover , for better clarity, the drawings are not drawn to scale.
図1は、上述したように、本発明による方法の一実施例を表している。FIG. 1, as mentioned above, represents an embodiment of the method according to the invention.
10で示す第1のステップは、各々が集積回路又はディスクリート部品を含む多 数(通常は数百のオーダ)のチップが形成されている半導体材料のウェハを可撓 性フィルムに固II(例えば接着)することからなる、このフィルムは、例えば ポリマー型の自己接着式のものである。The first step, indicated at 10, is to conduct multiple circuits, each containing integrated circuits or discrete components. A flexible wafer of semiconductor material on which a number (usually on the order of hundreds) of chips are formed. This film consists of hardening (e.g. adhesion) to a plastic film, for example It is a polymer type self-adhesive type.
11で示す第2のステップは、ワイヤ又はストリップである電気的リードをウェ ハ内に設けられた各チップの接続パッドの各々に配線することからなる。The second step, indicated at 11, is to wafer the electrical leads, which may be wires or strips. This consists of wiring each of the connection pads of each chip provided in the chip.
これらの処理動作の結果が図2に示されている。The results of these processing operations are shown in FIG.
この図2は、チップ21が強調されている半導体ウェハlを表わしている。ウェ ハlは、2で示されている可撓性フィルム上に設けられている。ウェハ1の22 で示されているパッドの各々は、例えばワイヤであるリード23に接続されてい る。ワイヤ23は、小さなボール24を得るべくそのワイヤの一端を溶かすこと からなるいわゆる「ポールボンディング」技術によって垂直に接続可能である。This FIG. 2 represents a semiconductor wafer l in which chips 21 are highlighted. We The shell 1 is provided on a flexible film indicated at 2. 22 of wafer 1 Each of the pads shown is connected to a lead 23, for example a wire. Ru. The wire 23 is melted at one end to obtain a small ball 24. They can be connected vertically using the so-called "pole bonding" technique.
例えば図7に示すような他の技術も使用可能である。固着後、ワイヤ23の各々 は、所定の高さに切断される0例えば、ワイヤ径が約25〜30μm、ウェハの 厚さが500μmのオーダ、フィルム2の厚さが200μmのオーダの場合にそ の高さは、例えば150〜200μmであるかもしれない。Other techniques can also be used, for example as shown in FIG. After fixing, each of the wires 23 For example, the wire diameter is about 25-30 μm and the wafer is cut to a predetermined height. When the thickness of film 2 is on the order of 500 μm and the thickness of film 2 is on the order of 200 μm, The height may be, for example, 150-200 μm.
次のステップ(図1の12)は、21で示すごときチップに分割するために、ウ ェハ2を好ましくはその厚み全体にわたってスクライビングすることからなる。The next step (12 in Figure 1) is to divide the wafer into chips as shown at 21. It consists of scribing the wafer 2, preferably over its entire thickness.
13で示す次のステップは5可撓性フイルム2を均一に引き伸ばすことからなる 。これによってチップ21が規則正しく互いに分離する。The next step, indicated at 13, consists in uniformly stretching the flexible film 2. . As a result, the chips 21 are regularly separated from each other.
ウェハ1にワイヤを配線するステップ11が、ある変更態様においては、可撓性 フィルム2を引き伸ばすこのステップ13の後のみ実行可能であることに注目す べきである。In some variations, the step 11 of routing wires to the wafer 1 includes Note that stretching film 2 is only possible after this step 13. Should.
14で示す次のステップは、チップ及びそれらの接続ワイヤを統合して全体を、 例えば有機、エポキシ又はポリイミド樹脂等の電気的絶縁材料を用い例えばキャ スティング又はモールディング法によって封止することからなる。ポリイミド樹 脂は、重合されていることが好ましい。The next step, indicated at 14, is to integrate the chips and their connecting wires to make the whole Using electrically insulating materials such as organic, epoxy or polyimide resins, e.g. It consists of sealing by a sting or molding method. polyimide tree Preferably, the fat is polymerized.
このステップによって得られた結果が図3に示されている。The results obtained by this step are shown in FIG.
この図は、この段階では各々に分割されて互いに分離されているチップ21を担 持するフィルム2を示している。チップ21及びそれらのり−ド23は、チップ 間の間隙26内にも侵入している絶縁材料25内に埋設されている。This figure shows chips 21 which are each divided and separated from each other at this stage. The film 2 shown in FIG. The chips 21 and their glues 23 are chips. It is embedded in an insulating material 25 which also penetrates into the interstices 26 between them.
15で示す次のステップは、ワイヤ23の断面と同高の平面が得られるように封 止材料25の上面(図3の27)を研磨することからなる。The next step, indicated at 15, is to seal the wire 23 so that it has a plane that is flush with the cross section of the wire 23. This consists of polishing the upper surface of the stopper material 25 (27 in FIG. 3).
封止材料25の厚さは、特に熱機械的理由から、ウェハ1及びこれに関連する材 料の厚さに、依存している。−例をあげれば、400・〜5001Lmのウェハ 厚で材料25の厚さは約150μmであるかもしれない。The thickness of the encapsulant material 25 is determined, in particular for thermomechanical reasons, by the thickness of the wafer 1 and its associated materials. It depends on the thickness of the material. - For example, a 400-5001Lm wafer The thickness of material 25 may be approximately 150 μm.
次のステップ(図1の16)は、可撓性フィルム2を除去することからなる。The next step (16 in FIG. 1) consists in removing the flexible film 2.
この除去は、例えばフィルムを引きはがすことによって実施される。ある変更態 様においては、アセンブリの背面、即ち面27の反対側の面(図3の28で示す )が、フィルム2を除去するために及び/又はチップ21の厚さ及び大きさを減 少させるべくこのチップ21を薄くするために研磨される。これは、封止された チップを3次元にスタックする(積み重ねる)以下に述べる用途において、特に 有効であろう。This removal is carried out, for example, by tearing off the film. a certain change 3, the rear side of the assembly, i.e., the side opposite side 27 (designated 28 in Figure 3). ) to remove the film 2 and/or reduce the thickness and size of the chip 21. This chip 21 is polished to make it thinner. This is sealed In the following applications where chips are stacked in three dimensions, especially It would be effective.
ある変更態様においては、可撓性フィルム2は除去されず、これによってチップ の背面28の絶縁及び/又は保護が可能となる。In some variations, the flexible film 2 is not removed, thereby allowing the chip to It is possible to insulate and/or protect the back surface 28 of.
17で示す次のステップは、各リード23を分離後にチップの側面となるものに 結合させる接続導体を形成することからなる。これら接続導体は、チップ間の間 隙上方の上面27へのメタライゼーションによって形成される。The next step, indicated at 17, is to attach each lead 23 to what will become the sides of the chip after separation. It consists of forming a connecting conductor to be coupled. These connecting conductors are connected between the chips. It is formed by metallization on the upper surface 27 above the gap.
図4a及び図4bは、このステップを断面から及び上面から見たものをそれぞれ 示している。Figures 4a and 4b show this step in cross-section and top view, respectively. It shows.
図4aは、材料25内に埋設されたワイヤ23を備えたチップ21を表わしてい る。アセンブリの上面27は、ワイヤ23上のメタライゼーション導体30を備 えている。これらメタライゼーション導体30は、各ワイヤ23をチップ間の間 隙26に結合する。FIG. 4a represents a chip 21 with a wire 23 embedded in a material 25. Ru. The top surface 27 of the assembly includes metallization conductors 30 on the wires 23. It is growing. These metallization conductors 30 connect each wire 23 between chips. It connects to the gap 26.
これらメタライゼーション導体30としては、図4の平面図に示されているよう に種々の形態が想定できる。These metallized conductors 30 are as shown in the plan view of FIG. Various forms can be assumed.
ワイヤ23をチップ間領域26へ結合するかも知れないし、異なるチップからの 2つのワイヤ23を1つに結合するかもしれないし、又は例えばチップを試験す るために後で使用する領域31ヘワイヤ23を付加的に結合するかもしれない。Wires 23 may be coupled to the interchip region 26, and wires 23 from different chips may be connected to One might combine two wires 23 into one, or test a chip, for example. Wires 23 may be additionally bonded to region 31 for later use.
接続導体30は、例えば金属層のデポジション及びこれに続(この層のエツチン グ等、公知のいかなる方法によっても形成することが可能である。デポジション は、例えば真空下でのスパッタリングによってなされる、金、ニッケル及び金、 ニッケルー銅及び金、銅及び金の金属デポジションであり得、恐ら(は電気化学 的めっきである。これに続くエツチングは、例えばホトエツチングであり得る。The connecting conductor 30 can be formed, for example, by the deposition of a metal layer and subsequent etching of this layer. It can be formed by any known method such as Deposition gold, nickel and gold, made for example by sputtering under vacuum Nickel-copper and gold, copper and gold metal deposition, possibly (electrochemical) It's a target. The subsequent etching can be, for example, photoetching.
ある変更態様においては、リードの周辺を除く部分全てに金属を残すいわゆる反 転ホトエツチングが使用可能である。これは、電磁シールドを付加的に形成可能 とするものである。One modification involves a so-called anti-reflection method that leaves metal on all but the periphery of the lead. Transfer photo-etching can be used. This can additionally form an electromagnetic shield That is.
封止されたチップを形成する最後のステップ(図1の18)は、チップ(複数) を分離することからなる。この分離は、例えばダイヤモンド付刃スクライバによ って材料25をチップ間で切断することによってなされる。The final step (18 in Figure 1) to form the encapsulated chip is to It consists of separating the This separation can be achieved, for example, with a diamond-tipped scriber. This is done by cutting the material 25 between the chips.
これにより、パッケージを構成する絶縁材料内にそれらの5つの面が封止された 半導体チップが得られる。このパッケージは試験及び取付けに使用できる接続導 体(メタライゼーション導体30)を備えている。This sealed those five sides within the insulating material that made up the package. A semiconductor chip is obtained. This package contains connection leads that can be used for testing and installation. (metallization conductor 30).
このように封止されたチップを3次元にスタックしたものを作成したい場合(図 1の19)、パッケージは、その2つの側面が一直線となるようにスライド状に 配列され、これによってパッケージの配置に関する問題が単純化される。パッケ ージ間には、例えば重合可能な樹脂等による接着性材料による層が設けられてい る。このアセンブリは、次いで、一体化されるべ(加圧され適当に重合される。If you want to create a three-dimensional stack of sealed chips like this (Fig. 1, 19), slide the package so that its two sides are in a straight line. This simplifies package placement issues. package A layer of adhesive material, such as a polymerizable resin, is provided between the pages. Ru. This assembly is then consolidated (pressurized and suitably polymerized).
この様子が、接着性#32によって互いに分離されたチップ21及びそれらの封 止材料25を示す図5に説明されている。1つの変更態様において、可撓性フィ ルム2について、接着性材料又は適当な処理によって接着性を有するものが層3 2の代わりに用いられ、従って層32の介在が不要となる。スタックの各最端面 上には、層32によって固着された非接着性のシーリング層42が付加的に設け られている。1つの変更態様においては(図示されていない)、シーリング層4 2は、その一方の面が接着性を有しており、これによって層32が不要となる。This situation shows the chips 21 separated from each other by adhesive #32 and their seals. This is illustrated in FIG. 5, which shows the stop material 25. In one variation, the flexible filament For layer 2, layer 3 is made of an adhesive material or has adhesive properties through appropriate treatment. 2, thus eliminating the need for the intervening layer 32. Each end of the stack A non-adhesive sealing layer 42 is additionally provided on top, secured by layer 32. It is being In one variant (not shown), the sealing layer 4 2 has adhesive properties on one side, which eliminates the need for layer 32.
メタライゼーション導体30は、各リード23をスタックのエツジ35に結合す る。A metallization conductor 30 connects each lead 23 to an edge 35 of the stack. Ru.
次のステップ(図1の20)は、スタックの種々のチップを相互接続し、かつそ れらを外部回路と接続可能とすべ(スタックパッドと称するパッドに適切に結合 することからなる。これら相互接続は、例えば前述の仏閣特許出願に記載されて いるように、スタックの面上でなされる。The next step (20 in Figure 1) is to interconnect the various chips of the stack and These can be connected to external circuits (properly coupled to pads called stack pads). consists of doing. These interconnections are described, for example, in the aforementioned Buddhist patent application. is done on the face of the stack, as shown.
図5に示されている例では、種々の接続導体30が全てスタックの側面上に設け られておりかつ例えばスタックの一方の又は両方の最端面上に伸びている(34 )メタライゼーション33によって共に結合されている。メタライゼーション3 3がスタックの両方の最端面上に伸びている場合、その一方は試験に用いられ、 他方は例えばそのスタックをプリント回路上に実装するのに用いられる。In the example shown in Figure 5, the various connecting conductors 30 are all provided on the sides of the stack. and extending, for example, on one or both extreme faces of the stack (34 ) are bonded together by metallization 33. Metallization 3 3 extends on both extreme faces of the stack, one of which is used for testing; The other is used, for example, to implement the stack on a printed circuit.
他の変更態様においては(図示されていない)、非接着性挿入体によって分離さ れていてもよい数個のスタックを同時に形成可能である。次いで、スタックの側 面を介するチップの相互接続が全てのスタックについてまとめて同時に行われる かもしれない。In other variations (not shown), they are separated by a non-adhesive insert. It is possible to form several stacks at the same time, which may be different. Then the side of the stack Chip interconnection through surfaces is done simultaneously for all stacks Maybe.
さらに他の変更態様においては、パッケージ間に放熱器に任意に結合されたヒー トシンクを挿入することによって動作中のチップの冷却を改善可能である。In still other variations, a heat sink is optionally coupled to a heat sink between the packages. Cooling of the chip during operation can be improved by inserting a sink.
図6に表された例は、チップ21、それらのリード23、及び封止材料25を示 している。ワイヤ23をチップの側面のうちの1つに接続する接続導体3oは、 これら側面のうちの1つ、例えばこの図の左側面、に接触しないようになされて いる。例えば銅、窒化アルミニウム、又はダイヤモンド等による金属層のヒート シンク38が、各チップ21の間に接着性層36によって設けられている。スタ ックの左側面は、好ましくは熱伝導性の接着層39によって放熱器37に接着さ れている。この放熱器37はこれによりシンク38に熱接触している6図を簡略 化するために、接着層36は断面であるにもかかわらずハツチングで示されてい ない。The example represented in FIG. 6 shows the chips 21, their leads 23, and the encapsulating material 25. are doing. The connecting conductor 3o connecting the wire 23 to one of the sides of the chip is It is made not to touch one of these sides, for example the left side in this figure. There is. Heating of metal layers, e.g. with copper, aluminum nitride, or diamond A sink 38 is provided between each chip 21 by an adhesive layer 36 . star The left side of the rack is preferably glued to the heat sink 37 by a thermally conductive adhesive layer 39. It is. This radiator 37 is thereby in thermal contact with the sink 38. Figure 6 is simplified. In order to make the adhesive layer 36 easier to understand, the adhesive layer 36 is shown with hatching even though it is a cross section. do not have.
図7は、図1のステップ11.即ちリードのウェハへの配線についての変更態様 を断面で示している。FIG. 7 shows step 11 of FIG. In other words, how to change the wiring of the leads to the wafer. is shown in cross section.
この図は、可撓性フィルム2上に設けられておりリード23をワイヤリングする ことが望ましいバッド22を有するウェハ1を示している。この変更態様によれ ば、ウェハ1の上面には、プリント回路型基板39の一部、好ましくは各チップ について少なくとも1つが設けられている。このプリント回路39は1例えば接 着層4oによってウェハに固着されている。プリント回路39は、少なくとも1 つのメタライゼーション導体41を備えている。この変更態様によれば、リード 23は、切断されておらず、プリント回路39が有するメタライゼーション導体 41に接続可能とするべくカーブされている。さらに、リード23は、前述の図 に表されているようにバッド22に垂直に接続可能であるか、又は図7に表され ているようにメタライゼーション導体41に水平に同様に接続可能である。This figure is provided on the flexible film 2 and wires the leads 23. A wafer 1 is shown having a pad 22 which is desirable. Depending on this change For example, the top surface of the wafer 1 includes a portion of the printed circuit board 39, preferably each chip. At least one is provided for. This printed circuit 39 has one connection, for example. It is fixed to the wafer by an adhesion layer 4o. The printed circuit 39 includes at least one metallization conductor 41. According to this modification, the lead 23 is an uncut metallization conductor that the printed circuit 39 has; It is curved so that it can be connected to 41. Furthermore, the lead 23 is can be connected vertically to the pad 22 as shown in FIG. A similar connection can be made horizontally to the metallization conductor 41 as shown in FIG.
本発明の方法の以後の全ての動作は、前述の場合と同様に行われ、封止材料の研 磨中(ステップ15)、チップの上面と同高となるようにリード23が切断され る。All further operations of the method of the invention are carried out as in the previous case, with the polishing of the sealing material During polishing (step 15), the leads 23 are cut at the same height as the top surface of the chip. Ru.
上述した方法は、これによって得られる装置と同様に、(単一のウェハに全て属 している)多数のチップを同時に処理でき、かつ半導体産業においては公知であ り半導体回路の製造ラインに容易に統合可能な技術を用いてこれを行うことがで きるという多(の効果を有している。これにより、封止されたチップの製造コス トを大幅に低減すると共に、使用する技術の結果、より小さな(特に封止材料の )寸法で製造することができる。典型的には、1%未満のチップ面積の増加をも たらすことができる。さらに、封止のモードは、コスト上の利点をも有しつつま とめてかつ簡単に行うことができるので、「3次元」のスタックに非常に適して いる。The method described above, as well as the resulting device (all belonging to a single wafer) It is possible to process a large number of chips simultaneously, and is well known in the semiconductor industry. This can be done using technology that can be easily integrated into semiconductor circuit manufacturing lines. This has the effect of reducing the manufacturing cost of the encapsulated chip. As a result of the technology used, smaller ) dimensions can be manufactured. Typically increases chip area by less than 1%. can be used. Furthermore, the mode of encapsulation also has cost advantages while It is very suitable for "three-dimensional" stacking because it can be fixed and easily done. There is.
FIG、1 FIG3 FIG、4a FIG 4b フロントページの続き (51) Int、 C1,6識別記号 庁内整理番号HOIL 25/11 IFIG.1 FIG3 FIG. 4a FIG 4b Continuation of front page (51) Int, C1, 6 identification symbol Internal reference number HOIL 25/11 I
Claims (8)
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FR93/04962 | 1993-04-27 | ||
FR9304962A FR2704690B1 (en) | 1993-04-27 | 1993-04-27 | Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions. |
PCT/FR1994/000427 WO1994025987A1 (en) | 1993-04-27 | 1994-04-15 | Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection |
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JPH07509104A true JPH07509104A (en) | 1995-10-05 |
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JP (1) | JPH07509104A (en) |
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Also Published As
Publication number | Publication date |
---|---|
EP0647357A1 (en) | 1995-04-12 |
FR2704690B1 (en) | 1995-06-23 |
FR2704690A1 (en) | 1994-11-04 |
WO1994025987A1 (en) | 1994-11-10 |
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