TW201010036A - Advanced quad flat non-leaded package structure and manufacturing method thereof - Google Patents

Advanced quad flat non-leaded package structure and manufacturing method thereof Download PDF

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Publication number
TW201010036A
TW201010036A TW098119241A TW98119241A TW201010036A TW 201010036 A TW201010036 A TW 201010036A TW 098119241 A TW098119241 A TW 098119241A TW 98119241 A TW98119241 A TW 98119241A TW 201010036 A TW201010036 A TW 201010036A
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Taiwan
Prior art keywords
wafer
package structure
central portion
carrier
quad flat
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TW098119241A
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English (en)
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TWI474455B (zh
Inventor
Chun-Hung Lin
Pao-Huei Changchien
Ping-Cheng Hu
Wei-Lun Cheng
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Advanced Semiconductor Eng
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Publication of TW201010036A publication Critical patent/TW201010036A/zh
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Publication of TWI474455B publication Critical patent/TWI474455B/zh

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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

201010036 Aanj·^ i^u-inEW-FINAL-TW-20090609 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝結構及其製造方法，且特別 是有關於一種先進四方扁平無引腳(advanced quad flat non-leaded，a-QFN)封裝結構及其製造方法 【先前技術】 根據導線架(leadframe)的引腳(lead)的形狀，四方扁平 封裝(4仙(1£^卩&〇1^邑6，（^?)可以分為1型((^1)、：[型((^】) 與無引腳型(QFN)封裝。由於QFN封裝結構具有相對較短 的訊號線(signal trace)以及較快的訊號傳輸速率，因此成為 一種普遍的具有低腳數(pin count)封裝結構，且適用於具有 高頻率(例如，射頻頻寬(radio frequency bandwidth))傳輸的 晶片封裝。 一般來說’在QFN封裝結構的製程中，將多個晶片 配置於導線架上’且藉由多個焊線(bonding wire)而電性連 接至導線架。然後，形成封裝膠體(molding c〇mpound)， 以包覆導線架、晶片與焊線。最後，藉由切割製程 (singulation process)來形成多個QFN封裝結構。 【發明内容】 本發明提供一種先進四方扁平無引腳封裝結構及其 製造方法’其減少了晶片座(die pad)暴露面積，以降低剝 離(delamination)的風險。 201010036 …*一'^Ί-ΝΕ\ν-ΡΙΝΑί-Τν/-20090609 、為了達成上述目的，本發明提出—種先進四方 彳丨腳封裝結構。此先進四方扁平無㈣封裝結構包括承^ .W咖㈣、晶片與封裝膠體。承载器具有上表面與相= 上表面的下表面。承載器包括晶片座與多個引腳。晶座 具有中央部分、周邊部分與多個連接部分。周邊部=配 於中央部分周圍。連接部分連接中央部分與周邊部分。 接部分彼此分離。周邊部分、連接部分盥中麥 〜 〇 ^二個中空啦㈣。引腳配座^ 圍，其中每一個引腳包括配置於上表面上的内引腳與配置 於下表面上的外引腳。晶片配置於承載器的上表面^，且 位於晶片座的中央部分中，其中晶片經由多個導線~ 而電性連接至内引腳。封裝膠體包覆晶片、導線、内引 與部分承栽器。 根據本發明的一實施例’晶片座的周邊部分作為接地 環(ground ring)之用，其中晶片座的周邊部分經由導線而電 性連接至晶片。 ' • 根據本發明的一實施例’承载器更包括至少一個電源 環(power ring)，其中電源環配置於引腳與晶片座的周】^ 分之間’並經由導線而電性連接至晶片，且電源環與接地 壤電性絕緣。 根據本發明的一實施例，先進四方扁平無引腳封裝結 構更包括黏著層’其配置於晶片與晶片座的中央部分之間。 根據本發明的一實施例’晶片座的中央部分具有多邊 形(polygonal)的形狀。 201010036 A*ius^ i^u-jnEW-FINAL-TW-20090609 中央it二實落施:接周邊邹分經由連接部分而與 實簡㈣㈣包括金㈣喊 個相鄰的引腳之間的 根據本發明的一實施例，任何二 距離大於或等於400微米。
邱八m明的—實關’巾料分的底面與周邊 面共平面(coplanar)’而中央部分的上表面與 周邊部分的上表面不共平面。 =據本發明的—實施例，晶片的邊緣與中央部分的邊 緣之間的距離大於或等於300微米。
發明另提出—種歧四方解無引腳封裝結構的 法，其包括以下步驟。首先，提供承載器，其中第 =案化金屬層形成於承顧的上表面上，料二圖案化 詈^形成於承載器的下表面上。承載器包括至少-個容 =八(accommodating cavity)與多個第一開口。然後，提 片曰曰片配置於容置凹穴的中央部分上，且經由多個 、、而電性連接至承載器的第一圖案化金屬層。接著，形 =裝膠體’以包覆晶片、導線、承鮮的第—圖案化金 ^，亚填滿容置凹穴與第一開口。而後，以第二圖案化 穿、尚層為f"幕，對承載器的下表面進行蝕刻製程，以蝕刻 過承载器而暴露出填人第_開口中的封裝膠體，且同時 6 ^0-NEW-FINAL-TW-20090609 201010036 形成多個第二開口與多個第三開口。 根據本發明的一實施例，在蝕刻製程之後，承载器萨 - 由第二開口而定義出多個引腳與晶片座。 W曰 • 根據本發明的一實施例，晶片座藉由第三開口同時定 義出中央部分、周邊部分與多個連接部分。 根據本發明的一實施例，在提供晶片之前，更包括於 容置凹穴的中央部分上形成黏著層。 、 综上所述，根據本發明，承載器的晶片座中具有多個 ❹ +空區域，对空區域暴露出封裝膠體。因此，封裝膠體 與晶片座的接觸面積可以減少’且由於不同材料之間的不 均勻應力所導致的封裝膠體與晶片座之間的剝離問題可以 減輕。另一方面，位於晶片座的中央部分上的晶片可以被 封裝膠體包覆且保護。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 § 圖1A為根據本發明的一實施例所繪示的先進四方扁 斗·無引腳封裝結構的底部示意圖。圖m為沿圖1A中的w， 剖面所繪示的剖面示意圖。圖lc為沿圖1A中的π_π，剖面所 繪示的剖面示意圖。請同時參照圖丨入、圖1Β與圖1C，在 本貫施例中，先進四方扁平無引腳(a_QFN)封裝結構1〇〇包 括承載器200、晶片300與封裝膠體5〇〇。 在本貫施例中，承載器2〇〇例如為導線架。詳細地說， 201010036 /vatijvz iHu-xNfiW-FlNAL-TW-20090609 器MO:有上表面210_相對於上表面21〇a的下表面 承载益200包括晶片座22〇與多個引腳23〇，其中晶片 座220具有中央部分222、周邊部分224與多個連接部分 226。在圖1A中’緣示出四個連接部分挪。然而，晶片座 220可以包括—個或多個連接部分挪，且連接部分挪的數 ^在此並不限疋。周邊部分a#圍繞中央部分垃。連接部 分226連接中央部分222與周邊部分似。由於連接部分226 ，此分離，因此周邊部分224、連接部分226與中央部分222 =義出^四個中空區域s。中空區域s的數目在此並不限 足，但藉由承載器200中連接部分226的數目來決定。 詳細地說，在本實施例中，晶片座220的中央部分222 具有矩形的形狀。中央部分222的底部表面222b與周邊部分 224的底部表面224b共平面，而中央部分222的上表面 與周邊部分224的上表面224a不共平面。如圖ic所示，周 邊部分224的上表面224a高於中央部分222的上表面222a。 然而，晶片座220的中央部分222可以是多邊形的形狀。連 接部分226配置於中央部分222的一侧或角落。特別是，在 本實施例中，連接部分226連接中央部分222的四側與周邊 部分224。值得注意的事，連接部分226的位置、排列或數 篁可以依據封膠製程(molding process)的需求而調整。在本 發明的另一實施例中，晶片座22〇僅具有二個連接部分 226 ’且周邊部分224經由連接部分226而連接至中央部分 222的一個角洛，如圖2所示。 5月參照圖1A與圖1B ’引腳230配置於晶片座220周圍， iU-NEW-FINAL-TW-20090609 201010036 其中每一個引腳230包括内引腳232與外引腳234。舉例來 說，引腳230可以沿著晶片座220的二侧來配置，或配置於 晶片座220的周圍。引腳230的配置方式例如是陣列 (array)、多行或多列，或配置成環狀。引腳23〇的配置方式 可以依據客戶需求或產品需求而客製化(cust〇mized)。引腳 230的材料例如為金或把。 此外，任何二個相鄰的引腳230之間的距離大於或等 於400微米。
晶片300配置於晶片座220的中央部分222，且位於承 載器2〇0的上表面21 〇a上。晶片3〇〇經由多個導線4〇〇而電性 連接至内引腳232與周邊部分224。此外，晶片300的邊緣與 中央部分222的邊緣之間的距離d大於或等於3〇〇微米。 封裝膠體500包覆晶片3〇〇、導線4〇〇、内引腳232、一 部分的晶片座220。換句話說，外引腳234與晶片座22〇的底 部表面未被封裝膠體500覆蓋。此外，晶片座22〇的中空區 域S與引腳230之間的間隙暴露出封裝膠體5〇〇。由於晶片 座220的中空區域S，因此封裝膠體500與晶片座22〇之間的 剝離現象可喊少。封轉體·的材制如為環氧樹脂 (epoxy resin)或其他可應用的聚合物材料 material)。 此外，在本實施例中，在a-QFN封裝結構1〇〇中，晶片 座的财料224例如可轉為接地環之用。另外，承 $器200還可以包括至少—個電4 9 201010036 Astis^: ihu-in£W-F1>JAL-TW-20090609 而電性連接至晶片300。電源環240與接地環224電性絕緣。 再者，在本實施例中，a-QFN封裝結構100更包括黏著 層600。黏著層600配置於晶片300與晶片座22〇的中央部分 222之間，以將晶片300固定於中央部分222。 簡s之，在本發明的實施例中，裝結構 100/100a具有至少一個位於晶片座220的周邊部分224與中 央部分222之間的中空區域s，且中空區域s暴露出封裝膠 體500。因此’可以減少·金屬氧化或㈣勻應力所導致 的封裝膠體500與晶片座220之間的剝離問題。 以下將以圖3A至圖31來說明本發明的^(^^封裝結構 100的製作流程。 圖3 A至圖31為根據本發明的一實施例所繪示的先進 四方扁平無引腳封裝結構的製造流程剖面圖，其中圖3H的 次圖⑻為沿圖1A中的14，剖面所繪示的剖面示意圖，而圖 3H的-人圖（b)為沿圖ία中的11-11’剖面所繪示的剖面示意 圖。為了方便說明，在本實施例中將省略電源環。 首先，請參照圖3A，提供具有上表面21〇a與下表面 21〇b的基底21〇。基底210的材料例如為銅、銅合金或其他 可應用的金屬材料。然後，於基底21⑽上表面2收上形成 第一圖案化光阻層214a，且於基底21〇的下表面212b上形成 第二圖案化光阻層214b。 然後，、，參照圖3B，於暴露出來的基底21〇的上表面 210a上形成第—金屬層216a，且於暴露出來的基底21〇的下 表面210b上形成第二金屬層216b。在本實施例中’形成第 10 ^40-NEW-FINAL-TW-20090609 201010036 -金屬層2i6a與第二金屬層的方法例 (plating)。 又 接著，請參照圖3C，移除第-圖案化光阻層2Ma，以 於基底210的上表面210a上形成第一圖案化金屬層薦。 而後，請參照圖3D，以第1案化金屬層218a作為敍 刻罩幕’進行侧製程來移除一部分的基底21〇，以形成至 少一個容置凹穴220a與多個第。錢，移除第二 圖案化光阻層214b，以於基底210的下表面21〇b上形成第二 _案化金屬層218b。藉由第1 DS1而彼此分離的第一圖 案化金屬層218a將在後續步驟中形成内引腳232。第一圖案 化金屬層218a的圖案與第二圖案化金屬層218b的圖案不相 同或不對稱。在此階段，約略形成了承載器2〇〇。 繼之，請參照圖3E，將晶片300提供至每一個容置凹 穴220a的中央部分222 ’且於晶片300與容置凹穴220a的中 央部分222之間形成黏著層6〇〇。配置於晶片3〇〇與容置凹穴 220a的中央部分222之間的黏著層600有助於將晶片300固 _ 定於中央部分222。 隨後，請參照圖3F，經由導線400將晶片300電性連接 至即將形成的内引腳232。 然後，請參照3G，形成封裝膠體500，以包覆晶片300、 導線400、即將形成的内引腳232，且填入容置凹穴220a與 第一開口 S1。 之後，請參照圖3H(a)與圖3H(b)，以第二圖案化金屬 層218b作為罩幕，對暴露出來的承載器200的下表面 11 201010036
AbtJ^z 14U-jnEW-FINAL-TW^20〇9〇6〇9 程，崎㈣過暴露的基底 、’ =因此，第—開口 S1中的封裝膠體500 $路出來’且同時形成了多個第二開nS2與多個第三開 」寺別地，由於第二開nS2的形成，基底2職姓刻穿， 且疋義出了内引腳232與外引腳234。内引腳232藉由第-開 口si而彼此物理分離與電性分離。外引腳234藉由第二開 口 S2而彼此物理分離與電性分離。第三開口幻定義容置凹 穴220a中的基底21G ’以形成具有中央部分222、圍繞中* ❿ 部分222的周邊部分224與多個連接部分226的晶片座22〇。 連接部分226藉由第三開口 S3而彼此分離。 詳細地說，晶片座220的中央部分222被周邊部分224 圍繞，且連接部分226連接中央部分222與周邊部分224。如 圖1C所示，中央部分222的底部表面222b與周邊部分224的 底部表面224b以及連接部分226的底部表面226b共平面，且 中央部分222的上表面222a與連接部分226的上表面226a共 平面’但疋不與周邊部分224的上表面224a共平面。晶片300 的邊緣與中央部分222的邊緣之間的距離大於或等於3〇〇微 參 米。 之後’請參照圖31 ’藉由鑛開製程(sawing process)來 進行切割製程。切割製程還可以包括衝壓製程(punch process)。切割的目的在於完全切斷承載器2〇〇與封裝膠體 500，以得到多個a_QFN封裝結構100。在圖31中，僅繚示 出二個a-QFN封裝結構100。 12 --40-NEW-FINAL-TW-20090609 201010036 成第簡^ Μ Ϊ由對基底的下表面進行⑽製程來同時形 開口而被暴露出來。此外，由於開口 育1/、 膠體之間的接觸面積可以減小，二= 離的問通’以及增進製程品#與產品良率。 本私日露如上，料並_以限定 二:之=斤屬技術領域中具有通常知識者’在不脫離 ❹ ❿ 圍内’當可作些許之更動與潤飾，故本 發月之保㈣^視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A為根據本發明的一實施例所纷示的先進四方 平…、引腳封裝結構的底部示意圖。 ^為沿圖1A中的14’剖面翁示的剖面示意圖。 圖為沿圖1A中的随，剖面所綠示的剖面示意圖。 圖2^根據本發明的另—實施例崎示祕進四方扁 千‘，，'引腳封裝結構的底部示意圖。 圖3A至圖31為根據本發明的一實施例所繪示的先進 扁平無引腳封袭結構的製造流程剖㈣，其中圖扭 圖二^圖^為沿圖1A中的u，剖面所緣示的剖面示意圖’而 、人圖（b)為沿圖1A中的關’剖面所繪示的剖面示 思圖。 13 201010036 ASEK2140-NEW-FINAL-TW-20090609 【主要元件符號說明】 100、100a :先進四方扁平無引腳封裝結構 200:承載器 210a、222a、224a、226a :上表面 . 210b、212b ··下表面 214a、218a :第一圖案化光阻層 214b、218a:第二圖案化光阻層 216a:第一金屬層 216b :第二金屬層 220 ·晶片座 參 220a :容置凹穴 222 :中央部分 224 :周邊部分 224b、222b、226b :底部表面 226 :連接部分 230 :引腳 232 :内引腳 234 :外引腳 240··電源環 β 300:晶 400 :導線 500 :封裝膠體 600 :黏著層 d :距離 S :中空區域 51 :第一開口 52 :第二開口 53 :第三開口 14

Claims (1)

  1. 201010036 八 u a i〇-NE W-FINAL-T W-20090609 七、申請專利範面： 包括： 其中該承載器 1. 一種先進四方扁平無引腳封裝結 一承載器，具有一上表面與—下表 包括： ’ 日曰片座，具有一中央部分
    連接部分，其巾制邊部分雜針央U邊部分與多個===:巧部分 且該中央部分、該周邊部分與該些連 少二申空區域；以及 部分定義出至 圍，其中每一引腳 置於該下表面上的 多個引腳，配置於該晶片座周 包括配置於該上表面上的一内引腳與配 一外引腳； 晶片 -置於祕储的虹表面上 片座的射央部分’其中該晶片經由多個 性： 至該些内引腳；以及 电ϋ連接
    一封裝膠體，包覆該晶片 部份該承載器。 該些導線、該些内引腳與 2.如申請專職圍幻項騎之先進四 封裝結構，其中該晶片座的該周邊部分作為一 ^二引腳 中該晶片座的該周邊部分經由該些導線而電二f 3.如申請專利範圍第2項所述之先進四 封裝結構’其中該承載器更包括至少—雷、篇與十…、引腳 I #壤，甘φ ,、、语 環配置於該些引腳與該晶片座的該周邊部分之一 “、 间’且經由 15 201010036 i^u-inEW-FINAL-TW-20090609 該些導線而電性連接至該晶片 地環電性絕緣。 ，且該至少一電源環與該接 4.如申請專利範圍第1項所述之先進四方扁平無引腳 封裝結構，更包括一黏著層，配置於該晶片與該晶片座 該中央部分之間。 '日日 5·如申請專利範圍第1項所述之先進四方扁平無引 腳封裝結構，其中該晶片座的該中央部分具有多邊形^形 6. 如申請專利範圍第5項所述之先進四方扁平無引腳 封裝結構，其中該周邊部分經由該些連接部分而 中央部分的至少一側。 7. 如申請專利範圍第5項所述之先進四方扁平無引腳 封裝結構，其中該周邊部分經由該些連接部分而連接至令 中央部分的至少一角落。 交人 8. 如申請專利範圍第味所述之先進四方扁平無引腳 封裝結構，其中該些引腳的材料包括金或鈀。 9. 如申請專利範圍第丨項所述之先進四方扁平無引腳 封裝結構，其中任何二個相鄰的該些引腳之間的距離大於 或等於400微米。 ' ίο.如申請專利範圍第1項所述之先進四方扁平無引 腳封裝結構，其中該中央部分的底部表面與該周邊部&的 底部表面共平面，而該中央部分的上表面與該周邊部二的 上表面不共平面。 ° 77 η•如申請專利範圍第1項所述之先進四方扁平無引 16 U)-NEW-FINAL-TW-20090609 201010036 腳封裝結構，其甲該晶片的邊緣與該中央部分的邊緣之間 的距離大於或等於300微未。 包括以-種先進四方扁平無引卿封裝結構的製造方法， 承載H ’―第—圖案化金屬層形成於該承载器 m二随化金屬層形成於該承載器的 一:=面上，其中該承载器包括至少—容置凹穴與多個第 ❹ 邻八提供3日片’亚將該晶片配置於該容置凹穴的一中央 案二金=由多個導線而電性連接至該承載器的該第一圖 器的包覆該晶片、該些導線、該承載 開口；以及圖金屬層，且填人該容置凹穴與該些第一 進行案化金屬為罩幕，對該承彻賴下表面 第-開口2程’簡刻穿過該承載器而暴露出填入該些 個第三開^該封鱗體，且同時形成多個第二開口與多 晶 腳封裝結圍2項所述之先進四方扁平無引 承栽^ 法，其中在進行該蝕刻製程之後.，Ί 座。° 3該些第二開口而被定義出多個引腳與一 17 201010036 ihu-inEW-FINAL-TW-20090609 而同時被定義出該中央部分、一周邊部分與多個連接部分。 15.如申請專利範圍第12項所述之先進四方扁平無 引腳封裝結構的製造方法，其中在提供該晶片之前，更包 括於該容置凹穴的該中央部分上形成一黏著層。 ❿ 1S
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401755B (zh) * 2010-08-10 2013-07-11 Adl Engineering Inc 四邊扁平無接腳封裝方法
CN106449528A (zh) * 2015-08-13 2017-02-22 稳懋半导体股份有限公司 高频封装结构
TWI655729B (zh) * 2011-06-20 2019-04-01 乾坤科技股份有限公司 一種封裝結構及其製造方法

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8492883B2 (en) * 2008-03-14 2013-07-23 Advanced Semiconductor Engineering, Inc. Semiconductor package having a cavity structure
US20100044850A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US7858443B2 (en) * 2009-03-09 2010-12-28 Utac Hong Kong Limited Leadless integrated circuit package having standoff contacts and die attach pad
KR100935854B1 (ko) 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
KR100950511B1 (ko) 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
JP2010238693A (ja) * 2009-03-30 2010-10-21 Toppan Printing Co Ltd 半導体素子用基板の製造方法および半導体装置
US8575742B1 (en) * 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20110115063A1 (en) * 2009-11-18 2011-05-19 Entropic Communications, Inc. Integrated Circuit Packaging with Split Paddle
US20110163430A1 (en) * 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
CN102194775B (zh) * 2010-03-03 2013-04-17 南茂科技股份有限公司 四边扁平无接脚封装结构
US8241956B2 (en) * 2010-03-08 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming wafer level multi-row etched lead package
TWI479580B (zh) * 2010-03-12 2015-04-01 矽品精密工業股份有限公司 四方平面無導腳半導體封裝件及其製法
US8203201B2 (en) * 2010-03-26 2012-06-19 Stats Chippac Ltd. Integrated circuit packaging system with leads and method of manufacture thereof
CN202275822U (zh) 2010-04-28 2012-06-13 先进封装技术私人有限公司 半导体封装件以及其基板
CN102244063A (zh) * 2010-05-14 2011-11-16 矽品精密工业股份有限公司 具有多边形芯片座的半导体封装件及其制法
KR101128999B1 (ko) * 2010-07-08 2012-03-23 엘지이노텍 주식회사 칩 패키지 제조 방법 및 이에 의해 제조된 칩 패키지
US8669654B2 (en) * 2010-08-03 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with die paddle and method of manufacture thereof
CN104658923B (zh) * 2010-09-01 2018-08-14 群成科技股份有限公司 四边扁平无接脚封装方法及其制成的结构
US8304277B2 (en) 2010-09-09 2012-11-06 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking
US8476772B2 (en) * 2010-09-09 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die
TWI420630B (zh) 2010-09-14 2013-12-21 Advanced Semiconductor Eng 半導體封裝結構與半導體封裝製程
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8519518B2 (en) * 2010-09-24 2013-08-27 Stats Chippac Ltd. Integrated circuit packaging system with lead encapsulation and method of manufacture thereof
US8546903B2 (en) * 2010-10-07 2013-10-01 Texas Instruments Incorporated Ionic isolation ring
US8912046B2 (en) * 2010-10-28 2014-12-16 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof
TWI419290B (zh) 2010-10-29 2013-12-11 Advanced Semiconductor Eng 四方扁平無引腳封裝及其製作方法
US20120140427A1 (en) * 2010-12-01 2012-06-07 Mediatek Inc. Printed circuit board (pcb) assembly with advanced quad flat no-lead (a-qfn) package
CN102487019B (zh) * 2010-12-02 2016-06-22 三星半导体(中国)研究开发有限公司 制造芯片封装件的方法
US8735224B2 (en) * 2011-02-14 2014-05-27 Stats Chippac Ltd. Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
US20120241926A1 (en) * 2011-03-23 2012-09-27 Zigmund Ramirez Camacho Integrated circuit packaging system with leveling standoff and method of manufacture thereof
CN102214635A (zh) * 2011-05-27 2011-10-12 日月光半导体制造股份有限公司 半导体封装结构及其制作方法
US8502363B2 (en) 2011-07-06 2013-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with solder joint enhancement element and related methods
US8513787B2 (en) * 2011-08-16 2013-08-20 Advanced Analogic Technologies, Incorporated Multi-die semiconductor package with one or more embedded die pads
CN102354689B (zh) * 2011-11-04 2013-12-04 北京工业大学 一种面阵引脚排列四边扁平无引脚封装及制造方法
US9219029B2 (en) 2011-12-15 2015-12-22 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8623711B2 (en) * 2011-12-15 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8629567B2 (en) 2011-12-15 2014-01-14 Stats Chippac Ltd. Integrated circuit packaging system with contacts and method of manufacture thereof
CN102522391B (zh) * 2011-12-31 2014-11-05 天水华天科技股份有限公司 一种具有接地环的e/LQFP堆叠封装件及其生产方法
TWI462255B (zh) * 2012-02-29 2014-11-21 矽品精密工業股份有限公司 封裝結構、基板結構及其製法
US8674487B2 (en) * 2012-03-15 2014-03-18 Advanced Semiconductor Engineering, Inc. Semiconductor packages with lead extensions and related methods
US9653656B2 (en) 2012-03-16 2017-05-16 Advanced Semiconductor Engineering, Inc. LED packages and related methods
CN102629599B (zh) * 2012-04-06 2014-09-03 天水华天科技股份有限公司 四边扁平无引脚封装件及其生产方法
US9059379B2 (en) 2012-10-29 2015-06-16 Advanced Semiconductor Engineering, Inc. Light-emitting semiconductor packages and related methods
US9324584B2 (en) * 2012-12-14 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with transferable trace lead frame
CN103065975B (zh) * 2012-12-17 2015-05-13 北京工业大学 一种再布线qfn封装器件的制造方法
US9368423B2 (en) * 2013-06-28 2016-06-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die package
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
CN105355619B (zh) * 2015-12-03 2018-11-02 日月光封装测试(上海)有限公司 导线框架条
CN105789072B (zh) * 2016-05-04 2018-06-08 天水华天科技股份有限公司 一种面阵列无引脚csp封装件及其制造方法
TWI604585B (zh) * 2016-12-23 2017-11-01 恆勁科技股份有限公司 基板結構的製造方法
JP6857035B2 (ja) * 2017-01-12 2021-04-14 ローム株式会社 半導体装置
US10134660B2 (en) * 2017-03-23 2018-11-20 Nxp Usa, Inc. Semiconductor device having corrugated leads and method for forming
TW201916182A (zh) * 2017-09-14 2019-04-16 矽品精密工業股份有限公司 電子封裝件
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
CN113035721A (zh) * 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 用于侧壁镀覆导电膜的封装工艺
CN113035722A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺

Family Cites Families (144)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69111002T2 (de) 1990-09-20 1995-11-02 Dainippon Screen Mfg Verfahren zur Herstellung von kleinen Durchgangslöchern in dünne Metallplatten.
US5389739A (en) 1992-12-15 1995-02-14 Hewlett-Packard Company Electronic device packaging assembly
US5497032A (en) * 1993-03-17 1996-03-05 Fujitsu Limited Semiconductor device and lead frame therefore
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5646831A (en) 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5847458A (en) 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
KR0185512B1 (ko) 1996-08-19 1999-03-20 김광호 칼럼리드구조를갖는패키지및그의제조방법
US6097098A (en) * 1997-02-14 2000-08-01 Micron Technology, Inc. Die interconnections using intermediate connection elements secured to the die face
US6201292B1 (en) 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
JP2928190B2 (ja) 1997-04-09 1999-08-03 九州日本電気株式会社 テーピングリードフレーム
KR100235308B1 (ko) 1997-06-30 1999-12-15 윤종용 2중 굴곡된 타이바와 소형 다이패드를 갖는 반도체 칩 패키지
US6132593A (en) 1998-06-08 2000-10-17 Tan; Yong-Jun Method and apparatus for measuring localized corrosion and other heterogeneous electrochemical processes
US7226811B1 (en) 1998-06-10 2007-06-05 Asat Ltd. Process for fabricating a leadless plastic chip carrier
US6989294B1 (en) 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US6585905B1 (en) 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6635957B2 (en) 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6933594B2 (en) 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US7247526B1 (en) * 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
US7049177B1 (en) * 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
US7271032B1 (en) 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
JP3764587B2 (ja) 1998-06-30 2006-04-12 富士通株式会社 半導体装置の製造方法
JP4030200B2 (ja) * 1998-09-17 2008-01-09 株式会社ルネサステクノロジ 半導体パッケージおよびその製造方法
US6667541B1 (en) 1998-10-21 2003-12-23 Matsushita Electric Industrial Co., Ltd. Terminal land frame and method for manufacturing the same
US6303985B1 (en) 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
WO2000033379A1 (en) 1998-12-02 2000-06-08 Hitachi, Ltd. Semiconductor device, method of manufacture thereof, and electronic device
SG75154A1 (en) 1999-02-23 2000-09-19 Inst Of Microelectronics Plastic ball grid array package
JP3780122B2 (ja) 1999-07-07 2006-05-31 株式会社三井ハイテック 半導体装置の製造方法
US20020100165A1 (en) 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
US6451627B1 (en) 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
TW423133B (en) 1999-09-14 2001-02-21 Advanced Semiconductor Eng Manufacturing method of semiconductor chip package
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
US6580159B1 (en) * 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
JP2001185651A (ja) * 1999-12-27 2001-07-06 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
US6333252B1 (en) 2000-01-05 2001-12-25 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6342730B1 (en) 2000-01-28 2002-01-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6261864B1 (en) 2000-01-28 2001-07-17 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US7173336B2 (en) 2000-01-31 2007-02-06 Sanyo Electric Co., Ltd. Hybrid integrated circuit device
US7091606B2 (en) 2000-01-31 2006-08-15 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device and semiconductor module
EP1122778A3 (en) 2000-01-31 2004-04-07 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
JP3706533B2 (ja) 2000-09-20 2005-10-12 三洋電機株式会社 半導体装置および半導体モジュール
US6306685B1 (en) 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
US6238952B1 (en) 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6562660B1 (en) 2000-03-08 2003-05-13 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
US6242284B1 (en) 2000-05-05 2001-06-05 Advanced Semiconductor Engineering, Inc. Method for packaging a semiconductor chip
JP3883784B2 (ja) 2000-05-24 2007-02-21 三洋電機株式会社 板状体および半導体装置の製造方法
JP2001338947A (ja) 2000-05-26 2001-12-07 Nec Corp フリップチップ型半導体装置及びその製造方法
US6683368B1 (en) 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
TW507482B (en) 2000-06-09 2002-10-21 Sanyo Electric Co Light emitting device, its manufacturing process, and lighting device using such a light-emitting device
TW506236B (en) 2000-06-09 2002-10-11 Sanyo Electric Co Method for manufacturing an illumination device
JP3650001B2 (ja) 2000-07-05 2005-05-18 三洋電機株式会社 半導体装置およびその製造方法
US6429536B1 (en) 2000-07-12 2002-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device
TW473965B (en) 2000-09-04 2002-01-21 Siliconware Precision Industries Co Ltd Thin type semiconductor device and the manufacturing method thereof
TW497371B (en) 2000-10-05 2002-08-01 Sanyo Electric Co Semiconductor device and semiconductor module
US6762118B2 (en) * 2000-10-10 2004-07-13 Walsin Advanced Electronics Ltd. Package having array of metal pegs linked by printed circuit lines
JP4417541B2 (ja) * 2000-10-23 2010-02-17 ローム株式会社 半導体装置およびその製造方法
JP3653460B2 (ja) 2000-10-26 2005-05-25 三洋電機株式会社 半導体モジュールおよびその製造方法
US6689640B1 (en) 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
JP3895570B2 (ja) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
US6720207B2 (en) * 2001-02-14 2004-04-13 Matsushita Electric Industrial Co., Ltd. Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
US6551859B1 (en) 2001-02-22 2003-04-22 National Semiconductor Corporation Chip scale and land grid array semiconductor packages
US6661083B2 (en) 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
US6545347B2 (en) * 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
JP3609737B2 (ja) 2001-03-22 2005-01-12 三洋電機株式会社 回路装置の製造方法
KR100393448B1 (ko) 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP4034073B2 (ja) 2001-05-11 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003017646A (ja) * 2001-06-29 2003-01-17 Matsushita Electric Ind Co Ltd 樹脂封止型半導体装置およびその製造方法
US7235868B2 (en) 2001-07-09 2007-06-26 Sumitomo Metal Mining Co., Ltd. Lead frame and its manufacturing method
TW538658B (en) 2001-08-27 2003-06-21 Sanyo Electric Co Manufacturing method for circuit device
JP2003124421A (ja) 2001-10-15 2003-04-25 Shinko Electric Ind Co Ltd リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法
US7001798B2 (en) 2001-11-14 2006-02-21 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device
TW523887B (en) 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
JP4173346B2 (ja) 2001-12-14 2008-10-29 株式会社ルネサステクノロジ 半導体装置
JP4526823B2 (ja) 2002-04-11 2010-08-18 エヌエックスピー ビー ヴィ キャリヤ、キャリヤを製造する方法および電子機器
US7799611B2 (en) 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6777265B2 (en) 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP2004063615A (ja) 2002-07-26 2004-02-26 Nitto Denko Corp 半導体装置の製造方法、半導体装置製造用接着シートおよび半導体装置
KR20040030283A (ko) 2002-09-05 2004-04-09 신꼬오덴기 고교 가부시키가이샤 리드 프레임 및 그 제조 방법
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
JP4159431B2 (ja) * 2002-11-15 2008-10-01 株式会社ルネサステクノロジ 半導体装置の製造方法
EP1579502A2 (en) 2002-12-20 2005-09-28 Koninklijke Philips Electronics N.V. Electronic device and method of manufacturing same
US6927483B1 (en) * 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
TW200425427A (en) 2003-05-02 2004-11-16 Siliconware Precision Industries Co Ltd Leadframe-based non-leaded semiconductor package and method of fabricating the same
TWI233674B (en) 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof
JP2007509485A (ja) 2003-08-14 2007-04-12 アドバンスド インターコネクト テクノロジーズ リミテッド 半導体デバイス・パッケージおよびその製造方法
TWI257693B (en) 2003-08-25 2006-07-01 Advanced Semiconductor Eng Leadless package
US7060535B1 (en) 2003-10-29 2006-06-13 Ns Electronics Bangkok (1993) Ltd. Flat no-lead semiconductor die package including stud terminals
KR100568225B1 (ko) 2003-11-06 2006-04-07 삼성전자주식회사 리드 프레임 및 이를 적용한 반도체 패키지 제조방법
JP2005191240A (ja) 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
JP2005191342A (ja) * 2003-12-26 2005-07-14 Renesas Technology Corp 半導体装置およびその製造方法
TWI254437B (en) 2003-12-31 2006-05-01 Advanced Semiconductor Eng Leadless package
US7122406B1 (en) 2004-01-02 2006-10-17 Gem Services, Inc. Semiconductor device package diepad having features formed by electroplating
JP2005203390A (ja) 2004-01-13 2005-07-28 Seiko Instruments Inc 樹脂封止型半導体装置の製造方法
US7009286B1 (en) * 2004-01-15 2006-03-07 Asat Ltd. Thin leadless plastic chip carrier
US7494557B1 (en) 2004-01-30 2009-02-24 Sandia Corporation Method of using sacrificial materials for fabricating internal cavities in laminated dielectric structures
US7215009B1 (en) * 2004-02-23 2007-05-08 Altera Corporation Expansion plane for PQFP/TQFP IR—package design
US7008820B2 (en) * 2004-06-10 2006-03-07 St Assembly Test Services Ltd. Chip scale package with open substrate
CN2726111Y (zh) 2004-06-22 2005-09-14 胜开科技股份有限公司 堆叠集成电路封装组件
WO2006008679A2 (en) 2004-07-13 2006-01-26 Koninklijke Philips Electronics N.V. Electronic device comprising an integrated circuit
US7087461B2 (en) * 2004-08-11 2006-08-08 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages
TWI256096B (en) 2004-10-15 2006-06-01 Advanced Semiconductor Eng Method for fabricating quad flat non-leaded package
US7598606B2 (en) * 2005-02-22 2009-10-06 Stats Chippac Ltd. Integrated circuit package system with die and package combination
US7087462B1 (en) * 2005-06-07 2006-08-08 Advanced Semiconductor Engineering, Inc. Method for forming leadless semiconductor packages
US7348663B1 (en) 2005-07-15 2008-03-25 Asat Ltd. Integrated circuit package and method for fabricating same
TWI287275B (en) * 2005-07-19 2007-09-21 Siliconware Precision Industries Co Ltd Semiconductor package without chip carrier and fabrication method thereof
JP3947750B2 (ja) 2005-07-25 2007-07-25 株式会社三井ハイテック 半導体装置の製造方法及び半導体装置
EP1921674A4 (en) 2005-08-10 2010-08-25 Mitsui High Tec SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
US7262491B2 (en) 2005-09-06 2007-08-28 Advanced Interconnect Technologies Limited Die pad for semiconductor packages and methods of making and using same
TWI264091B (en) * 2005-09-15 2006-10-11 Siliconware Precision Industries Co Ltd Method of manufacturing quad flat non-leaded semiconductor package
US8163604B2 (en) 2005-10-13 2012-04-24 Stats Chippac Ltd. Integrated circuit package system using etched leadframe
US7372133B2 (en) * 2005-12-01 2008-05-13 Intel Corporation Microelectronic package having a stiffening element and method of making same
TW200729429A (en) 2006-01-16 2007-08-01 Siliconware Precision Industries Co Ltd Semiconductor package structure and fabrication method thereof
TW200729444A (en) 2006-01-16 2007-08-01 Siliconware Precision Industries Co Ltd Semiconductor package structure and fabrication method thereof
JP2007221045A (ja) 2006-02-20 2007-08-30 Oki Electric Ind Co Ltd マルチチップ構造を採用した半導体装置
US7301225B2 (en) 2006-02-28 2007-11-27 Freescale Semiconductor, Inc. Multi-row lead frame
TWI286375B (en) * 2006-03-24 2007-09-01 Chipmos Technologies Inc Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for fabricating the same
US7683461B2 (en) * 2006-07-21 2010-03-23 Stats Chippac Ltd. Integrated circuit leadless package system
US20080029855A1 (en) 2006-08-04 2008-02-07 Yi-Ling Chang Lead Frame and Fabrication Method thereof
SG140574A1 (en) * 2006-08-30 2008-03-28 United Test & Assembly Ct Ltd Method of producing a semiconductor package
JP4533875B2 (ja) 2006-09-12 2010-09-01 株式会社三井ハイテック 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法
US20080079124A1 (en) 2006-10-03 2008-04-03 Chris Edward Haga Interdigitated leadfingers
US7741704B2 (en) 2006-10-18 2010-06-22 Texas Instruments Incorporated Leadframe and mold compound interlock in packaged semiconductor device
CN101601133B (zh) * 2006-10-27 2011-08-10 宇芯（毛里求斯）控股有限公司 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US7608484B2 (en) * 2006-10-31 2009-10-27 Texas Instruments Incorporated Non-pull back pad package with an additional solder standoff
US7608482B1 (en) 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
US7605477B2 (en) 2007-01-25 2009-10-20 Raytheon Company Stacked integrated circuit assembly
US7800211B2 (en) 2007-06-29 2010-09-21 Stats Chippac, Ltd. Stackable package by using internal stacking modules
US7675146B2 (en) 2007-09-07 2010-03-09 Infineon Technologies Ag Semiconductor device with leadframe including a diffusion barrier
US20090127682A1 (en) 2007-11-16 2009-05-21 Advanced Semiconductor Engineering, Inc. Chip package structure and method of fabricating the same
US7808089B2 (en) 2007-12-18 2010-10-05 National Semiconductor Corporation Leadframe having die attach pad with delamination and crack-arresting features
US8492883B2 (en) 2008-03-14 2013-07-23 Advanced Semiconductor Engineering, Inc. Semiconductor package having a cavity structure
TWI368983B (en) 2008-04-29 2012-07-21 Advanced Semiconductor Eng Integrated circuit package and manufacturing method thereof
TW200947654A (en) 2008-05-12 2009-11-16 Advanced Semiconductor Eng Stacked type chip package structure and method of fabricating the same
TWI372458B (en) 2008-05-12 2012-09-11 Advanced Semiconductor Eng Stacked type chip package structure
US7786557B2 (en) 2008-05-19 2010-08-31 Mediatek Inc. QFN Semiconductor package
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
CN101442035B (zh) 2008-12-14 2011-03-16 天水华天科技股份有限公司 一种扁平无引线封装件及其生产方法
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20110163430A1 (en) 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401755B (zh) * 2010-08-10 2013-07-11 Adl Engineering Inc 四邊扁平無接腳封裝方法
TWI655729B (zh) * 2011-06-20 2019-04-01 乾坤科技股份有限公司 一種封裝結構及其製造方法
CN106449528A (zh) * 2015-08-13 2017-02-22 稳懋半导体股份有限公司 高频封装结构
US9653408B2 (en) 2015-08-13 2017-05-16 Win Semiconductors Corp. High-frequency package
US9673152B2 (en) 2015-08-13 2017-06-06 Win Semiconductors Corp. High-frequency package
TWI627713B (zh) * 2015-08-13 2018-06-21 穩懋半導體股份有限公司 高頻封裝結構
CN106449528B (zh) * 2015-08-13 2019-05-07 稳懋半导体股份有限公司 高频封装结构

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