CN202275822U - 半导体封装件以及其基板 - Google Patents

半导体封装件以及其基板 Download PDF

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Publication number
CN202275822U
CN202275822U CN2011201320460U CN201120132046U CN202275822U CN 202275822 U CN202275822 U CN 202275822U CN 2011201320460 U CN2011201320460 U CN 2011201320460U CN 201120132046 U CN201120132046 U CN 201120132046U CN 202275822 U CN202275822 U CN 202275822U
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China
Prior art keywords
layer
chip carrier
limiting section
joint sheet
substrate
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CN2011201320460U
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周辉星
林少雄
林建福
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Advanpack Solutions Pte Ltd
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Advanpack Solutions Pte Ltd
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Abstract

本实用新型公开半导体封装件以及其基板，该基板包括电性载板、第一金属层及第二金属层。第一金属层形成于电性载板上，第一金属层包括延伸引脚，延伸引脚具有上表面。第二金属层形成于第一金属层上，第二金属层包括接合垫，接合垫重叠于且接触于延伸引脚的上表面，延伸引脚的上表面的一部分露出。接合垫的一部分突出超过延伸引脚的边缘。

Description

半导体封装件以及其基板
技术领域
本实用新型涉及一种封装件及其基板，且特别是涉及一种半导体封装件及其基板。 
背景技术
随着电子产业的蓬勃发展，半导体封装技术不断地进步。一般而言，半导体封装技术是利用导线架承载芯片，并以封胶密封导线架及基板，以避免芯片受潮或因碰撞而损坏。其中，芯片还通过导线架的接垫与外界电性连接，以便于与印刷电路板电性连接。 
然而，导线架的重量较重、体积较大，因此不符合电子产品追求“轻、薄、短、小”的潮流。 
实用新型内容
本实用新型涉及一种半导体封装件及其基板，是以电性接点对外电性连接，故基板及应用其的半导体封装件的厚度较薄，符合电子产品追求“轻、薄、短、小”的潮流。 
根据本实用新型的第一方面，提出一种基板。基板包括电性载板、第一金属层及第二金属层。第一金属层形成于电性载板上，第一金属层包括延伸引脚，延伸引脚具有第一上表面。第二金属层形成于第一金属层上，第二金属层包括接合垫，接合垫重叠于且接触于延伸引脚的第一上表面，延伸引脚的第一上表面的一部分露出。其中，接合垫的一部分突出超过延伸引脚的边缘。 
根据本实用新型的第二方面，提出一种半导体封装件。半导体封装件包括第一金属层、第二金属层、半导体芯片及包封层。第一金属层形成于电性载板上，第一金属层包括延伸引脚，延伸引脚具有第一上表面。第二金属层形成于第一金属层上，第二金属层包括接合垫，接合垫重叠于且接触于延伸引脚的第一上表面，延伸引脚的第一上表面的一部分露出。其中，接合垫的 一部分突出超过延伸引脚的边缘。半导体芯片，是透过多个第一连接元件电性连接于接合垫。包封层包覆第一金属层、第二金属层及半导体芯片，其中，延伸引脚的第一下表面露出。 
为了对本实用新型的上述及其他方面有更佳的了解，下文特举实施例，并配合附图，作详细说明如下： 
附图说明
图1绘示依照本实用新型实施例的基板的剖视图。 
图2绘示图1中延伸引脚及接合垫的俯视图。 
图3绘示依照本实用新型另一实施例中延伸引脚及接合垫的俯视图。 
图4绘示依照本实用新型再一实施例的延伸引脚及接合垫的俯视图。 
图5绘示依照本实用新型又一实施例的延伸引脚及接合垫的剖视图。 
图6绘示图1的芯片座及限位部的俯视图。 
图7A绘示绘示图1的基板的俯视图。 
图7B绘示图7A中沿方向7B-7B’的剖视图。 
图8绘示依照本实用新型实施例的半导体封装件的剖视图。 
图9绘示图8的半导体封装件形成有焊球的剖视图。 
图10A至图10I，其绘示图1的基板的制造示意图。 
图11绘示绘示图10I的半导体结构在电性载板移除后其包封层的突出墙露出的剖视图。 
图12绘示另一实施例的基板的俯视图。 
附图标记说明 
100：基板                       100a：基板单元区 
100′：半导体封装件             110：电性载板 
110u：上表面                    110r：载板凹部 
120：第一金属层121、221、421：延伸引脚 
121c、122c、131c、221c、231c、421c、431c：中心 
121u、122u、421u：第一上表面    121b、122b：第一下表面 
121s1、121s2、122s、221s1、221s2、421s1：边缘 
122：芯片座                     123：连接框 
130：第二金属层                 131、231、431：接合垫 
131a、132a：突出部                  132：限位部 
132c：延伸轴                        132r：限位凹部 
131u、132u、431u：第二上表面        140：第一表面处理层 
150：第二表面处理层                 160：半导体芯片 
161：第一连接元件                   170：包封层 
170b：第三下表面                    170a：卡合部 
171：封装体                         172、272：突出墙 
180：黏合物                         190：第一光致抗蚀剂层 
190a：引脚开孔                      190b：芯片座开孔 
190c、191c：部分                    191：第二光致抗蚀剂层 
191a：接垫开孔                      193：焊球 
D1：第一距离                        D2：第二距离 
D3：第三距离                        D4：第四距离 
具体实施方式
请参照图1，其绘示依照本实用新型实施例的基板的剖视图。基板100包括电性载板110、第一金属层120、第二金属层130、第一表面处理层140及第二表面处理层150。 
第一金属层120的材料及第二金属层130的材料可分别选自于铜或镍。第一金属层120形成于电性载板110的上表面110u上，第一金属层120包括至少一延伸引脚121及至少一芯片座122，延伸引脚121具有相对的第一上表面121u与第一下表面121b。 
第二金属层130形成于第一金属层120上。第二金属层130包括至少一接合垫131及至少一限位部132。接合垫131重叠于且接触于延伸引脚121的第一上表面121u，延伸引脚121的第一上表面121u的一部分露出，亦即该部分未被第二金属层130覆盖。 
如图1所示，第一金属层120与第二金属层130可构成导线架结构，电性载板110承载该导线架结构。其中延伸引脚121例如是外引脚，而接合垫131例如是内引脚。透过该导线架结构的内、外引脚，可使半导体元件(例如是图8的半导体芯片160)与外部电路电性沟通。此外，该导线架结构可以是电镀结构层，其厚度甚薄，可缩小基板100或半导体封装件100’(绘示 于图8)的厚度。 
第一表面处理层140及第二表面处理层150可以是单层结构或多层结构。第一表面处理层140形成于电性载板110与第一金属层120之间。第二表面处理层150形成于第二金属层130的第二上表面(如接合垫131的第二上表面131u及限位部132的第二上表面132u)上。第一表面处理层140的材料及第二表面处理层150的材料可分别选自于金、钯、镍、铜、锡或银。 
请参照图2，其绘示图1中延伸引脚及接合垫的俯视图。优选但非限定地，接合垫131的第二上表面131u的面积小于延伸引脚121的第一上表面121u的面积，如此可减少第二表面处理层150(其对应第二上表面131u及132u形成)中贵重金属(例如是金)的用量。此外，由于接合垫131的第二上表面131u的面积小于延伸引脚121的第一上表面121u的面积，故可露出更多延伸引脚121的第一上表面121u的面积，如此可提升包封层170(绘示于图8)、第一金属层120与第二金属层130的结合性。 
请继续参照图2，延伸引脚121的中心121c与对应的接合垫131的中心131c错开第一距离D1。此外，中心121c例如是延伸引脚121的第一上表面121u的几何中心，而中心131c例如是接合垫131的第二上表面131u的几何中心。此外，第一金属层120与第二金属层130形成至少一段差特征，可提升包封层170(绘示于图8)、第一金属层120与第二金属层130间的结合性。进一步地说，第一金属层120与第二金属层130往侧向错开距离且延伸引脚121的第一上表面121u与接合垫131的第一上表面131u间隔段差距离而使第一金属层120与第二金属层130形成段差结构，该段差结构与包封层170(绘示于图8)可彼此卡合或锚合，因此可提升包封层170、第一金属层120与第二金属层130之间的结合性。 
请参照图3，其绘示依照本实用新型另一实施例中延伸引脚及接合垫的俯视图。延伸引脚421的边缘421s1例如是朝向芯片座122的侧面。优选但非限定地，接合垫431的第二上表面431u的面积小于延伸引脚421的第一上表面421u的面积。延伸引脚421的中心421c与对应的接合垫431的中心431c错开第一距离D1。优选但非限定地，接合垫431的中心431c与延伸引脚421重叠，可使接合垫431稳固地形成于延伸引脚421上。 
请参照图4，其绘示依照本实用新型再一实施例的延伸引脚及接合垫的俯视图。延伸引脚221的中心221c与对应的接合垫231的中心231c实质上 重合。在此情况下，接合垫231的相对二端可突出超过延伸引脚221的相对二边缘221s1及221s2。 
虽然接合垫131的突出部131a(绘示于图1)突出超过延伸引脚121的边缘121s1，其中边缘121s1例如是朝向芯片座122的侧面。然于其它实施例中，接合垫亦可仅突出超过延伸引脚的另一相对边缘。以下以图5举例说明。 
请参照图5，其绘示依照本实用新型又一实施例的延伸引脚及接合垫的剖视图。接合垫131突出超过延伸引脚121的边缘121s2，其中边缘121s2相对于边缘121s1。本实施例中，边缘121s2及边缘121s1为接合垫131的相对二外侧面。 
请参照图6，其绘示图1的芯片座及限位部的俯视图。芯片座122具第一上表面122u。第二金属层130的限位部132沿着芯片座122的周边设置且具有第二上表面132u。其中，芯片座122的周边被限位部132覆盖，而芯片座122的第一上表面122u的一部分露出。优选但非限定地，限位部132的第二上表面132u的面积小于对应的芯片座122的第一上表面122u的面积，如此可减少第二表面处理层150(其对应第二上表面131u及132u形成)中贵重金属(例如是金)的用量。此外，由于限位部132的第二上表面132u的面积小于对应的芯片座122的第一上表面122u的面积，露出更多的芯片座122的第一上表面122u的面积，可提升包封层170(如图8)、第一金属层120与第二金属层130的结合性。 
限位部132的突出部132a突出超过芯片座122的边缘122s(突出部132a亦绘示于图1)。此外，芯片座122的中心122c与对应的限位部132的延伸轴错开第二距离D2。其中，中心122c例如是芯片座122的几何中心。 
第一金属层120的第一上表面的一部分露出而形成芯片设置面。进一步地说，限位部132定义至少一限位凹部132r，限位凹部132r露出芯片座122的第一上表面122u。限位部132例如是接地环(ground ring)，其环绕出限位凹部132r；或者，在实施示例中，限位部132包括数个块体，该多个块体分离配置而围绕出限位凹部132r，或该多个块体彼此连接在一起且围绕出限位凹部132r。 
请参照图7A及图7B，图7A绘示绘示图1的基板的俯视图，图7B绘示图7A中沿方向7B-7B’的剖视图。电性载板110还包括载板凹部110r，载 板凹部110r可环绕整个电性载板110的周边。实施例中，亦可省略载板凹部110r。 
请参照图8，其绘示依照本实用新型实施例的半导体封装件的剖视图。半导体封装件100’包括第一金属层120、第二金属层130、第一表面处理层140、第二表面处理层150、半导体芯片160及包封层170。 
半导体芯片160设于芯片座122上。当半导体芯片160的数量为二个或二个以上时，芯片座122的数量可与半导体芯片160的数量相同；或者，多个半导体芯片160亦可设于单个芯片座122上。 
半导体芯片160被定位于限位凹部132r内且透过粘合物180设于芯片座122的第一上表面122u上，其中黏合物180设于限位部132的限位凹部132r内。由于限位凹部132r的设计，使粘合物180不致溢流至邻近的半导体芯片或不致溢流至芯片座122外，可维持半导体封装件100’的可靠性。此处的粘合物180例如是粘胶或粘贴膜。 
半导体芯片160透过至少一第一连接元件161电性连接于接合垫131。其中第一连接元件161例如是金线(gold wire)，第一连接元件161连接半导体芯片160与第二表面处理层150，以电性连接于半导体芯片160与接合垫131。 
虽然图8未绘示，然其它实施例中，至少一第二连接元件可连接半导体芯片160与限位部132。其中第二连接元件例如是金线。 
包封层170的材料可包括酚醛基树脂(Novolac-based resin)、环氧基树脂(epoxy-based resin)、硅基树脂(silicone-based resin)或其他适当的包覆剂。包封层170的材料亦可包括适当的填充剂，例如是粉状的二氧化硅。在本实施例中，优选但非限定地，包封层170例如是封胶(molding compound)。包封层170包覆第一金属层120、第二金属层130及半导体芯片160，其中第一表面处理层140从包封层170露出。其它实施例中，半导体封装件100’可省略第一表面处理层140，在此情况下，延伸引脚121的第一下表面121b及芯片座122的第一下表面122b从包封层170露出。无论是第一表面处理层140或第一金属层120露出，半导体封装件100’都能透过第一表面处理层140及/或第一金属层120设置于外部电路板，以电性连接外部电路板。此外，无论是第一表面处理层140或第一金属层120露出，半导体封装件100’的热量可透过第一表面处理层140及/或第一金属层120快速地散逸至外界。 
请参照图9，其绘示图8的半导体封装件形成有焊球的剖视图。图9的半导体封装件还包括至少一焊球193，焊球193设于延伸引脚121或第一表面处理层140上。半导体封装件可透过焊球193设置于外部电路板上。 
此外，包封层170具有至少一卡合部170a，其位于芯片座122与延伸引脚121之间。由于接合垫131的突出部131a突出超过延伸引脚121的边缘的设计，使突出部131a抵靠于卡合部170a上，接合垫131因此更稳固设于延伸引脚121上。此外，由于突出部131a的突出外形，接合垫131与延伸引脚121坚固地锚合于包封层170中，而不容易与包封层170脱离且可提升半导体封装件100’的可靠度。相似地，由于限位部132的突出部132a突出超过芯片座122的边缘的设计，使突出部132a抵靠于卡合部170a上，限位部132因此更稳固设于芯片座122上。此外，由于限位部132的突出外形，不容易脱离且可提升半导体封装件100’的可靠度。 
以下说明依照本实用新型实施例的基板的制造方法。以图1的基板100的制造方法为例，请参照图10A至图10I，其绘示图1的基板的制造示意图。 
于图10A中，提供电性载板110，电性载板110具有上表面110u。电性载板110例如是单层或多层结构。以多层结构来说，电性载板110可包括内层及外披覆层。内层例如是钢，而外披覆层的材料包括铜(Cu)或铜合金。相较于铜，钢与后续形成的包封层170的热膨胀系数甚接近，使半导体封装件100’(如图8)或基板100(如图1)的翘曲量减少。优选但非限定地，电性载板110的热膨胀系数介于约10至15ppm/℃(或10-6/℃)之间，其接近包封层170的热膨胀系数。由于半导体封装件100’或基板100的翘曲量减少，可容许基板100的面积增大，在此情况下，可形成更多数量的半导体封装件100’。 
此外，电性载板110定义至少一基板单元区100a，在后续的切割狭缝的形成步骤中，对应基板单元区100a的范围切割，即可形成至少一基板或至少一半导体封装件。此外，为更清楚表示结构特征，图10C至图10I仅绘示出单个基板单元区100a内的结构。 
然后，以例如是层压(lamination)、印刷(screen-printing)或旋涂(spin-coating)，形成第一光致抗蚀剂层190覆盖电性载板110的上表面110u。 
如图10B所示，以例如光刻工艺(photolithography)，形成至少一引脚 开孔190a于第一光致抗蚀剂层，以露出电性载板110。 
如图10B所示，以例如光刻工艺，形成至少一芯片座开孔190b于第一光致抗蚀剂层190。引脚开孔190a及芯片座开孔190b可于同一工艺中同时或分别形成，或于不同工艺中分别形成。 
如图10C所示，以例如是电解电镀(electrolytic plating)，形成第一表面处理层140于电性载板110的上表面110u上。在其它实施例中，亦可省略第一表面处理层140；或者，第一表面处理层140可于电性载板110移除后形成(请参照后续说明图12的内容)。 
如图10C所示，邻近电性载板110的上表面110u形成第一金属层120，本实施例中，第一金属层120形成于电性载板110上的第一表面处理层140上表面上。其它实施例中，在省略第一表面处理层140的情况下，第一金属层120形成于电性载板110的上表面110u上。 
第一金属层120包括至少一延伸引脚121及至少一芯片座122。延伸引脚121形成于第一光致抗蚀剂层190的引脚开孔190a内且具有第一上表面121u。芯片座122形成于第一光致抗蚀剂层190的芯片座开孔190b内且具有第一上表面122u。 
如图10D所示，以例如是层压形成第二光致抗蚀剂层191覆盖第一光致抗蚀剂层190。 
请继续参照图10D，以例如是光刻工艺，形成至少一接垫开孔191a于第二光致抗蚀剂层191上，延伸引脚121的第一上表面121u及芯片座122的第一上表面122u从接垫开孔191a露出。此外，第一光致抗蚀剂层190的一部分190c从接垫开孔191a露出。 
接垫开孔191a露出延伸引脚121的第一上表面121u及芯片座122的第一上表面122u，使后续形成的接合垫131及限位部132可形成于露出的延伸引脚121及芯片座122上。此外，由于第二光致抗蚀剂层191未覆盖第一光致抗蚀剂层190的该部分190c，故后续形成的突出部131a及132a(绘示于图10E)不致受到第一光致抗蚀剂层190的阻挡，而可分别突出于延伸引脚121的边缘121s1及芯片座122的边缘122s延伸至形成于该部分190c上。实施例中，第二光致抗蚀剂层191可覆盖第一光致抗蚀剂层190的该部分190c的局部(例如是该部分190c的中间或该部分190c的二端以外的部分)，如此不影响突出部131a及132a的形成。此外，透过接垫开孔191a的尺寸 及位置设计，可控制接合垫131及限位部132的边缘位置以及突出部131a及132a的延伸方向。 
第二光致抗蚀剂层191覆盖部份的延伸引脚121，使形成后的接合垫131的第二上表面131u的面积小于延伸引脚121的第一上表面121u的面积。 
第一光致抗蚀剂层190的引脚开孔190a的中心与对应的第二光致抗蚀剂层191的接垫开孔191a的中心错开第三距离D3。第一光致抗蚀剂层190的芯片座开孔190b的中心与第二光致抗蚀剂层191的对应的接垫开孔191a错开第四距离D4。 
此外，第二光致抗蚀剂层191的一部分191c可对应芯片座122的中心区域设置，如此可使后续形成的限位部132设于芯片座122的周边或使限位部132的几何中心(未绘示)与芯片座122的中心122c(中心122c绘示于图6)实质上重合。 
如图10E所示，以例如是电解电镀(electrolytic plating)，形成第二金属层130。第二金属层130包括至少一接合垫131及至少一限位部132。 
接合垫131及限位部132形成于露出的延伸引脚121及芯片座122上。接合垫131形成于第二光致抗蚀剂层191的接垫开孔191a内且具有第二上表面131u。接合垫131重叠于且接触于延伸引脚121的第一上表面121u。其中，接合垫131的第二上表面131u的面积可小于对应的延伸引脚121的第一上表面121u的面积。 
限位部132形成于第二光致抗蚀剂层191的接垫开孔191a内且沿着芯片座122的周边设置以及具有第二上表面132u。其中，限位部132的第二上表面132u的面积可小于对应的芯片座122的第一上表面122u的面积。限位部132定义至少一限位凹部132r，限位凹部132r露出芯片座122的第一上表面122u。 
接合垫131形成后，延伸引脚121的中心121c与对应的接合垫131的中心131c错开第一距离D1(第一距离D1绘示于图2)。相似地，限位部132形成后，芯片座122的中心122c与对应的限位部132的延伸轴132c错开第二距离D2(第二距离D2绘示于图1及图6)。 
在电镀过程中，电镀层会往延伸引脚121及芯片座122的边缘之外的方向形成，在此情况下，接合垫131的突出部131a突出超过延伸引脚121的边缘121s1，而限位部132的突出部132a突出超过芯片座122的边缘122s。 
接合垫131的突出部131a的突出量约10至80微米(um)，此突出量不致影响对第一光致抗蚀剂层190及第二光致抗蚀剂层191的移除，即，第一光致抗蚀剂层190及第二光致抗蚀剂层191可完整地被移除，并不受突出部131a的影响。相似地，限位部132的突出部132a的突出量约10至80微米(um)，此突出量不致影响对第一光致抗蚀剂层190及第二光致抗蚀剂层191的移除，即，第一光致抗蚀剂层190及第二光致抗蚀剂层191可完整地被移除，并不受突出部132a的影响。 
接合垫131的突出部131a及限位部132的突出部132a并不受限于往单边延伸。在另一实施例中，接合垫131的突出部131a及/或限位部132的突出部132a亦可往双边或多边突出地延伸，以形成如同”香菇头”或”T字型”的结构。此外，突出部131a及突出部132a的尺寸依据电镀时间、电流或电压而定，本实用新型不做任何限制。 
请继续参照图10E，以例如是电解电镀(electrolytic plating)，形成第二表面处理层150于第二金属层130上，例如第二表面处理层150覆盖接合垫131及限位部132。在其它实施例中，亦可省略第二表面处理层150。此外，可采用例如是光刻工艺，形成较小面积的第二表面处理层150，此较小面积的第二表面处理层150未覆盖整个第二金属层130。 
如图10F所示，以例如是化学除膜，移除第一光致抗蚀剂层190及第二光致抗蚀剂层191。至此，形成如图1所示的基板100。第一光致抗蚀剂层190及第二光致抗蚀剂层191移除后，延伸引脚121的第一上表面121u的一部分露出。 
以下说明图8的半导体封装件的制造过程。以下是从移除第一光致抗蚀剂层190及第二光致抗蚀剂层191后开始说明。 
如图10G所示，设置至少一半导体芯片160于芯片座122上。其中，半导体芯片160定位于限位凹部132r内并透过黏合物180固设于芯片座122的第一上表面122u上。 
如图10G所示，以例如是引线技术，以数个第一连接元件161电性连接半导体芯片160与接合垫131。第一连接元件161连接半导体芯片160与第二表面处理层150或接合垫131(在省略第二表面处理层150的情况下)。虽然图未绘示，然第一连接元件161亦可连接半导体芯片160与限位部132；或者，第一连接元件161以外的数个第二连接元件(未绘示)可连接半导体 芯片160与限位部132。第二连接元件可同样以引线技术形成。 
如图10H所示，以例如是封装技术，形成包封层170至少包覆第一金属层120、第二金属层130及半导体芯片160。此外，包封层170还包覆第一连接元件161、黏合物180、第一表面处理层140、第二表面处理层150及电性载板110的上表面110u。可利用数种封装技术的一种形成包封层，例如是压缩成型(compression molding)、注射成型(injection molding)或转注成型(transfer molding)。 
实施例中，形成包封层170之前，可对第一金属层120及第二金属层130露出的表面进行化学处理或表面洁净处理，以提升第一金属层120及第二金属层130与包封层170间的结合性。 
如图10I所示，以例如是化学蚀刻，移除电性载板110，其中第一表面处理层140及包封层170的第三下表面170b露出。第一表面处理层140的露出面与包封层170的第三下表面170b实质上齐平或凹入。在省略第一表面处理层140的情况下，延伸引脚121的第一下表面121b露出。 
请参照图11，其绘示图10I的半导体结构在电性载板移除后其包封层的突出墙露出的剖视图。包封层170包括封装体171与突出墙172，封装体171包覆第一金属层120、第二金属层130、第一表面处理层140、第二表面处理层150及半导体芯片160。突出墙172突出于封装体171的第三下表面170b形成，使封装体171相对于突出墙172如同包封层170的凹入结构。第一金属层的下表面，例如是延伸引脚121中露出的第一下表面121b及/或第一表面处理层140的下表面，其往包封层170的内部凹陷。于电性载板110移除后，包封层170的突出墙172露出。突出墙172的外形及位置对应电性载板110的载板凹部110r(绘示于图7B)，因此突出墙172可以是环状突出结构，或是包括数个分离配置的突出块。突出墙172可强化其半导体结构的整体强度。当半导体结构的厚度少于0.5mm时，突出墙172有效增加半导体封装件的强度，使半导体封装件可朝向薄封装件的趋势设计。 
另一实施例中，突出墙亦可形成于半导体封装件的包封层的上侧。透过于封装模具的沟槽设计，其中沟槽对应半导体封装件的包封层的上侧，使包封层形成后，突出墙对应形成。在此设计下，电性载板可选择性地省略载板凹部。 
然后，可形成如图9所示的焊球193于延伸引脚121或第一表面处理层 140上。 
然后，以例如是激光或刀具，切割如图10I所示的半导体封装结构，以形成至少一如图8或图9所示的半导体封装件100’。在切割工艺中，图11的突出墙172可被切除。 
此外，当要使用具有载板凹部的电性载板时，制造方法还包括：以例如是化学蚀刻或机械切削，在图10A所示的电性载板110中形成至少一载板凹部110r。其中，载板凹部110r可环绕整个电性载板110的周边。 
请参照图12，其绘示另一实施例的基板的俯视图。形成于电性载板110上的第一金属层120还包括连接框123。连接框123连接所有的延伸引脚121及所有的芯片座122，使所有的延伸引脚121及所有的芯片座122透过连接框123电性连接。如此一来，第一表面处理层140可于电性载板110移除后通过电镀工艺形成。进一步地说，由于延伸引脚121及芯片座122透过连接框123电性连接，故只要将电镀设备的电极(未绘示)连接于连接框123，则可一次形成第一表面处理层140于延伸引脚121的第一下表面121b(绘示于图10I)及芯片座122第一下表面122b(绘示于图10I)上。在后续的切割工艺中，可沿基板单元区100a的边界切割基板100，如此可电性隔离延伸引脚121与芯片座122。在此实施例中，切割后的基板100的延伸引脚121的外侧面与包封层170的外侧面实质上齐平，即共面。 
本实用新型上述实施例的半导体封装件及其基板，具有数个特征，以下举出其中几个说明： 
(1).包封层具有至少一卡合部，接合垫及限位部抵靠于卡合部上，使接合垫及限位部更稳固地设置。 
(2).由于接合垫的突出部及限位部的突出部的设计，使接合垫131与延伸引脚121和限位部132与芯片座122不容易与包封层脱离且可提升半导体封装件的可靠度。 
(3).由于限位凹部的设计，使粘合物不致溢流至邻近的半导体芯片或不致溢流至芯片座外，可维持半导体封装件的可靠性。 
(4).第一金属层及第二金属层可构成导线架结构，导线架结构可以是电镀结构层，其厚度甚薄，可缩小基板及半导体封装件的厚度。 
(5).包封层具有至少一突出墙。突出墙可强化半导体封装件在制造过程及操作过程中的结构强度，以减少翘曲量。 
(6).钢制材料的电性载板与后续形成的包封层的热膨胀系数甚接近，使半导体封装件或基板的翘曲量减少。 
综上所述，虽然本实用新型已以至少一实施例披露如上，然其并非用以限定本实用新型。本实用新型所属技术领域中普通技术人员，在不脱离本实用新型的精神和范围内，当可作各种的更动与润饰。因此，本实用新型的保护范围当视权利要求所界定为准。 

Claims (21)

1.一种基板，其特征在于，包括：
电性载板；
第一金属层，形成于该电性载板上，该第一金属层包括延伸引脚，该延伸引脚具有第一上表面；以及
第二金属层，形成于该第一金属层上，该第二金属层包括接合垫，该接合垫重叠于且接触于该延伸引脚的该第一上表面，该延伸引脚的该第一上表面的一部分露出；
其中，该接合垫的一部分突出超过该延伸引脚的边缘。
2.如权利要求1所述的基板，其特征在于，该延伸引脚的中心与对应的该接合垫的中心错开第一距离。
3.如权利要求1所述的基板，其特征在于，该接合垫具有第二上表面，该接合垫的该第二上表面的面积小于该延伸引脚的该第一上表面的面积。
4.如权利要求1所述的基板，其特征在于，该第一金属层还包括芯片座，该芯片座具有第一上表面；该第二金属层还包括限位部，该限位部沿着该芯片座的周边设置且具有第二上表面；
其中，该芯片座的该第一上表面的一部分露出，该限位部的该第二上表面的面积小于该对应的该芯片座的该第一上表面的面积，该限位部的一部分突出超过该芯片座的边缘。
5.如权利要求4所述的基板，其特征在于，该芯片座的中心与对应的该限位部的延伸轴错开第二距离。
6.如权利要求4所述的基板，其特征在于，该限位部定义限位凹部，该限位凹部露出该芯片座的该第一上表面。
7.如权利要求4所述的基板，其特征在于，该限位部为接地环。
8.如权利要求1所述的基板，其特征在于，该第二金属层具有第二上表面，该基板还包括：
第一表面处理层，形成于该电性载板与该第一金属层之间；以及
第二表面处理层，形成于该第二金属层的该第二上表面。
9.如权利要求8所述的基板，其特征在于，该电性载板还包括载板凹部，该载板凹部环绕于基板单元区的周边或环绕于呈阵列排列的多个该基板单 元区的周边。
10.如权利要求1所述的基板，其特征在于，该电性载板的热膨胀系数介于10至15ppm/℃之间，该电性载板包括内层及外披覆层，该外披覆层为铜层。
11.一种半导体封装件，其特征在于，包括：
第一金属层，形成于该电性载板上，该第一金属层包括延伸引脚，该延伸引脚具有相对的第一上表面与第一下表面；以及
第二金属层，形成于该第一金属层上，该第二金属层包括接合垫，该接合垫重叠于且接触于该延伸引脚的该第一上表面，该延伸引脚的该第一上表面的一部分露出，其中，该接合垫的一部分突出超过该延伸引脚的边缘；
半导体芯片，透过多个第一连接元件电性连接于该接合垫；
包封层，包覆该第一金属层、该第二金属层及该半导体芯片，其中，该延伸引脚的该第一下表面露出。
12.如权利要求11所述的半导体封装件，其特征在于，该延伸引脚的中心与对应的该接合垫的中心错开第一距离。
13.如权利要求11所述的半导体封装件，其特征在于，该接合垫具有第二上表面，该接合垫的该第二上表面的面积小于该延伸引脚的该第一上表面的面积。
14.如权利要求11所述的半导体封装件，其特征在于，该第一金属层还包括芯片座，该芯片座具有第一上表面；该第二金属层还包括限位部，该限位部沿着该芯片座的周边设置且具有第二上表面；
其中，该芯片座的该第一上表面的一部分露出，该限位部的该第二上表面的面积小于该对应的该芯片座的该第一上表面的面积，该限位部的一部分突出超过该芯片座的边缘。
15.如权利要求14所述的半导体封装件，其特征在于，该芯片座的中心与对应的该限位部的延伸轴错开第二距离。
16.如权利要求14所述的半导体封装件，其特征在于，该限位部定义限位凹部，该限位凹部露出该芯片座的该第一上表面。
17.如权利要求16所述的半导体封装件，其特征在于，该半导体芯片定位于该限位凹部内且透过黏合物设于该芯片座的该第一上表面上；
其中，该黏合物设于该限位部的该限位凹部内。 
18.如权利要求14所述的半导体封装件，其特征在于，该限位部为接地环；该半导体芯片透过多个第二连接元件电性连接于该接地环。
19.如权利要求11所述的半导体封装件，其特征在于，该第二金属层具有第二上表面，该基板还包括：
第一表面处理层，形成于该电性载板与该第一金属层之间；以及
第二表面处理层，形成于该第二金属层的该第二上表面。
20.如权利要求11所述的半导体封装件，其特征在于，该延伸引脚中露出的该第一下表面往该包封层的内部凹陷。
21.如权利要求11所述的半导体封装件，其特征在于，该包封层还包括：
突出墙，环绕于基板单元区的周边或环绕于呈阵列排列的多个该基板单元区的周边。 
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