CN113793810A - 一种芯片防溢胶封装方法和封装结构 - Google Patents
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Abstract
本发明公开了一种芯片防溢胶封装方法,包括如下步骤,1)将一圈胶圈设置到所述基岛上;2)在所述基岛上位于所述胶圈中间的位置涂布银胶;3)将所述芯片放置在所述基岛上位于所述胶圈内的位置;4)焊接金线;5)塑封。由于胶圈的作用,银胶会被限制在胶圈的范围内,这样银胶就不会溢出到基岛外,避免基岛与引脚之间发生粘接。
Description
技术领域
本发明涉及一种芯片防溢胶封装方法和封装结构。
背景技术
参见图1,图1中展示了芯片封装时的一个步骤,就是将晶片100通过银胶101粘贴在铜排102上。步骤中需要先在铜排102中间的基岛103上涂上银胶101,然后再将晶片100覆盖在基岛103上。这个步骤中,由于基岛顶部是一个平面,因此银胶很容易就溢出基岛表面,导致基岛与引脚104之间通过银胶粘接。参见图2,在后续金线105焊接过程中,金线与引脚的焊接点可能收到溢出的银胶的影响,因此有必要予以改进。
发明内容
针对现有技术中存在的不足,本发明提供了一种芯片防溢胶封装方法,可以有效避免基岛上的银胶溢出。
本发明的另一目的是提供一种芯片防溢胶封装结构,可以避免银胶溢出。
为了解决上述问题,本发明采用的技术方案为:一种芯片防溢胶封装方法,包括如下步骤,1)将一圈胶圈设置到所述基岛上;2)在所述基岛上位于所述胶圈中间的位置涂布银胶;3)将所述芯片放置在所述基岛上位于所述胶圈内的位置;4)焊接金线;5)塑封。由于胶圈的作用,银胶会被限制在胶圈的范围内,这样银胶就不会溢出到基岛外,避免基岛与引脚之间发生粘接。
上述技术方案中,优选的,步骤1)中所用的胶圈的材料与步骤5)中塑封所用材料相同。 材料相同,在后续塑封过程中,胶圈可以与塑封料合为一体,芯片封装后整体性状都与一般的芯片无异。
上述技术方案中,优选的,所述胶圈上设置有胶水,所述胶圈通过胶水粘附在基岛上。这样可以防止胶圈在基岛上的位置发生变动。
上述技术方案中,优选的,所述胶圈的材料为环氧树脂胶圈。
芯片防溢胶封装结构,包括铜排,所述铜排上设置有基岛和位于所述基岛周圈的引脚,所述基岛的顶面上设置有胶圈,所述胶圈内设置有银胶,所述银胶上方为晶片,所述晶片外圈为塑封料形成的外壳。在基岛顶部设置胶圈,可以将银胶限定在基岛和胶圈形成的空间内,防止银胶溢出。
上述技术方案中,优选的,所述塑封料和所述胶圈的材料相同。材料相同,在后续塑封过程中,胶圈可以与塑封料合为一体,芯片封装后整体性状都与一般的芯片无异。
上述技术方案中,优选的,所述塑封料和所述胶圈的材料为环氧树脂。
本发明具有如下有益效果:由于胶圈的作用,银胶会被限制在胶圈的范围内,这样银胶就不会溢出到基岛外,避免基岛与引脚之间发生粘接。
附图说明
图1为现有芯片设置晶片时的示意图。
图2为现有芯片焊接金线时的示意图。
图3为本发明一个实施例封装第一步的示意图。
图4为本发明一个实施例封装第二步的示意图。
图5为本发明一个实施例封装第三步的示意图。
图6为本发明一个实施例片封装第四步的示意图。
图7为本发明一个实施例封装第五步的示意图。
图8为本发明另一个实施例封装完成的芯片示意图。
具体实施方式
下面结合附图与具体实施方式对本发明作进一步详细描述:
实施例1,参见图3-7,一种芯片防溢胶封装方法,参见图3至7,包括如下步骤,
1)将一圈胶圈2设置到所述基岛11上,胶圈2的材料为环氧树脂,胶圈上设置有胶水,胶圈2通过胶水与基岛11相连。胶水的存在,可以将胶圈的位置固定,这样可以防止胶圈在基岛上的位置发生变动。
2)在所述基岛11上位于所述胶圈2中间的位置涂布银胶3。
3)将晶片4放置在所述基岛11上位于所述胶圈2内的位置。
4)焊接金线5,金线5的第一点焊接在晶片4上,金线5的第二点焊接在引脚12上。
5)塑封,在晶片4外封装一圈环氧树脂,形成芯片的外壳6,这就完成了芯片的封装。塑封所用的材料和胶圈的材料相同,胶圈可以与塑封料合为一体,芯片封装后整体性状都与一般的芯片无异。
由于胶圈的作用,银胶会被限制在胶圈的范围内,这样银胶就不会溢出到基岛外,避免基岛与引脚之间发生粘接。
实施例1,参见图7,芯片防溢胶封装结构,包括铜排1,所述铜排1上设置有基岛11和位于所述基岛11周圈的引脚12,所述基岛11的顶面上设置有胶圈2,所述胶圈2内设置有银胶3,所述银胶3上方为晶片4,所述晶片3外圈为塑封料形成的外壳6。
在基岛顶部设置胶圈,可以将银胶限定在基岛和胶圈形成的空间内,防止银胶溢出。所述塑封料和所述胶圈的材料相同。材料相同,在后续塑封过程中,胶圈可以与塑封料合为一体,芯片封装后整体性状都与一般的芯片无异。
实施例2,参见图8,芯片防溢胶封装结构,所述基岛11的厚度小于所述引脚12的厚度。其余同实施例1,芯片的厚度等于基岛的厚度加上晶片的厚度再加上晶片顶部与塑封的距离,由于基岛上与晶片相接触区域的厚度小于所述引脚的厚度,因此相比于以前整块铜排都一个厚度,我们芯片的厚度可以降低。对基岛进行减薄处理,可以在确保铜排整体强度的同时,让晶片与引脚之间的高度差大大减少,因此也可以减少金线的用量,降低芯片封装的成本。
Claims (8)
1.一种芯片防溢胶封装方法,其特征在于,包括如下步骤,
1)将一圈胶圈设置到所述基岛上;
2)在所述基岛上位于所述胶圈中间的位置涂布银胶;
3)将所述芯片放置在所述基岛上位于所述胶圈内的位置;
4)焊接金线;
5)塑封。
2.根据权利要求1所述的一种芯片防溢胶封装方法,其特征在于:步骤1)中所用的胶圈的材料与步骤5)中塑封所用材料相同。
3.根据权利要求1所述的一种芯片防溢胶封装方法,其特征在于:所述胶圈上设置有胶水,所述胶圈通过胶水粘附在基岛上。
4.根据权利要求1所述的一种芯片防溢胶封装方法,其特征在于:所述胶圈的材料为环氧树脂胶圈。
5.用于如权利要求1所述的芯片防溢胶封装结构,其特征在于:包括铜排,所述铜排上设置有基岛和位于所述基岛周圈的引脚,所述基岛的顶面上设置有胶圈,所述胶圈内设置有银胶,所述银胶上方为晶片,所述晶片外圈为塑封料形成的外壳。
6.根据权利要求5所述的一种芯片防溢胶封装结构,其特征在于:所述塑封料和所述胶圈的材料相同。
7.根据权利要求6所述的一种芯片防溢胶封装结构,其特征在于:所述塑封料和所述胶圈的材料为环氧树脂。
8.根据权利要求5所述的一种芯片防溢胶封装结构,其特征在于:所述基岛的厚度小于所述引脚的厚度。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115621212A (zh) * | 2022-11-07 | 2023-01-17 | 合肥矽迈微电子科技有限公司 | 一种防溢的封装结构及其装片方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW543922U (en) * | 2002-10-09 | 2003-07-21 | Taiwan Ic Packaging Corp | Ultra-thin type semiconductor device package structure |
US20090224384A1 (en) * | 2008-03-07 | 2009-09-10 | Chipmos Technologies Inc. | Chip package |
US20110267789A1 (en) * | 2010-04-28 | 2011-11-03 | Advanpack Solutions Pte Ltd. | Etch-back type semiconductor package, substrate and manufacturing method thereof |
CN205177808U (zh) * | 2015-11-18 | 2016-04-20 | 上海兆芯集成电路有限公司 | 芯片封装结构 |
-
2021
- 2021-09-22 CN CN202111108852.9A patent/CN113793810A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW543922U (en) * | 2002-10-09 | 2003-07-21 | Taiwan Ic Packaging Corp | Ultra-thin type semiconductor device package structure |
US20090224384A1 (en) * | 2008-03-07 | 2009-09-10 | Chipmos Technologies Inc. | Chip package |
US20110267789A1 (en) * | 2010-04-28 | 2011-11-03 | Advanpack Solutions Pte Ltd. | Etch-back type semiconductor package, substrate and manufacturing method thereof |
CN205177808U (zh) * | 2015-11-18 | 2016-04-20 | 上海兆芯集成电路有限公司 | 芯片封装结构 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115621212A (zh) * | 2022-11-07 | 2023-01-17 | 合肥矽迈微电子科技有限公司 | 一种防溢的封装结构及其装片方法 |
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