TW200529384A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
TW200529384A
TW200529384A TW094102436A TW94102436A TW200529384A TW 200529384 A TW200529384 A TW 200529384A TW 094102436 A TW094102436 A TW 094102436A TW 94102436 A TW94102436 A TW 94102436A TW 200529384 A TW200529384 A TW 200529384A
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Taiwan
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layer
semiconductor device
semiconductor
aforementioned
scope
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TW094102436A
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English (en)
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TWI261343B (en
Inventor
Koujiro Kameyama
Akira Suzuki
Yoshio Okayama
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Sanyo Electric Co
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Publication of TW200529384A publication Critical patent/TW200529384A/zh
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Publication of TWI261343B publication Critical patent/TWI261343B/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

200529384 九、發明說明： 【發明所屬之技術領域】 本發明係關於—種半導體μ及其製造方法 ==種在半導體基板形成有導通孔（via 導體裝置及其製造方法。 风《牛 【先前技術】 的外：二以一種具有與半導體晶片的外形尺寸大致相同 的外=寸之日日日片尺寸封裝件而言，係以bga(㈣咖 =型：導體裝置為大家所熟知。該bga型半導體裝置 的今严播件的一主面上以格子狀複數配列由録錫等 屬構件所形成之球狀端子，並與形成於封裝件的另-面上之半導體晶片電性連接之裝置。 而且’將該BGA型半導體農置組裝於電子機器時， 错由將各球狀端子壓接於印刷基板上的配線圖案，使半導 體晶片與搭載於印刷基板的外部電路電性連接。
如上述之BGA型半導體裝置，相較於具有由側部突 出之導線銷(lead㈣的s〇P(Smai丨ο— _㈣或 QFP(Quad Flat Packagae)等其他型態的晶片尺寸封裝件， 其可配置多數的球狀端子，並具有可小型化之優點。懸 ，丰導體裝置具有例如：搭載於行動電話之數位照相機之 影像感測晶片的用途。在該例中，係在半導體晶片的一主 面上或兩主面上’黏接有由例如玻璃所構成之支撐基板。 此外’相關技術文獻可例冑以下之專利文獻i。 接著，參照圖式，說明在半導體晶片黏接】片支撑基 316698 5 200529384 * 板而成時之習知例的BGA型半導體裝置及其製造方法。 第5圖至第7圖係顯示可適用於影像感測晶片之習知 例的BGA型半導體裝置及其製造方法的剖視圖。首先， 如第5圖所示，在半導體基板3〇上的表面隔著絕緣膜、例 如氧化膜3 1，形成由鋁層或鋁合金層所構成之銲墊電極層 ，著，在包含銲墊電極層34的半導體基板％表面隔 .者樹脂㉟35，黏接由例如玻璃所構成之支撲基板36。 . 接者，如第ό圖所示，在對應銲墊電極層34的半導體 基板30肖面形成具有開口部的阻劑層η，並以該 阻劑層作為遮罩，對半導體基板3G進行乾触刻，形成由半 導體基板30背面到達銲塾電極層34的導通孔“。在此， 在利用上述蝕刻所形成之導通孔38底部的銲墊電極層Μ 的一部分上，形成有姓刻時所產生之紹氧㈣5^列如 ΑΙ2Ο3化合物）。 之後，如第7圖所示，在包含導通孔38内之半導體基 •板30的背面形成阻障層39。此外，在阻障層％上“ 覆用的晶種層（seedlayer)4〇,並在該晶種層4〇上進行鑛覆 處理’形成由例如銅（Cu)所構成之再配線層41。接著= 再配線層41上形成保護層（未圖示），並於保護層的預定位 置設置開σ並形成與再g己制41接觸之球狀端子a。 之後，雖未圖示，但切斷半導體基板以及疊層於其上 之上述各層，使其分離為各個半導體晶片。藉由該方 形成銲塾電極層34與球狀端子42電性連接之 導體奘罟。 1 ^ 316698 6 200529384 [專利文獻1]日本特許公表2002_512436號公報 【發明内容】 (發明所欲解決之課題） 燕而’利用上述蝕刻形成導通孔3 8時 -可心〜π时，因形成於其底 。之紹氧化物5G係形成於部份之銲墊電極層34上，故使
録墊電極層34與再配線層41之間的電阻形成高電阻。此 外、由於絲化物5G會使銲墊電極層34料配線層Μ 之覆盍性劣化’因此容易使再配線層41產生斷線等損傷。 因而，產生半導體裝置之特性劣化的問題。 、 因此，雖可考慮再度藉由蝕刻等去除該鋁氧化物5〇， 但此時，則由純❹驟增加而產生製程繁複的問題。 因此，本發明係提供不增加蝕刻步驟而能極力抑制♦ 性特性劣化的半導體裝置及其製造方法者。 电 (解決課題之手段） 本％明之半導體裝置係為解決上述問題而研創者，其 特徵為具備：形成於半導體晶片的表面，且疊層有第i阻 障層與鋁層或鋁合金層而成之銲墊電極層；黏接於半導體 =片表面之支撐體；由半導體晶片背面到達第i阻障層的 導通孔；以及形成於包含導通孔内之半導體晶片背面，且 與第1阻障層相連接之再配線層。 此外，本發明之半導體裝置，除上述構成外，其特徵 為：再配線層係以完全或部分埋入導通孔内之方式形成。 此外，本發明之半導體裝置，係上述再配線層藉由鍍 覆處理或濺鑛處理而形成。 316698 7 .200529384 此外，本發明之半導體裝置，其 上形成有導電端子。 ，.在再配線層 此外，本發明之半導體裳置，其特徵為 孔内之半導體晶片背面與再 已δ v通 層。 ，、冉配線層之間形成有第2阻障 此外，本發明之半導體裝置的製造方法， 備.準備具有叠層有第！阻障層與結層或銘合金層:成^ 知塾電極層之半導體基板，並在半導體基 ^成之 體之步驟，·在半導體1 土表面黏接支撐 1阻障層的導诵》丨夕半跡· 達第 其杯= 及在包含導通孔内之半導體 基板月面’形成與第i阻障層相連接之再配線層之_虹 此外，本發明之半導體裝置之製造方法，其特徵’真. 在形成上述再配線層的步驟中，再配線層係邻八 埋入導通孔内之方式形成。 戍口 P刀 /此外，本發明之半導體裝置之製造方法，其特徵為： 在形成再配線層的步驟中’前述再配線層係藉由錄覆處理 或濺鏡處理而形成。 n’本發明之半導體裝置之製造方法除上述步驟 卜/、特啟為：包含在再配線層上形成導電端子之步驟。 此外，本發明之半導體裝置之製造方法除上ς步驟 外’其特徵為：包含在包含導通孔内之半導體基板背面與 再配線層之間，形成第2阻障層之步驟。 、 (發明之效果） 根據本發明之半導體裝置及其製造方法，藉由最 且隹呂 316698 8 200529384 J層或鋁合金層與第1阻障層，形成銲墊電極層。藉此，在 藉由蝕刻形成導通孔時，可避免在位於如習知之導通孔的 底部之銲墊電極層丨，形成鋁氧化物。因而，銲墊電極層 興再配線層之間便不會形成高電阻，而得以極力抑制再配 線層產生斷線等之損傷。結果，可極力抑制因形成上述導 通孔而導致之半導體裝置的電性特性的劣化。此外，亦可 • 省略用以去除鋁氧化物之蝕刻步驟。 ， 【實施方式】 篇i '妾著，參照圖式說明本實施形態之半導體裝置的構 ^第4圖係顯示在本實施形態之半導體裝置中，存在有 後述薛墊電極層的領域之剖面，並顯示在分離為個別 導體晶片前的狀態。 如第4圖所示’在由Si所構成之半導體基板叫之後 分離而形成個別的半導體晶片）的表面上隔著絕緣膜，例如 乳化膜η在第i阻障層12上形成有疊層有紹層13(或銘 t合金層）而成之銲堅電極層14。亦即，第！阻障層P係形 成較為接近半導體基板10的層。 ^ “此外在半導體基板丨〇上形成未圖示之電路，而銲墊 電極層14係與上述電路電性連接。上述未圖示之電路係形 ^為例如CCD(Charge Coupled Device)影像感測器。此 由於必須要有成$ CCD影像（畫像）的基準點之光學/ =色區域（〇PHCal black)，因此，構成銲塾電極層Μ之紹 « 13’最好為由可將光線（紅外線）遮蔽之純㈣構成，亦 可為AM：u層。或者，最好為包含穿透紅外線㈣⑻的 316698 9 .200529384 合金（例如Al-Si、Al-Si-Cu等）以外的金屬。 此外’第1阻障層12最好為例如氮化鈦⑽)層。或 者’第1阻障層12只要為高炫點金屬層或其化合物層，亦 可為減化鈦金屬所構成之轉層，亦可為组（Ta) 層、鈦鎢層（TiW)層及氮化钽（TaN)層等。 此外，在半導體基板10的表面上隔著樹脂们5(具有 黏接劑的功能），黏接有由例如可透過預定波長帶之光的玻 蠱璃所形成的支撐基板16。然後，在半導體基板1〇中，在 ’存在有銲墊電極層14的區域，係形成有由半導體基板1〇 背面到達銲墊電極層14之第！阻障層12的導通孔以。之 後，在包含該導通孔18内的半導體基板1〇背面上，為使 藉由將從導通孔18所露出之半導體基板1〇之側壁予以絕 緣而形成的絕緣層並對該等構成加以覆蓋，係形成有第2 =障層19。該第2阻障層19,最好為例如氮化鈦層。或者， 第2阻障層19亦可與第j阻障層相同，由氮化欽層以外的 γ金屬形成者。 接著，在第2阻障層19上形成有電鍍用晶種層（seed layer)20與藉由鑛覆處理成膜之再配線層2ι。此外，在再 配線層21上形成保護層（未圖示），並在保護層的預定位置 設置開口並形成與再配線層21接觸之球狀端子22。亦即， 該球狀端子22係隔著再配線層2卜晶種層2〇及第2阻障 層19與銲墊電極層14電性連接。 接著’麥照圖式說明上述本實施形態之半導體裝置之 製造方法。第1圖至第4圖係顯示本實施形態之半導體裝 316698 •200529384 ‘置之製造方法的剖視圖。第1圖至Μ 墊電極層14之區域的剖面，且 乐4圖係顯示存在有銲 片前的狀態。 '丁刀離為個別的半導體晶 如第1圖所示，首先，在形 一 體基板ΗΗ之後分離而形成個別的/H示之電路之半導 隔著絕緣層例如氧化膜u形 曰片）的表面上， .電極層14係在第1阻障層12上羼^包極層14，該銲墊 ·'而成。亦即，第1阻障層12係層13或紹合金層 产10的層。 形成為較為接近半導體晶片 在此，上述未圖示的電路為 槿汰锃埶+托既^ j影像感測器時， :穴3 :層14的紹層13’最好為由純紹形成。而且， =此:將顿紅外 , # 1阻1^層12最好為例如氮化鈦（TiN)層， 在本貫施形態中係使用25(rc 形成氮化鈦（TlN)層。❹，第乂广度的減鍵裝置舰 1:: 物時’亦可使用氮化鈦以外的金屬 所構成之阻障層。 然後’在半導體基板1G的表面上，隔著樹脂層μ(具 黏接劑的功能）’黏接有由例如玻璃所構成之支撐基板 16 〇 接著，如第2圖所示，在半導體基板1〇背面上，形成 將存在銲墊電極層14的部分位置上予以開口之阻劑層 P。接著，以阻劑層17做為遮罩對半導體基板1〇進行蝕 刻，藉此形成由半導體基板1〇的背面到達銲墊電極層14 π 316698 200529384 的第1阻障層12的導通孔18。此時所進行之蝕刻，在 導體基板10為矽（S〇所形成時，最好使用例如：包八〇 或C2F山匕或CHU CF系氣體等㈣氣體^乾㈣2 加以進行。 在此’因位於導通孔18底部之銲墊電極層14 成為第1阻障層！2,因此上述姓刻不會到達料13。因此，、 不會形成如顯示習知例之半導體裝置之第6 氧化物50(例如八丨2〇3化合物）等之氧化物。 丁 .’呂 接著’去除阻劑層17後，如第3圖所示，在 孔18内的半導體基板1G的背面上，形成由氧化膜等構成 之絕緣層以覆蓋上述構成’並在去除第！阻障層η 緣層後，全面形成第2阻障層19。該第 = 為例如氮化鈦層，在本實旖报能+在+ 丨早層19取好 在本只鈀形恕中係在2〇〇t以下的c 裝置内以CVD法形成氮化鈦層。或者， 障層19只要為高熔點金屬或其化合 二：二： 以外的金屬所形成者。另外，在第2阻障v；=::層 成後’可在半導體基板10或第 緩和加諸於球狀端子22的二：層19上’形成用以 此，名飾利土队〃 0力迢之未圖不的緩衝構件。在 在飯刻去除第1阻障層12 t的έ 時，由於第！阻障声12“ " 彖層(例如氧化膜） 成鋁氧化物。 个曰路出，故不會形 接著，如第4 FI α - 心卜卜〜 再配線層21。此，二’在：2阻障層19上之全面形成 此¥，百先，在第2阻障声〗Q μ从八二 藉由電解電鍍形， 曰 上的王面’ ^成由例如銅（Cu)所形成之錢覆用晶種層 316698 12 •200529384 ’之俊1由對該晶種層2G進行無電解電鑛處理，形成 ，（CU)所構成之再配線層2!。在此，再配線層21 =以不完全埋入導通孔内18之方式形成。或
亦可以完全埋入導通孔内18之方式形成。 L 鬌 再者，在再配線層21上形成保(未 :層的預定位置設置開口後利用網版印刷法印刷鲜錫且： 其迴銲（感w)，藉此在前述開口上形成球狀端子Μ 者1未圖示’但藉由沿著分割線，切斷半導體基板10 :及”於该基板的各層，而完成各個半導體晶片，亦即 完成本實施形態之半導體裝置。 如上所述，根據本發明之半導體裝置及其製造方法， 係在半導體基板U)的表面，形成在第丨阻障層12(例如由 氮化鈦層所形成）上疊層_ 13或紹合金層而成之銲 極層14。 藉此，在利用蝕刻形成導通孔18時，因第丨阻障層 a之存在，而得以避免在位於導通孔18底部之銲墊電^ 層14上形成銘氧化物。因此，可極力避免在婷整電極層 14與再配線層21之間形成高電阻。此外，亦可極力抑制 再配線層21產生斷線等損傷。結果’即可極力抑制因形成 上述導通孔18而導致之半導體裝置的特性劣化。此外，由 於無需去除鋁氧化物50，因此不必增加蝕刻步驟。 此外，在本實施形態中，雖在包含導通孔丨8的半導體 基板10背面形成第2阻障層19,但本發明並不限定於此。 亦即，本發明亦可在包含導通孔18的半導體基板1〇背面， 316698 ,^uy293S4 隔著珂述絕緣層形成再配線層2】 此外，在本實施形態中，θ再配不形成第2阻障層19。 而形成者，但本發明並不限制於此。s 21係藉由鍍覆處理 錄覆用的晶種層2ϋ，藉由鑛覆處:即，本發明不形成 層？外？如亦可為_形==再配線 此外，本發明雖適用於形成 i屬之方法。 置，但本發明並未褐限於此。子22之半導體裝 貫通半導體基板之導通孔而 =只要是形成有 =端子之半導體裝置。例如本發:=用:二二 Grid Array)型半導體裝置。 ；GA(Land 層13更之^發明係在形成導通㈣之側㈣ 的钱刻處叫將因此，在進行導通孔開口時 到敍刻。故，不*要顧/^賴刻而導致紹層13的表面受 層13的臈厚。巾…因賴刻而被切削的量而增加紹 【圖式簡單說明】 弟1圖為說明本發明之實施形態之半導體裝置之製造 万法的剖視圖。 第2圖為說明本發明之實施形態之半導體裝置之製造 方法的剖視圖。 圖為說明本發明之實施形態之半導體裝置之製造 方法的剖視圖。
Arh： 卑4圖為說明本發明之實施形態之半導體裝置及其製 造方法的剖視圖。 14 3\6698 200529384 t •第5圖為說明習知例之半導體裝置及其製造方法的剖 視圖。 第6圖為說明習知例之半導體裝置及其製造方法的剖 視圖。 第7圖為說明習知例之半導體裝置及其製造方法的剖 視圖。 【主要元件符號說明】 10、30 半導體基板 11、31 氧化膜 12 第1阻障層 13 1呂層 14、34 銲墊電極層 15 > 35 樹脂層 16、36 支撐基板 17、37 阻劑層 18 08 導通孔 19 第2阻障層 20、40 晶種層 21、41 再配線層 22、42 球狀端子 39 阻障層 50 1呂氧化物 15 316698

Claims (1)

  1. 200529384 十、申請專利範圍： 1· 一種半導體裝置’其特徵在具備： 形成於半導體晶片表面，且％ 層或紹合金層而成之鲜塾電極;，層有弟1阻障層與叙 黏接於前述半導體晶片表面之支撐雕· 由前述半導體晶片背面到達前述二 孑L ;以及 τ曰〜彳逋 形成於包括前述導通孔内部之前述半導體北 面’且與前述第1阻障層相連接之再配線層。日曰月 2.如申請專利範圍帛！項之半導體裝置 / 線層係以完全埋人前述導通孔内部之方式形成。再配 3·如甲凊專利範圍第！項之半導體裝置，直中 線層係以部分埋入前述暮、g 处再配 I刀埋八刖迷泠通孔内部之方式形成。 4·如申請專利範！5第！項至第3項中任—項之 =其中’前料喊㈣藉由料處理或缝處理而' 形成。 1=利範圍第，項至第4項中任一項之半導體裝 八中，在則述再配線層上形成有導電端子。 6. 如申請專利範圍第丨項至第5項中任—項之半導 其中’前述第"且障層係由：氮化鈦層、鈦嫣層、、 氮化组層、高㈣金屬層及其化合物層的任一者所構 成。 7. 如申請專利範圍帛i項至第6項中任一項之半導體裝 置，其令，在包括前述導通孔内部之前述半導體晶片背 316698 16 ,200529384 人刎逑再配線層之間形成有第2阻障層。 8.如：請專利範圍第7項之半導體裝置，其，，2 9. 丄氮化鈦層、鈦鎢層、氮化-層、高炫點金 曰，、化合物層的任一者所構成。 裝ΐίΐ造方法，其特徵為具備:準備具有 1阻逾曰之半導體基板，該輝塾電極層係由疊層有第 手鋁層或鋁合金層而成者， 將切體黏接於前述半導體基板表面之步驟； 達前^料導體基板，形成由該當何體基板背面到 達則述弟1阻障層之導通孔之步驟，·以及 ^括前述導通孔内部之前述半導體基板背面，步 成=述第"轉層相連接之再配線層之步驟。夕 •中^开專利範圍第9項之半導體裝置之製造方法，其 〜述再配線層的步驟中，前述再配線層“ 凡王埋入耵述導通孔内部之方式形成。 專利範圍第9項之半導體裝置之製造方法，t 二::成前述再配線層的步驟中，前述再配線層係二 4刀埋入W述導通孔内部之方式形成。 12=:!!:範圍第9項至第11項中任-項之半導體袈 前述再配線層係藉由鑛覆===㈣的步驟中， 17 λ ^ 柯由观復慝理或濺鍍處理而形成。 .二：利範圍第9項至第12項中任一項之半 端子之步驟。 匕3在所述再配線層上形成導電 316698 17 200529384 *】4.如_請專利範圍第9項至第 置之#方丨甘士 令任—項之半導體裝 之衣k方法，其令，前述第】阻障 鈦鎢層、所介相展丄 曰知由·虱化鈦層、 者所構成'谷點金屬層及其化合物層的任- 15·如申請專利範圍第9項至 置之製造方法，盆由、, 員中任一項之半導體裝 之前述半導係'包含·在包括前述導通孔内部 障層之步驟 與前述再配線層之間形成第2阻 16 ·如申*主宙 矛】範圍第1 5項之半導體麥：詈 中，前述筮,也 只心干V月且衣置之製造方法，苴 弟2阻障層係由：氮化鈦声、飪雜 層、高_|^^ 乳化欽層鈦鹤層、氮化I旦 ”屬層及其化合物層的任一者所構成。
    316698 18
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