TWI559474B - 無穿矽埋孔結構的低散熱傳導係數中介層和其方法 - Google Patents

無穿矽埋孔結構的低散熱傳導係數中介層和其方法 Download PDF

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TWI559474B
TWI559474B TW103108845A TW103108845A TWI559474B TW I559474 B TWI559474 B TW I559474B TW 103108845 A TW103108845 A TW 103108845A TW 103108845 A TW103108845 A TW 103108845A TW I559474 B TWI559474 B TW I559474B
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layer
sealing layer
microelectronic
dielectric region
assembly structure
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TW103108845A
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TW201448138A (zh
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查爾斯Ｇ 渥奇克
席普倫 亞梅卡 烏若
麥可 紐曼
泰倫斯 卡斯基
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英凡薩斯公司
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Description

無穿矽埋孔結構的低散熱傳導係數中介層和其方法
本案為一種與微電子裝置的封裝相關的發明，特別是半導體裝置的封裝。
微電子裝置一般來說都會包含一片很薄的半導體材料，類似像是矽或砷化鎵等，通常會稱之為晶元或是半導體晶片。前述的半導體晶片通常會提供一個個別的，且事先封裝好的單元。在某些單元的設計裡，半導體晶元會被打件在一塊基板或晶元載體之上，其中該基板或載體上還會有電路面板也被打件於其上，如印刷電路板等等。
其中該主動電路會被焊接在半導體晶片的第一表面上(例如前方表面)。為了能將電子連接焊接到主動電路上，晶片會在相同的表面上提供焊墊。其中該焊墊基本上會安排定位在一個正規的陣列中，無論是環繞著晶元的邊緣或，針對很多的記憶體裝置而在晶元的中央。其中該焊墊一般會由傳導材料所構成，類似像銅或鋁等，且其厚度大約為0.5微米(pm)。其中該焊墊可以包含單一的一層或多層的金屬。焊墊的大小會隨著裝置的型式而變化，但基本上它們的每一邊大約都在數十到數百 微米。
中介層可以被用來提供類似像一或多個未封裝或已封裝之 半導體晶片的微電子元件之間的相互電子連接，或一或多個未封裝或已封裝之半導體晶片與其他類似像具有被動電路元件於其中之晶片上積體被動元件(integrated passives on chip，“IPOC”)，分離式被動裝置如電阻和電容，或電感或前述元件之組合等的元件。其中該中介層可能會與該晶片或具有類似像電路板之其他結構的各種晶片等相耦合。
尺寸大小是晶片的任何實質安排配置的重要考量。晶片的 更多整合型實質安排配置的需求已經變成可攜式電子裝置之迅速發展的重點。僅僅就例子來說，我們通常舉“智慧型手機“(smart phone)作為參考範例，它將一般手機的通話功能整合到一個強力的資料處理器，記憶體，以及類似像全球定位系統接收器(GPS)，電子相機，還有區域網路連線和高解析度之顯示器與整合型影像處理晶片等的相關裝置裡。前述的這些裝置可以提供諸如完整的網際網路連接，包含全解析度之影像播放的娛樂，網頁瀏覽，電子銀行和更多其他等等的功能，然後整合在一個口袋大小的裝置裡。前述的複雜的攜帶型裝置必需將許多晶片整合到一個很小的空間中。另外，其中該某些晶片還可能會有許多輸入和輸出的接頭，即一般我們所說的“I/O“。這些輸入/輸出必需內部連接到其他晶片的輸入/輸出接口。其中該內部連接線長最好是越短越好且必須有很低的阻抗，才能讓訊號的傳遞延遲縮減到最小化。當然形成前述之內部連接的元件不應該使何整個裝置的組裝變得太大。在其他應用中也可能會出現類似的需求，舉例來說，像是用來作為網際網路搜尋引擎的那些資料伺服器。 舉例而言，在一堆複雜晶片之間提供各種短而且低阻抗之內部連接的結構將能夠增加搜尋引擎的頻寬並降低其功率消耗。
儘管之前已經有很多技術和發明已經針對中介層結構和製造提出很多主張與敘述，但是本案仍然對於生產製造中介曾與結構的處理程序提出更多的改善方式。
本案為一種微電子的組裝架構，它包含：具有第一表面的介電區域，相對於第一表面位置的第二表面，以及許多至少會順著與第一和第二表面相平行之方向延伸之線路，還有在介電區域之第一表面上的複數接觸點；另外有許多電子傳導元件會與線路相耦合並突出在上述的第二表面之上；在第二表面上延伸的密封層(encapsulant)，其中該密封層會充滿鄰接之傳導元件與從第二表面背離方向起所覆蓋之表面中間的空間，此時傳導元件的終端會在此密封層的表面上；一個具有一個表面和表面上有許多元件接觸點的微電子元件，其中該元件接觸點會面對且連接複數的接觸點，此時密封層的散熱傳導係數(CTE)將不大於整合介電區域或微電子元件之散熱傳導係數的二倍。
如本案所提出之具體實施範例，其中該密封層可以是第一密封層，而微電子組裝架構另外還包含：在第一表面上延伸的第二密封層。
如本案所提出之具體實施範例，其中該第二密封層其散熱傳導係數可以和第一密封層的散熱傳導係數相同。
如本案所提出之具體實施範例，其中該第一與第二密封層都可以密封整個介電區域。
如本案所提出之具體實施範例，其中該微電子元件可以包含在至少一個平行於第一表面的方向上至少能容納二個微電子元件的空間。
如本案所提出之具體實施範例，其中該介電區域可以包含第一介電材料所形成的第一層，以及不同之介電材料所形成的第二層以便能設定作為處理終止層。
如本案所提出之具體實施範例，其中該複數電子傳導元件可以包含至少一種融合固定的材料，這些材料會從由焊錫，錫，銦，銅，鎳，金，各種合金組合，非合金組合，以及電子傳導矩陣材料等所構成的群組中被選擇出來。
如本案所提出之具體實施範例，其中該複數電子傳導元件可以包含許多金屬支柱，這些金屬支柱具有包含以下至少一種金屬所構成的至少一個核心：銅，銅合金，鎳與鎳合金等等，這些金屬支柱的熔點溫度都必須高於300℃。
如本案所提出之具體實施範例，其中該微電子組裝架構包含一塊電路板，其中複數的傳導元件會連接到該電路板表面上的相對應接觸點。
如本案所提出之具體實施範例，其中該介電層可以從由後段製程層(Back End of Line layer，BEOL)與重新分佈層(redustribution layer，RDL)等所構成之組合中被選擇出來。
藉由本案所提出之另一目的主要在說明一種如以上所述之微電子組裝架構以及一或多個電氣連接至結構之其他電子元件。
如本案所提出之具體實施範例，其中該系統還可以包含一個外殼，而前述所謂的微電子組裝架構與其他的電子元件都會被固定裝設在此一外殼上。
藉由本案所提出之另一目的主要在說明一種中介層，它包含：具有第一表面的介電區域，相對於第一表面位置的第二表面，以及許多至少會順著與第一和第二表面相平行之方向延伸之線路，還有在介電區域之第一表面上的複數接觸點；另外有許多電子傳導元件會與線路相耦合並突出在上述的第二表面之上；在第二表面上延伸的密封層(encapsulant)，其中該密封層會充滿鄰接之傳導元件與從第二表面背離方向起所覆蓋之表面中間的空間，此時傳導元件的終端會在此密封層的表面上；一個具有一個表面和表面上有許多元件接觸點的微電子元件，其中該元件接觸點會面對且連接複數的接觸點，此時密封層的散熱傳導係數(CTE)將不會大於整合介電區域，或具有用來與第一表面上之接觸點作覆晶連接(flip-chip connection)之接觸點的微電子元件之散熱傳導係數的二倍。
如本案所提出之具體實施範例，其中該第二密封層其散熱傳導係數可以和第一密封層的散熱傳導係數相同。
如本案所提出之具體實施範例，其中該介電區域可以包含第一介電材料所形成的第一層，以及不同之介電材料所形成的第二層以便能設定作為處理終止層。
如本案所提出之具體實施範例，其中該複數電子傳導元件 可以包含至少一種融合固定的材料，這些材料會從由焊錫，錫，銦，銅，鎳，金，各種合金組合，非合金組合，以及電子傳導矩陣材料等所構成的群組中被選擇出來。
如本案所提出之具體實施範例，其中該複數電子傳導元件 可以包含許多金屬支柱，這些金屬支柱具有包含以下至少一種金屬所構成的至少一個核心：銅，銅合金，鎳與鎳合金等等，這些金屬支柱的熔點溫度都必須高於300℃。
如本案所提出之具體實施範例，其中該介電層可以從由後段製程層(BEOL)與重新分佈層(RDL)等所構成之組合中被選擇出來。
藉由本案所提出之另一目的主要在說明一種製造微電子組裝架構的方法，它包含：在向上突出至沉積於支撐結構上介電區域之第二表面上的一些鄰接電子傳導元件之間的密封填充空間，其中複數的線路會與平行於第一和第二表面之最少一個方向中延伸的傳導元件作電氣連接，此時密封層會具有一個覆蓋且背離第二表面方向的表面，其中傳導元件的終端會在密封層的表面上；針對支撐結構的厚度順著直對介電區域之第一表面的方向來清除至少局部的厚度；組裝一個具有表面以及在此表面上連接著複數元件的微電子元件，以使得元件會接觸表面並且連接到第一表面上的複數接觸點，其中密封層的散熱傳導係數(CTE)將不會大於整合介電區域或微電子元件之散熱傳導係數的二倍。
如本案所提出之具體實施範例，其中該方法另外還可以包含：在組裝完成微電子元件之後清除密封層表面上的部份密封層，接著 在清除密封層表面之部份傳導元件。
如本案所提出之具體實施範例，其中該方法另外還可以包 含：在清除局部的密封層之後，將複數的連接元件附著在表面上之部份傳導元件，其中該連接元件會被設定用來連接第二元件之表面上的複數接觸點。
如本案所提出之具體實施範例，其中該密封層可以是第一 密封層，其中該方法另外還會包含第二密封層的形成，此時的第二密封層會在第一表面之上延伸，而且第二密封層的散熱傳導係數會與第一密封層的散熱傳導係數相同。
如本案所提出之具體實施範例，其中該方法另外還呵以包 含：當完成微電子元件與介電區域的組裝之後，將相對於介電區域之第一表面位置的微電子元件之表面上的局部微電子元件加以磨除，以便能清除至少局部的微電子元件的厚度。
如本案所提出之具體實施範例，其中該微電子元件可以包 含複數的微電子元件。
如本案所提出之具體實施範例，其中該方法另外還可以包 含：將複數的電子傳導元件連接到電路板表面上的相對應接觸點。
如本案所提出之具體實施範例，其中該支撐結構以及介電 區域是一體成形的。
如本案所提出之具體實施範例，其中該支撐結構可以由第 一材料所構成，而介電區域則可以由第二材料所構成。
如本案所提出之具體實施範例，其中該方法另外還可以包 含：沉積處理終止層，並且終止所有在處理終止層上的清除處理程序。
110‧‧‧介電區域
105‧‧‧支撐結構
110a、110b‧‧‧表面
110a1‧‧‧接觸點
111、112、114‧‧‧介電層
113‧‧‧線路
115‧‧‧電子傳導元件
115a‧‧‧支柱
116‧‧‧接觸墊
120‧‧‧密封層
125‧‧‧鍚球
130、130a‧‧‧微電子元件
131‧‧‧表面
135‧‧‧密封層
140‧‧‧連接元件
145‧‧‧密封層
150‧‧‧基板
200‧‧‧微電子組裝架構
300‧‧‧系統
301‧‧‧外殼
302‧‧‧電路板
304‧‧‧傳導器
306‧‧‧結構
308、310‧‧‧電子元件
311‧‧‧鏡頭
本案所附的圖示都針對本案所提出之若干具體實施範例作詳細深入的說明。另外，圖示中的元件配置都只是本案所提出之部份具體實施範例的示意圖而已，並未涵括所有可能的狀況與實際應用。
圖1所示為藉由本案所提出之具體實施範例裡所介紹之組裝包含中介層的微電子組裝架構的區段示意圖。
圖2所示為藉由本案所提出之另一具體實施範例裡所介紹之介電區域的放大區段示意圖。
圖3所示為藉由本案所提出之另一具體實施範例裡所介紹之組裝包含中介層的微電子組裝架構的區段示意圖。
圖4所示為藉由本案所提出之另一具體實施範例裡所介紹之組裝包含中介層的微電子組裝架構的區段示意圖。
圖5所示為藉由本案所提出之另一具體實施範例裡所介紹之組裝包含中介層的微電子組裝架構的區段示意圖。
圖6所示為藉由本案所提出之另一具體實施範例裡所介紹之組裝包含中介層的微電子組裝架構的區段示意圖。
圖7所示為藉由本案所提出之另一具體實施範例裡所介紹之組裝包含中介層的微電子組裝架構的區段示意圖。
圖8所示為藉由本案所提出之另一具體實施範例裡所介紹之組裝包含中介層的微電子組裝架構的區段示意圖。
圖9所示為藉由本案所提出之另一具體實施範例裡所介紹之組裝包含中介層的微電子組裝架構的區段示意圖。
圖10所示為藉由本案所提出之另一具體實施範例裡所介紹之組裝包含微電子組裝架構的系統的區段示意圖。
如圖1所示為藉由本案所提出之組裝包含中介層的微電子組裝架構的方法區段示意圖如圖1中所示，其中該介電區域110會沉積在支撐元件或支撐結構的最上層，且厚度會達到T。其中該支撐結構105可以藉由任何材料來形成，在某些具體實施範例裡該材料可以是矽，模鑄材料，玻璃基板，或任何其他的材料等。基本上，介電區域110會形成於支撐結構105的頂層上。舉例來說，介電區域110可能會有第一表面110a以及相對於第一表面110a之位置的第二表面110b。如本案所提出之某一具體實施範例裡，第一表面110a可以被定義成介電區域110和支撐結構105之間的介面。如本案所提出之另一具體實施範例裡，介電區域110可以完全地和支撐結構105一體成形而且在某些情況下它還可能會藉由相同的介電材料所構成，以使得第一表面110a會在組裝的後段才會出現存在。
如圖2所示為藉由本案所提出之介電區域110以及其所支撐之線路和內部連接之集合的區段放大圖其中該介電區域110可以支撐一或多個線路層，並且結合類似像後段製程層結構中(BEOL)或重新分佈層中(RDL)之埋孔的內部連接結構。舉例來說，介電區域110可 以包含許多的介電層111，112，和114，以及許多的線路113，例如線路層，它們會嵌入在一或多個介電層111，112，和114之中。其中該線路113可以順著任何的方向做延伸，當然也可能會順著相對於介電區域110之表面110a，110b之平行，垂直，或任何其他的方向延伸。
如以上所述，當介電區域110是一種後段製程層區域時， 其厚度T大約會是在50奈米到10奈米之間。如本案所提出之其他範例中，介電區域可能會是或包含重新分佈層(RDL)且有較厚的厚度T，在此情況下線路113順著與表面110a平行的方向延伸之寬度大約會是在20奈米到20微米的範圍內。
如以上所述，介電區域110可以是任何一種介電層，類 似像阻焊層(solder mask)。如本案所提出之其他範例中，介電區域110可能不會包含介電層111。其中該介電層112也可能會是任何型式的介電層，在本案所提出之某一範例裡它還可以包含氧化矽。其中該介電層114可以任何型式的介電層，在本案所提出之某一範例裡它還可以是磨亮終止，研磨終止，或其他的處理終止層，也就是說在某一範例中當支撐結構105遭遇到研磨，重疊，或磨亮的處理時就可以讓處理暫停或激烈的慢下來。如前面所述之層可以包含或由氮化矽所組成，舉例來說，當介電層包含氧化矽。如本案所提出之某一範例裡，處理終止層可以是終端層或終端偵測層，它會藉由將處理裝置接觸到該層並進而偵測處理的終端。
藉由本案所提出之某一具體實施範例，其中該介電層111 和112，以及介電層110的線路113，都可以形成於介電層114的頂端。 其中該介電層114，例如磨亮終止層，研磨終止層，或其他的處理終止層等，都可以形成於支撐結構105的最頂層上，舉例來說，可以藉由將介電層114沉積在支撐結構105的最頂層。
藉由本案所提出之某一具體實施範例，其中該一或多個電子傳導元件115可以被用來突出在介電區域110的第二表面110b之上。請注意，本案中所謂的“之上“與“向上“並不是相對於一般重力的上下關係，而是指從某個表面起的某個方向。藉由本案所提出之某一具體實施範例，其中該電子傳導元件115可以包含傳導聚集，例如焊錫球，如圖2中所示，它可以被附著到電子傳導元件上就如同表面110b的金屬接觸墊116。而本案中所謂的“附著在之上“可以包含在表面上的元件能夠加以連接，或可能就是該表面，或突出在表面之上。其中該金屬接觸墊116，舉例來說，它可能會在與表面110b相平行的方向上有個維度且此維度大約會在2毫米到100毫米。舉例來說，其中該傳導元件115可以包含至少一組接合材料的聚集，類似像焊點，錫，銦，銅，鎳，金，共熔合金(eutectic composition)，非共熔合金，以及電子傳導矩陣材料等等。如本案所提出之另一具體實施範例，其中該傳導元件可能會是支柱115a(post)，如圖2中所示，它可以藉由將金屬電鍍到金屬墊上或，直接包覆上一層類似像銅，銅合金，鎳或鎳合金，或其他金屬的組合等的金屬，之後在對這些金屬層加以蝕刻以形成支柱115a。當藉由蝕刻而形成之後，支柱115a將會如同圖2中所示的截頭圓錐形狀(frustoconical shape)。其中該電子傳導元件115可能會是焊錫球與上述之支柱的任意組合，或任合型態的電子傳導元件。如此一來， 傳導元件115就可以包含由包含銅，銅合金，鎳或鎳合金等的金屬所構成之群組中所選擇出來的至少一種金屬所形成的核心，這樣的支柱其熔點將會高達300℃以上。
其中在介電區域110的第一表面110a上具有複數的接觸 點110a1。如本案所提出之某一具體實施範例，其中該接觸點110a1可以包含微凸塊接觸點以連接一或多個微電子元件，而詳細說明如以下所述。
如以上所述之系統架構中，一或多個接觸點110a1可能會 透過線路113而與一或多個電子傳導元件115或傳導元件(支柱115a)作電氣耦合。其中該接觸點110a1，電子傳導元件115，以及線路113可以藉由系統接觸點110a1來設定成為任何所需要的設定，以使得任何傳導元件和接觸點的內部連接設定能夠完成。
藉由本案所提出之具體實施範例中，接觸點110a1就定位 在表面110a上且其最小的間距可以和介電區域110相對方向之表面110b的電子傳導元件115或支柱115a的最小間距相同或不同。如本案所提出之某些特殊範例，傳導元件115的最小間距可以大於接觸點110a1的最小間距，且其比例可大於1：1，而在某些範例中該比例會大於或等於2：1，甚至在其他範例中該比例會大於或等於3：1，或甚至更大。
其中該介電區域110的散熱傳導係數(CTE)最高可達到 10ppm/℃，而在某些狀況下該散熱傳導係數會與矽或其他半導體材料的散熱傳導係數相同或接近，例如散熱傳導係數會低於5ppm/℃。
如圖3所示為藉由本案所提出之具體實施範例中，介電區 域110的第二表面110b上的密封層120。如本案所提出之某一具體實施範例，密封層120可以覆蓋電子傳導元件115以局部或完全地密封該電子傳導元件115。其中該密封層120可以填滿介於鄰接之電子傳導元件115之間的空間。如本案所提出之某一具體實施範例，密封層120的散熱傳導係數會在最高等於10ppm/℃的範圍裡。
比較圖4與前述之圖1，其中至少局部的支撐結構105 的厚度T會從介電區域110的第一表面110a上被移除。藉由許多不同的方法可以達到此一目的，例如像是研磨，磨亮，或反結合，劈開，蝕刻，或任何其他的處理程序，或以上這些處理程序的組合。在進行清除的處理程序過程中，用來作為研磨終止層或終端偵測層的介電層114，將會被偵測到或暴露出來。如此將有助於確認出支撐結構105的位置，特別是對於半導體材料或非介電材料之一被完全地清除後，也要注意確認介電區域110它本身或局部並未隨著被清除。
如圖5所示為本案所提出之具體實施範例中，複數的微電 子元件130可以定位且覆蓋在介電區域110的第一表面110a之上。其中該微電子元件其散熱傳導係數會在最高不超過10ppm/℃的範圍內。 如本案所提出之某一具體實施範例，微電子元件130可以是或包含具有主動電路元件之半導體晶片，類似像電晶體。其中該微電子元件130會被配置在與第一表面110a相平行的方向上。如本案所提出之另一具體實施範例，微電子元件130則可以是或包含被動電路元件，類似像整合被動元件晶片(integrated passives on chip，IPOC)。其他也還可以包含另外的微電子元件130a。其中該微電子元件130a可以是被動微電子元件， 類似像是被動晶元。
其中該每一個微電子元件130都會具有一個表面131以 及在該表面131上有許多接觸點，以便能面對並與介電區域之表面110a上的相對應接觸點110a1作連接，就如同電子傳導凸塊金屬。同理，元件130a也可以和接觸點110a1相連接在一起。
如圖6中所示為藉由本案所提出之具體實施範例中的密封 層135。其中該密封層可以包含未填滿的與/或覆蓋的情形。如本案所提出之某一具體實施範例，密封層135的散熱傳導係數要比與密封層120相結合之散熱傳導係數來得較高，特別是因為在微電子元件130中的矽主要用來作為補強且具有較高的楊格彈性係數(Young's modulus)。在本案所提出之其他範例中，密封層120與135可以具有相同的散熱傳導係數，或密封層135的散熱傳導係數要比密封層120的散熱傳導係數來的較低。
如圖中所示，密封層120與135的組合可以是二者個別 或整合在一起，至少會局部或完全地密封介電區域110。如此將會使得組裝便得相對容易。在本案其他的範例中，密封層135可以從組裝系統中被忽略。
如圖7中所示為藉由本案所提出之具體實施範例中，密封 層120的局部與/或電子傳導元件115可以被部份地清除以便至少能暴露出部份的電子傳導元件115。以上的處理可以藉由類似像打磨，磨亮，拋光，或其他等的研磨處理程序來完成。另外，包含由焊錫，錫，或其他電子傳導材料所構成的傳導群塊的電子傳導元件115可以被用來和 其他的電子傳導結構相接觸，例如像是接觸墊116，埋孔，線路等，它們都會在前述的清除處理程序中被暴露出來。
如本案所提出之某一具體實施範例，其中密封層135的局 部，以及微電子元件130的局部等都可能也會被清除。清除的處理方法也可以藉由類似像打磨，磨亮，拋光，或其他等的研磨處理程序來完成。
如圖8所示為藉由本案所提出之具體實施範例中，連接元 件140可以被附著在電子傳導元件115上。其中該連接元件可以包含或藉由強化接合材料之電子傳導群塊所構成，舉例來說，在沒有任何限制的情況下，焊錫，錫，共熔合金，或其他電子傳導矩陣材料等，類似像填充了金屬粒子或薄片的聚合物材料。如本案所提出之某些特殊範例裡，其中該連接元件可以包含內含低熔點溫度與高熔點溫度之元件的金屬元件。
如圖9所示為藉由本案所提出之具體實施範例中，微電子 組裝架構200包含藉由前面所述之中介層。其中該中介層可能會包含，舉例來說，介電區域110，電子傳導元件115，以及密封層120。在此階段裡，其中該連接元件140可以連接到基板150。另外，其中該密封層145，例如像是填充劑，可以用來填滿介於密封層120，基板150，以及連接元件140之間的空間。
如本案所提出之某一具體實施範例，其中該密封層120其 散熱傳導係數將不高於整合微電子元件或連接到微電子元件之介電區域110的散熱傳導係數二倍。
如本案所提出之另一未顯示於圖中之具體實施範例，基板 150另外還可以透過將基板接觸到電路板的表面上(但未顯示於圖中)以連接到一片電路板。另外，基板150它本身也可以就是電路板或可以包含被動，主動，或其他的電路元件。
如以上所介紹之結構說明了一些特殊三維內部連接的架構。這些架構可以被應用在任何型式的晶片上。藉由本案所提出之具體範例中的方法，以下所列之晶片組合也可以被包含在前面所述之結構中：(i)一個處理器與提供給該處理器使用之記憶體；(ii)相同型式之複數記憶體晶片；(iii)相反型式之複數記憶體晶片，類似像DRAM與SRAM；(iv)一個影像感應器與用來處理由該影像感應器所傳送過來之影像的影像處理器；(v)特殊應用規格積體電路(application-specific integrated circuit，ASIC)與記憶體。
如前面所述之結構可以被應用在各種不同電子系統的建立過程裡。舉例來說，如本案所提出之另一具體實施範例裡的系統300包含如前面所述之整合了其他電子元件308與310所構成的結構306。如此一範例所述，元件308是一個半導體晶片而元件310則是一個顯示螢幕，但是也可以是其他的元件。當然，如圖10所示只有顯示出兩個額外的元件來說明此一結構，但是系統其實可以包含任何數量的任何元件。如前面所述其中該結構306可以類似像是如圖1~9中所說明的微 電子組裝系統。其中該結構306以及元件308和310會整合固定在一個通用的外殼301中，線路則以虛線來表示，而且彼此間的電氣連接是必需的以形成所要的電氣迴路。如此一範例系統所示，該系統包擴了一塊類似像彈性印刷電路板的電路板302，且該電路板包含若干個傳導器304，但只有一個傳導器顯示在圖10之中，並且元件彼此之間都會相互地內部連接。然而，前面所述畢竟只是一個簡單的範例而已；它可以應用在建立電氣連接的任何適當結構裡。其中該外殼301可以是可用型式的可攜式外殼，舉例來說，它可以是手機或個人數位助理等的可攜式裝置，且螢幕310會設置暴露在外殼的表面上。其中該結構306包含一個類似像影像處理晶片的感光元件，而鏡頭311或其他的光學裝置也可以加進來以便能讓光線得以進入結構中。再次重申，如圖10所示的簡易系統只是一個簡單的範例示意圖；其他的系統，包含具有固定結構的系統，如桌上型電腦，路由器，以及如前所述之使用此一結構的裝置等，都包含在本案所提出之涵蓋範疇。
當本案所提出之各種具體實施範例被詳細地引述說明時，這些應用或衍生的理論都在本案所提出的專利申請涵蓋範圍之內。額外的優點或變化也都屬於本案所提出之技術所能涵蓋的權利範圍。因此，本案所提出申請的權利範圍並不僅限於前述所提出介紹的具體實施範例而已，各種其他的延伸方法或範例等也都涵蓋在其中。也就是說，只要是應用的精神或理念符合本案所提出的前述構想都將在保護的範圍中。其他的申請範圍細節則都詳細地載明於附件裡申請範圍之中。
110‧‧‧介電區域
115‧‧‧電子傳導元件
115a‧‧‧支柱
116‧‧‧接觸墊
111、112、114‧‧‧介電層
113‧‧‧線路
110a、110b‧‧‧表面
110a1‧‧‧接觸點

Claims (18)

  1. 一種微電子組裝架構，包含：一介電區域，具一第一表面，一第二表面，複數之線路及複數接觸點，該第二表面係相對於該第一表面，該複數之線路係以平行於該第一和第二表面之至少一方向作延伸，該複數接觸點係位於該介電區域之第一表面；複數電子傳導元件，係與該線路相耦合，且突出在第二表面之上；一密封層，係於該第二表面上延伸，該密封層係填滿介於相鄰接之傳導元件之間的空間，並且具有一表面，該表面係覆蓋該第二表面之背面，其中該傳導元件的終端係落在該密封層的表面上；一微電子元件，其複數元件接觸點位於該微電子元件之表面上，該等元件接觸點面對並且連接上述之複數接觸點；其中，該密封層之散熱傳導係數(CTE)不大於結合該介電區域或該微電子元件之散熱傳導係數的二倍。
  2. 如申請專利範圍第1項所述之微電子組裝架構，其中該密封層為第一密封層，該微電子組裝架構另外還包含：一第二密封層，係於該第一表面上延伸，而且介於該第一表面及該微電子元件之該表面之間。
  3. 如申請專利範圍第2項所述之微電子組裝架構，其中該第二密封層之散熱傳導係數與該第一密封層的散熱傳導係數相同。
  4. 如申請專利範圍第2項所述之微電子組裝架構，其中該第一與第二密封層係密封該介電區域。
  5. 如申請專利範圍第1項所述之微電子組裝架構，其中該微電子元件包含之至少二微電子元件係以至少一平行於該第一表面的方向定距相隔。
  6. 如申請專利範圍第1項所述之微電子組裝架構，其中該介電區域包含一第一層及一第二層；該第一層由第一介電材料構成，該第二層由一種不同之介電材料所構成，可規劃作為一處理終止層。
  7. 如申請專利範圍第1項所述之微電子組裝架構，其中該複數電子傳導元件包含一群接合材料，其可選擇之群組包含：焊錫、錫、銦、銅、鎳、金、共熔合金、非共熔合金、以及電子傳導矩陣材料等。
  8. 如申請專利範圍第1項所述之微電子組裝架構，其中該複數電子傳導元件包含複數的金屬墊，這些金屬墊之至少一核心基本上包含一種由銅、銅合金、鎳與鎳合金等所選出來的金屬，而該金屬墊的熔點溫度係高於300℃。
  9. 如申請專利範圍第1項所述之微電子組裝架構，其中另外還包含一電路板，其中該複數傳導元件係連接到該電路板之表面上相對應的接觸點。
  10. 如申請專利範圍第1項所述之微電子組裝架構，其中該介電區域係選自一群組，該群組包含後段製程層(Back End of Line layer，BEOL)與重新分佈層(redustribution layer，RDL)。
  11. 一種系統，包含申請專利範圍第1項所述之微電子組裝架構；以及一或多個與該架構電氣連接之其他的電子元件。
  12. 如申請專利範圍第11項所述之系統，其中另外還包含一外殼，而前述的微電子組裝架構與其他的電子元件係固定在此一外殼上。
  13. 一種中介層，包含：一介電區域，具一第一表面、一第二表面、複數線路及複數接觸點；該第二表面相對於該第一表面；該複數線路之延伸之至少一方向係平行於該第一和第二表面，該複數接觸點係位於該介電區域之第一表面上，以作為覆晶連接(flip-chip conneciton)，並連接一微電子元件之相對應的元件的接觸點，如同一焊接金屬位於其間；複數電子傳導元件，係與該線路相耦合且突出在第二表面之上；一密封層，係在該第二表面上延伸，該密封層係填滿介於相鄰接之傳導元件之空間，且有一表面覆蓋於該第二表面之背面，其中該傳導元件的終端係落在密封層的表面上；其中該密封層之散熱傳導係數(CTE)不大於結合該介電區域或微電子元件之散熱傳導係數的二倍。
  14. 如申請專利範圍第13項所述之中介層，其中該第二密封層之散熱傳導係數等於第一密封層的散熱傳導係數。
  15. 如申請專利範圍第13項所述之中介層，其中該介電區域包含一第一層及一第二層；該第一層由第一介電材料所構成，該第二層由不同之介電材料所構成，並規劃用來作為處理終止層。
  16. 如申請專利範圍第13項所述之中介層，其中該複數電子傳導元件包含至少一群接合材料，其可選擇之群組包含焊錫、錫、銦、銅、鎳、金、共熔合金、非共熔合金以及電子傳導矩陣材料等。
  17. 如申請專利範圍第13項所述之中介層，其中該複數電子傳導元件包含複數金屬墊，其至少具有一核心；該核心基本上由一金屬構成，該金屬可選自銅、銅合金、鎳與鎳合金；該金屬墊的熔點溫度高於300℃。
  18. 如申請專利範圍第13項所述之中介層，其中該介電區域係可選自一群組，該群組之構成係為後段製程層(Back End of Line layer，BEOL)與重新分佈層(redustribution layer，RDL)。
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US8884427B2 (en) 2014-11-11
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TW201448138A (zh) 2014-12-16
KR102037114B1 (ko) 2019-10-28
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