TWI413225B - 半導體結構以及半導體元件的形成方法 - Google Patents

半導體結構以及半導體元件的形成方法 Download PDF

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Publication number
TWI413225B
TWI413225B TW099135705A TW99135705A TWI413225B TW I413225 B TWI413225 B TW I413225B TW 099135705 A TW099135705 A TW 099135705A TW 99135705 A TW99135705 A TW 99135705A TW I413225 B TWI413225 B TW I413225B
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Taiwan
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buffer layer
bump
substrate
pad
ball
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TW099135705A
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English (en)
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TW201143002A (en
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Chen Hua Yu
Jiun Yi Wu
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Taiwan Semiconductor Mfg
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Publication of TW201143002A publication Critical patent/TW201143002A/zh
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Description

半導體結構以及半導體元件的形成方法
本發明關於半導體元件，特別是有關於基板接觸窗。
自積體電路(integrated circuit，IC)發明以來，由於各種電子組件(例如電晶體、二極體、電阻、電容等)的積體密度(integration density)不斷提高，半導體工業已經歷了連續的快速成長。在大多數的情況下，積體密度的提高是來自於最小特徵尺寸(minimum feature size)一再地縮小，且最小特徵尺寸的縮小可使更多的組件集成到一給定的面積中。
在過去的幾十年中，也經歷了許多半導體封裝的轉變，且這些轉變影響了整個半導體工業。一般而言，導入表面黏著技術(surface-mount technology，SMT)與球格陣列(ball grid array)封裝對於眾多種類的積體電路元件之高產量組裝而言是重要的手段，於此同時還能允許印刷電路板(printed circuit board，PCB)上之接墊間距(pad pitch)縮小。習知的積體電路封裝基本上是藉由細金線互連，細金線係位於晶片上的金屬接墊與由模製樹脂封裝(molded resin package)所延伸出的電極之間。在另一方面，有些球格陣列封裝是依靠焊料凸塊來電性連接晶片上的接點與封裝基板(例如矽轉接板、有機基板、陶瓷基板或其相似物)上的接點，並依靠焊球來電性連接封裝基板上的接點與印刷電路板。同樣地，有些晶片級封裝(chip size packaging，CSP)的封裝體是依靠焊球來直接電性連接晶粒上的接點與印刷電路板、另一晶片/晶圓或其相似物。這些技術也可用來使多個晶片及/或晶圓互相連接。組成這些互連的各種膜層通常具有不同的熱膨脹係數(coefficients of thermal expansion，CTEs)。因此，在連接區可能會出現相當大的應力，而應力經常會導致產生裂縫。
本發明一實施例提供一種半導體結構包括一第一基板、一第二基板以及一導電材料。第一基板具有形成於其上的電路。第二基板包括一第一接墊、一第一緩衝層以及一第一導體焊墊，其中第一緩衝層位於第一接墊上，且第一緩衝層的一開口暴露出至少部分的第一接墊，第一導體焊墊電性接觸第一接墊並具有一非平坦的表面，第一導體焊墊沿著開口的側壁而形成並延伸至至少部分的第一緩衝層上。導電材料插置於第一基板與第二基板之間，導電材料直接接觸第一導體焊墊。
本發明一實施例提供一種半導體結構包括一第一基板以及一凸塊應力緩衝層。第一基板具有一第一側與一第二側，且第一側與第二側至少其中之一被形成為接受一連接至一積體電路晶片。凸塊應力緩衝層位於第一基板的第一側上，凸塊應力緩衝層包括一第一凸塊緩衝層，第一凸塊緩衝層位於一第一電接點上，且第一凸塊緩衝層具有一開口，開口位於至少部分的第一電接點上，第一凸塊應力緩衝層更包括多個第一凸塊導體焊墊，第一凸塊導體焊墊具有均勻的厚度並延伸至第一凸塊緩衝層的一頂面上。
本發明一實施例提供一種形成一半導體元件的方法，其包括：提供一第一基板，第一基板具有一第一電接點與一第二電接點，第一電接點位於一第一側上，第二電接點位於一第二側上；形成一第一凸塊緩衝層於第一電接點上，第一凸塊緩衝層具有一第一開口，第一開口位於至少部分的第一電接點上；以及形成一第一凸塊導體焊墊，第一凸塊導體焊墊延伸至第一凸塊緩衝層的一頂面上，第一凸塊導體焊墊具有均勻的厚度。
以下將詳細說明本發明之多個實施例的製作與使用方式。然應注意的是，這些實施例提供許多可供應用的發明概念，其可在多種特定的環境中實施。文中所討論的特定實施例僅用以說明以特定的方式去製作與使用實施例，非用以限制本發明之範圍。
在此描述的實施例係關於凸塊下金屬(under-bump metallization，UBM)的使用，該凸塊下金屬適用於半導體元件。如同以下即將討論的，實施例係揭露利用基板上的凸塊下金屬結構來將一基板貼附至另一基板，其中各基板可為封裝基板、轉接板(interposer)、印刷電路板或其相似物。其他實施例的凸塊下金屬結構可被用來電性連接一或多個晶片與一基板，並可依序電性連接至另一基板。舉例來說，實施例亦可應用在晶圓級晶片尺寸封裝(wafer level chip scale packaging，WLCSP)製程中。在全部的圖示與說明實施例中，相似之標號將用以標示相似之元件。
第1圖繪示本發明一實施例之三個相互連接的基板的部份剖面圖。一第一基板100可代表一或多個晶片，且前述晶片上具有電路。第一基板100可包括任何適合的基板，例如已摻雜或未摻雜的塊狀矽(bulk silicon)或是絕緣體上半導體(semiconductor-on-insulator，SOI)基板的主動層，或是其相似物。第一基板100上所包括的電路可為任何類型的電路，且前述電路適於特定的應用。舉例來說，電路可包括各種N型金氧半導體(N-type metal-oxide semiconductor，NMOS)及/或P型金氧半導體(P-type metal-oxide semiconductor，PMOS)元件(例如電晶體)、電容、電阻、二極體、光二極體、保險絲及其相似物，且前述元件可彼此互連以執行一或多個功能。前述功能可包括記憶體結構(memory structure)、處理結構(processing structure)、感應器、增幅器(amplifier)、電力分配(power distribution)、輸入/輸出電路或其相似功能。本領域具有通常知識者將可了解上述所提供之例子僅為了進一步解釋一些說明實施例的應用，並非用以限制本發明。其他的電路可恰當地用在一特定的應用上。
第一基板100更包括多個外部接點102，用以提供外部電性連接至形成於其上的電路。圖案化一第一鈍化層104以提供一位於外部接點102上的開口以及保護下層不受到各種環境污染。當第一基板100的上介電層暴露於外界環境中時容易被氧化，因此第一鈍化層104形成在最上面的介電層上。之後，在第一鈍化層104上形成並圖案化多個第一導電接墊106，如此一來，可暴露出至少部分的外部接點102。在第一鈍化層104上形成一第二鈍化層105，第二鈍化層105例如為一聚亞醯胺層(polyimide layer)或者是由其他的高分子材料所構成。之後，在第二鈍化層105上形成並圖案化一凸塊下金屬層107以電性連接至外部接點102。凸塊下金屬層107可由任何適合的導電材料(例如銅、鎢、鋁、銀、前述之組合或是其相似物)所構成。
本領域具有通常知識者將可了解第一基板100可包括許多其他的特徵。舉例來說，第一基板100可包括各種金屬化層/介電層、導孔(via)、接點、貫穿基板導孔(through-substrate via)、鈍化層、襯層(liner)、黏著/阻障層、重分布層(redistribution layer)及/或其相似物。
任何適合的製程都可被用來形成上述的結構，並且在此將不會再作更詳細的討論。本領域具有通常知識者將可了解以上的描述提供了實施例之特徵的一般說明，而且可提出許多其他的特徵。舉例來說，可提出其他的電路、襯層、阻障層、凸塊下金屬結構及其相似物。以上的描述在此僅用以討論實施例，並非用以將本發明或是任何申請專利範圍限制在那些特定的實施例中。
第1圖亦繪示本發明一實施例之一第二基板120與一第三基板150。第二基板120例如可為有機基板、陶瓷基板、矽或玻璃轉接板、高密度互連(high-density interconnect)、及其相似物。在一實施例中，第三基板150為一印刷電路板，但可包括其他類型的基板。在某些實施例中，第二基板120可包括電子組件，例如電容、電阻、訊號分配電路(signal distribution circuitry)、及/或其相似的電子組件。這些電子組件可為主動、被動或是主動與被動組件之結合。
第二基板120具有一凸塊應力緩衝層(bump stress buffer layer)122與一第一球應力緩衝層(ball stress buffer layer)126，其中凸塊應力緩衝層122沿著一晶片側124配置，第一球應力緩衝層126沿著一外側128配置。在晶片側124上，凸塊應力緩衝層122包括多個凸塊接點130，其上具有一凸塊緩衝層(bump buffer layer)132。圖案化凸塊緩衝層132以提供多個位於凸塊接點130上的開口，從而暴露出至少部分的凸塊接點130。凸塊導體焊墊(bump conductor pad)134形成於開口中並且與凸塊緩衝層132之至少部分上表面重疊。
同樣地，在外側128上，第一球應力緩衝層126包括多個第一球接點140，其上具有一第一球緩衝層(ball buffer layer)142。第二基板120可具有一或多個導孔(例如貫穿基板導孔，未繪示)以電性連接各第一球接點140以及各凸塊接點130。圖案化第一球緩衝層142以在第一球接點140上形成開口，從而暴露出至少部分的第一球接點140。第一球導體焊墊(ball conductor pad)144形成於(第一球緩衝層142的)開口中，並與第一球緩衝層142的上表面至少部分重疊。
第三基板150具有一第二球應力緩衝層160，第二球應力緩衝層160包括一第二球接點162以及形成於第二球接點162上的一第二球緩衝層164。圖案化第二球緩衝層164以於第二球接點162上形成開口，從而暴露出至少部分的第二球接點162。第二球導體焊墊166形成於(第二球緩衝層164的)開口中並與第二球緩衝層164的上表面至少部分重疊。
凸塊緩衝層132、第一球緩衝層142以及第二球緩衝層164共同稱為緩衝層，其可由介電材料所構成，介電材料例如為高分子材料、環氧樹脂(epoxy)、聚亞醯胺(polyimide)、防焊材料(solder resist)、光阻材料或其相似物，並可以任何適合的方法製得，例如噴塗法(spray coating)、滾輪塗佈(roller coating)、印刷(printing)、層壓(film lamination)或其相似的方法。在一實施例中，緩衝層的厚度約為1-30微米。之後，以微影技術圖案化緩衝層，其係藉由沈積一光阻材料、以定義有開口的圖案對該光阻材料進行曝光、以及使該光阻材料顯影以移除該光阻材料之多餘的部份，或是以雷射鑽孔的方式移除該光阻材料之多餘的部份來達成。一旦形成該圖案化的光阻材料，就可以該圖案化光阻材料作為蝕刻罩幕圖案化該緩衝層(如第1圖所示)。值得注意的是，緩衝層本身可由光阻材料所構成(例如感光高分子材料)，且當緩衝層本身是由光阻材料所構成時可省略蝕刻步驟，或者是緩衝層本身可以雷射鑽孔的方式形成。
如第1圖中的插圖所示，在一實施路中，緩衝層的開口具有一寬度D以及一高度H，高寬比(H/D)的範圍約為0.1至1。在另一實施例中，寬度D約為高度H的二分之一。值得注意的是，在一實施例中，開口的側壁可以是傾斜的(slanted)，而且在本實施例中，寬度D可以是從開口的側壁的中點量測而得的。
凸塊導體焊墊134、第一球導體焊墊144以及第二球導體焊墊166共同稱為導體焊墊，其可經由任何適當的方法而形成，包括物理氣相沈積(physical vapor deposition，PVD)、化學氣相沈積(chemical vapor deposition，CVD)、電化學沈積(electrochemical deposition，ECD)、分子束磊晶(molecular beam epitaxy，MBE)、原子層沈積(atomic layer deposition，ALD)、電鍍以及其相似的製作方法。在一實施例中，導體焊墊是藉由沈積一共形的(conformal)晶種層而形成的，該晶種層為一導電材料薄膜，其可有助於在後續的製程中形成一較厚的膜層。晶種層可以是以化學氣相沈積技術或是物理氣相沈積技術沈積一薄導電層的方式形成，其中該薄導電層例如為鎳、金、銅、鈦、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、其他的惰性金屬(inert metal)、前述之組合、或其相似物的一薄層。之後，在晶種層上形成一圖案化罩幕並進行圖案化，以定義出導體焊墊的橫向邊界(lateral boundary)。圖案化罩幕例如可為一圖案化光阻罩幕、硬罩幕、前述之組合、或其相似物。
在圖案化罩幕形成在晶種層上之後，可進行一電鍍製程以形成導體焊墊至希望的厚度。導體焊墊可為由一或多種材料所構成的單層、複合層、疊層、及其相似的結構，且前述材料例如為鉭、鈦、鎳、金、銅、鋁、鈀、其他惰性金屬或其相似物。舉例來說，在一實施例中，導體焊墊包括一厚度約為5微米的銅層以及一厚度約為3微米的上方鎳層。在一實施例中，導體焊墊是由一材料所構成，該材料例如為鎳、鈀、金、或其相似物，該材料可防止銅擴散至導電凸塊/球中或是減少銅之擴散至導電凸塊/球中的能力。在一實施例中，導體焊墊具有一非平坦的表面並具有一均勻的厚度，該厚度約小於10微米。一旦導體焊墊形成，可移除圖案化罩幕及晶種層之剩下的部分。在多個實施例中，圖案化罩幕層是由光阻材料所形成的，而光阻可例如被一化學溶液剝除，該化學溶液例如為乳酸乙酯(ethyl lactate)、苯甲醚(anisole)、乙酸甲酯丁酯(methyl butyl acetate)、乙酸戊酯(amyl acetate)、甲酚醛樹脂(cresol novolak resin)以及重氮光活性化合物(diazo photoactive compound，稱為SPR9)的混合物，或者光阻可被其他的剝除製程剝除。可進行一清潔製程(例如浸濕於一磷酸與過氧化氫的化學溶液(稱為DPP)中，其具有2%的氫氟酸)或是另外的清潔製程以移除晶種層之外露的部份以及任何來自於緩衝層表面的污染物。值得注意的是，上述製程可使凸塊導體焊墊134、第一球導體焊墊144以及第二球導體焊墊166具有圓化的邊緣(rounded edge)。
導電凸塊170電性連接於第一基板100與第二基板120之間，導電球172電性連接於第二基板120與第三基板150之間。在一實施例中，第二基板120提供一與第一基板100相配的熱膨脹係數以減少因熱應力所導致的第一基板100與第二基板120之間的焊料連接故障的可能性(potential solder failure)，第二基板120例如為一矽轉接板。第二基板120用來轉接第一基板100上之縮小間距的較小接墊與第三基板150上之增大間距的較大接墊。為了有助於轉接製程以及容許第一基板100與第三基板150具有不同的接腳配置(pin configuration)，第二基板120可包括一或多個重分布層，重分布層可位於晶片側124與外側128其中之一或兩者上。導電凸塊170與導電球172可為無鉛凸塊(lead free bump)、共晶凸塊(eutectic bump)、銅柱(Cu post)、或其相似物，且導電凸塊170與導電球172可包括同質的(homogeneous)材料特性。
此技藝人士當可了解，可選擇性地(optional)在第一基板100與第二基板120之間以及第二基板120與第三基板150之間形成一底膠(underfill)174，以分別提供較為可靠的電性連接以及保護連接第一基板100與第二基板120以及連接第二基板120與第三基板150的焊料凸塊/球免於受到外界的污染。
第2A圖與第2B圖分別繪示本發明之其他實施例之凸塊連接與球連接。第2A圖所介紹的實施例相似於第1圖所介紹的實施例，除了第2A圖所介紹的實施例具有二凸塊緩衝層(1321 、1322 )以及二凸塊導體焊墊(1341 、1342 )以外，且凸塊緩衝層(1321 、1322 )以及凸塊導體焊墊(1341 、1342 )可分別使用相似於上述的凸塊緩衝層132與凸塊導體焊墊134的技術與材料並以相似的方式形成。
同樣地，第2B圖所介紹的實施例相似於第1圖所介紹的實施例，除了第2B圖所介紹的實施例具有二球緩衝層(1641 、1642 )與二球導體焊墊(1661 、1662 )以外，且球緩衝層(1641 、1642 )與球導體焊墊(1661 、1662 )可分別使用相似於上述的球緩衝層164與球導體焊墊166的技術與材料並以相似的方式形成。值得注意的是，第2B圖的基板200代表第1圖的第二基板120或第三基板150，故第二基板120及/或第三基板150可具有二球緩衝層164與二球導體焊墊166。
值得注意的是，實施例(例如在此介紹的多個實施例)允許導電凸塊及/或導電球具有同質的材料特性。在其他元件所用的連接(connection)中，導電凸塊及/或導電球會被多種類型的材料所圍繞，例如防焊材料及底膠材料。然而，在此揭露的這些實施例中，導電凸塊及/或導電球僅被單一類型的材料所圍繞，例如底膠材料。如此一來，單一材料特性會施加應力在導電凸塊及/或導電球上。也已經發現在導體焊墊與導電凸塊/球之間的熱應力小於(如同在其他系統中的)導電凸塊/球與防焊材料直接連接處的熱應力。
第3圖介紹本發明之另一實施例，其例如可被用於晶圓級晶片尺寸封裝中。在本實施例中，一晶圓級晶片尺寸封裝的晶片300經由導電球372直接連接至一印刷電路板302。晶圓級晶片尺寸封裝的晶片300已於其上形成一晶圓級晶片尺寸封裝的球緩衝層332，其中晶圓級晶片尺寸封裝的球緩衝層332已被圖案化以暴露出其下方的晶圓級晶片尺寸封裝的球接點330。晶圓級晶片尺寸封裝的球導體焊墊334形成於晶圓級晶片尺寸封裝的球緩衝層332的開口中並延伸至晶圓級晶片尺寸封裝的球緩衝層332的一表面上。可利用類似凸塊接點130、凸塊緩衝層132與凸塊導體焊墊134的製程與材料來分別形成晶圓級晶片尺寸封裝的球接點330、晶圓級晶片尺寸封裝的球緩衝層332與晶圓級晶片尺寸封裝的球導體焊墊334。
在晶圓級晶片尺寸封裝製程完成後，晶圓級晶片尺寸封裝的晶片300可利用例如導電球372連接至印刷電路板302，其中導電球372可類似於上述的導電球172。一選擇性的底膠374亦被表示出來，其中底膠374可相似於上述的底膠174。
值得注意的是，在本實施例中，依照晶圓級晶片尺寸封裝技術，晶圓級晶片尺寸封裝的晶片300是本身具有導電球372於其上的晶片。因此，本實施例將上述之晶片上的導電凸塊/球接點結構(參考第1-2B圖)應用在晶圓級晶片尺寸封裝結構中並用在印刷電路板302上。雖然某些元件具有過去使用的導電凸塊/球結構(其相似於上述在晶片本身上的導電凸塊/球結構)，但本實施例除此之外還將導電凸塊/球結構應用在晶圓級晶片尺寸封裝結構中。
已經發現例如上述的這些實施例可減少導電凸塊/球、第二基板與第三基板之間的應力，並且使用例如在第二基板與第三基板上的結構亦可減少第一基板本身中的應力，第一基板本身例如為矽晶片。舉例來說，模擬結果指出，在一實施例中，晶片直接貼附至基板，且基板例如使用上述的導體焊墊，此實施例不僅可以減少凸塊與基板之間的應力，還可減少凸塊與矽晶片本身之間的應力。特別是，模擬比較了位於一(不具有上述的導體焊墊結構的)基板與一晶片之間的連接以及位於一(具有上述的導體焊墊結構的)基板與一晶片之間的連接，在凸塊與晶片之間的界面區域中的應力可減少至少32%。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．第一基板
102．．．外部接點
104．．．第一鈍化層
105．．．第二鈍化層
106．．．第一導電接墊
107．．．凸塊下金屬層
120．．．第二基板
122．．．凸塊應力緩衝層
124．．．晶片側
126．．．第一球應力緩衝層
128．．．外側
130．．．凸塊接點
132、1321 、1322 ．．．凸塊緩衝層
134、1341 、1342 ．．．凸塊導體焊墊
140．．．第一球接點
142．．．第一球緩衝層
144．．．第一球導體焊墊
150．．．第三基板
160．．．第二球應力緩衝層
162．．．第二球接點
164．．．第二球緩衝層
1641 、1642 ．．．球緩衝層
166．．．第二球導體焊墊
1661 、1662 ．．．球導體焊墊
170．．．導電凸塊
172、372．．．導電球
174、374．．．底膠
300．．．晶圓級晶片尺寸封裝的晶片
302．．．印刷電路板
330．．．晶圓級晶片尺寸封裝的球接點
332．．．晶圓級晶片尺寸封裝的球緩衝層
334．．．晶圓級晶片尺寸封裝的球導體焊墊
D．．．寬度
H．．．高度
第1圖繪示本發明一實施例之接點結構的剖面圖，該接點結構可被用來電性連接基板。
第2A圖與第2B圖繪示本發明另一實施例之接點結構的剖面圖，接點結構可被用來電性連接基板。
第3圖繪示本發明又一實施例之一連接結構的剖面圖，該連接結構位於一晶片與一印刷電路板之間。
100‧‧‧第一基板
102‧‧‧外部接點
104‧‧‧第一鈍化層
105‧‧‧第二鈍化層
106‧‧‧第一導電接墊
107‧‧‧凸塊下金屬層
120‧‧‧第二基板
122‧‧‧凸塊應力緩衝層
124‧‧‧晶片側
126‧‧‧第一球應力緩衝層
128‧‧‧外側
130‧‧‧凸塊接點
132‧‧‧凸塊緩衝層
134‧‧‧凸塊導體焊墊
140‧‧‧第一球接點
142‧‧‧第一球緩衝層
144‧‧‧第一球導體焊墊
150‧‧‧第三基板
160‧‧‧第二球應力緩衝層
162‧‧‧第二球接點
164‧‧‧第二球緩衝層
166‧‧‧第二球導體焊墊
170．．．導電凸塊
172、372．．．導電球
174、374．．．底膠
D．．．寬度
H．．．高度

Claims (7)

  1. 一種半導體結構，包括：一第一基板，具有形成於其上的電路；一第二基板，包括一第一接墊、一第一緩衝層以及一第一導體焊墊，其中該第一緩衝層位於該第一接墊上，且該第一緩衝層的一開口暴露出至少部分的該第一接墊，該第一導體焊墊電性接觸該第一接墊並具有一非平坦的表面，該第一導體焊墊沿著該開口的側壁而形成並延伸至至少部分的該第一緩衝層上；一導電材料，插置於該第一基板與該第二基板之間，該導電材料直接接觸該第一導體焊墊；一第二緩衝層，插置於該第一緩衝層與該第一接墊之間；以及一第二導體焊墊，插置於該第一導體焊墊與該第一接墊之間，該第二導體焊墊延伸至該第二緩衝層的一頂面上。
  2. 如申請專利範圍第1項所述之半導體結構，其中該第一緩衝層包括高分子材料、環氧樹脂、聚亞醯胺、防焊材料或感光材料。
  3. 一種半導體結構，包括：一第一基板，具有一第一側與一第二側，且該第一側與該第二側至少其中之一用來接受至一積體電路晶片的連接；一凸塊應力緩衝層，位於該第一基板的該第一側上，該凸塊應力緩衝層包括一第一凸塊緩衝層，該第一 凸塊緩衝層位於一第一電接點上，且該第一凸塊緩衝層具有一開口，該開口位於至少部分的該第一電接點上，該凸塊應力緩衝層更包括多個第一凸塊導體焊墊，該些第一凸塊導體焊墊具有均勻的厚度並延伸至該第一凸塊緩衝層的一頂面上；一第二凸塊緩衝層，插置於該第一凸塊緩衝層與該第一電接點之間；以及一第二凸塊導體焊墊，插置於該第一凸塊導體焊墊與該第一電接點之間，該第二凸塊導體焊墊延伸至該第二凸塊緩衝層的一頂面上。
  4. 如申請專利範圍第3項所述之半導體結構，更包括：一球應力緩衝層，位於該第一基板的該第二側上，該球應力緩衝層包括一球緩衝層，該球緩衝層位於一第二電接點上，該球緩衝層具有一開口，該開口位於至少部分的該第二電接點上，該球應力緩衝層更包括一球導體焊墊，該球導體焊墊具有均勻的厚度並延伸至該球緩衝層的一頂面上。
  5. 如申請專利範圍第3項所述之半導體結構，更包括：一第二基板，具有形成於其上的電路，該第二基板利用多個導電凸塊電性連接至該第一基板的該些第一凸塊導體焊墊。
  6. 如申請專利範圍第3項所述之半導體結構，其中該第一凸塊緩衝層包括高分子材料、環氧樹脂、聚亞醯 胺、防焊材料或感光材料。
  7. 一種半導體元件的形成方法，該方法包括：提供一第一基板，該第一基板具有一第一電接點與一第二電接點，該第一電接點位於一第一側上，該第二電接點位於一第二側上；形成一第一凸塊緩衝層於該第一電接點上，該第一凸塊緩衝層具有一第一開口，該第一開口位於至少部分的該第一電接點上；形成一第一凸塊導體焊墊，該第一凸塊導體焊墊延伸至該第一凸塊緩衝層的一頂面上，該第一凸塊導體焊墊具有均勻的厚度；形成一第二凸塊緩衝層於該第一凸塊導體焊墊上，該第二凸塊緩衝層具有一第二開口，該第二開口位於至少部分的該第一凸塊導體焊墊上；形成一第二凸塊導體焊墊，該第二凸塊導體焊墊延伸至該第二凸塊緩衝層的一頂面上並具有均勻的厚度；以及在形成該第二凸塊導體焊墊之後，提供一第二基板與一導電材料，其中該導電材料插置於該第一基板與該第二基板之間，該導電材料直接接觸該第二凸塊導體焊墊。
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