KR970072193A - 다단 매립 배선구조 - Google Patents

다단 매립 배선구조 Download PDF

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Publication number
KR970072193A
KR970072193A KR1019960056028A KR19960056028A KR970072193A KR 970072193 A KR970072193 A KR 970072193A KR 1019960056028 A KR1019960056028 A KR 1019960056028A KR 19960056028 A KR19960056028 A KR 19960056028A KR 970072193 A KR970072193 A KR 970072193A
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conductive
layer
groove
wiring
insulating layer
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KR1019960056028A
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KR100218869B1 (ko
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마키코 하세가와
요시히코 토요다
타케시 모리
테츠오 후카다
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기다오까 다까시
미쓰비시 뎅끼 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

IC의 다단 매립 배선구조는 채널 또는 홈내의 도전층상에 형성된 피복을 가지고, 노광의 헐레이션을 방지함으로써, 고정밀도인 구조를 형성할 수 있다. 도전층 재료로서 Cu재료가 사용되더라도, 배선저항이 여전히 작고, Cu의 확산 및 산화를 방지한다.

Description

다단 매립 배선구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1의 실시의 형태에 따른 IC의 다단 매립 배선구조의 단면도.

Claims (3)

  1. 반도체 기판상의 제1의 절연층중에 형성된 제1의 배선구조용 홈 또는 채널과; 해당 제1의 홈에 매립된 제1의 배선용 제1의 도전층과; 상기 제1의 도전층을 피복하고 상기 제1의 도전층과 도통하며, 제2의 절연층의 패터닝시의 노광의 헐레이션을 방지하는 기능을 가지는 도전성 피복층과; 상기 제1의 절연층 및 도전성 피복층상에 형성되고, 비어 홀을 가지는 제2의 절연층과; 해당 비어 홀내에 형성되고, 제2의 도전층과 상기 제1의 도전성 피복층을 접속하는 도전성 접속부와; 제2의 배선구조용 홈을 가지는 제3의 절연층과; 상기 도전성 접속부와 접속되는 제2의 배선용 제2의 도전층을 구비하는 것을 특징으로 하는 IC의 다단 매립 배선구조.
  2. 1) 제1의 배선 형성 공정. 2) 제1의 접속부 형성 공정 및 3) 제2의 배선 형성 공정을 구비하는 IC의 다단매립 배선구조의 제조방법에 있어서, 1) 상기 제1의 배선 형성 공정은 반도체 기판상의 제1의 절연층중에 제1의 매립 배선용 홈을 형성하는 공정과; 상기 홈에 제1의 도전층 및 제1의 도전 피복층을 순차 매립하는 공정으로 이루어지고, 2) 상기 제1의 접속부 형성 공정은 상기 제1의 절연층 및 상기 제1의 도전성 피복층상에 제2의 절연층을 형성하는 공정과; 상기 제1의 도전성 피복층상의 상기 제2의 절연층의 부분에 비어 홀을 형성하는 공정과; 상기 비어 홀내에 상기 제1의 도전성 피복층과 접속하는 도전성 접속부를 매립하는 공정으로 이루어지고, 3) 상기 제2의 배선 형성 공정은 상기 제2의 절연층과 도전성 접속부상에 제3의 절연층을 형성하는 공정과; 상기 도전성 접속부상에 상기 제3의 절연층상의 제2의 배선용 홈을 형성하는 공정과; 상기 홈에 상기 도전성 접속부와 접속한 제2의 도전층을 매립하는 공정으로 이루어지는 것을 특징으로 하는 IC의 다단 매립 배선구조의 제조방법.
  3. 제2항에 있어서, 상기 제1의 홈에 제1의 도전층 및 제1의 도전성 피복층을 순차 형성하는 공정은 상기 제1의 절연층상 및 제1의 홈내에 도전층재료를 퇴적하는 공정과; CMP에 의해 상기 제1의 홈내에만 상기 도전층재료가 남도록 도전층 재료의 상면을 평탄화하는 공정과; 상기 제1의 홈내의 도전층재료의 상부의 리세스를 형성하는 공정과; 상기 리세스에 도전성 피복층을 매립하는 공정으로 이루어지는 것을 특징으로 하는 IC의 다단 매립 배선구조의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019960056028A 1996-04-11 1996-11-21 다단 매립 배선구조 KR100218869B1 (ko)

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JP96-089507 1996-04-11
JP08950796A JP3304754B2 (ja) 1996-04-11 1996-04-11 集積回路の多段埋め込み配線構造

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US5793112A (en) 1998-08-11
US6184124B1 (en) 2001-02-06

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