TW337030B - Multi-stage buried wiring structure and the manufacturing method for Ics - Google Patents

Multi-stage buried wiring structure and the manufacturing method for Ics

Info

Publication number
TW337030B
TW337030B TW085111316A TW85111316A TW337030B TW 337030 B TW337030 B TW 337030B TW 085111316 A TW085111316 A TW 085111316A TW 85111316 A TW85111316 A TW 85111316A TW 337030 B TW337030 B TW 337030B
Authority
TW
Taiwan
Prior art keywords
conductive
layer
buried wiring
insulation layer
continuation
Prior art date
Application number
TW085111316A
Other languages
English (en)
Inventor
Katashi Mori
Yoshihiko Toyota
Tetsuo Fukata
Makiko Hasegawa
Original Assignee
Mitsubish Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubish Electric Corp filed Critical Mitsubish Electric Corp
Application granted granted Critical
Publication of TW337030B publication Critical patent/TW337030B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW085111316A 1996-04-11 1996-09-16 Multi-stage buried wiring structure and the manufacturing method for Ics TW337030B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08950796A JP3304754B2 (ja) 1996-04-11 1996-04-11 集積回路の多段埋め込み配線構造

Publications (1)

Publication Number Publication Date
TW337030B true TW337030B (en) 1998-07-21

Family

ID=13972706

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085111316A TW337030B (en) 1996-04-11 1996-09-16 Multi-stage buried wiring structure and the manufacturing method for Ics

Country Status (4)

Country Link
US (2) US5793112A (zh)
JP (1) JP3304754B2 (zh)
KR (1) KR100218869B1 (zh)
TW (1) TW337030B (zh)

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JPH11283985A (ja) * 1998-03-27 1999-10-15 Seiko Epson Corp 半導体装置およびその製造方法
US6372633B1 (en) * 1998-07-08 2002-04-16 Applied Materials, Inc. Method and apparatus for forming metal interconnects
US6150257A (en) * 1998-08-28 2000-11-21 Micron Technology, Inc. Plasma treatment of an interconnect surface during formation of an interlayer dielectric
US7338908B1 (en) * 2003-10-20 2008-03-04 Novellus Systems, Inc. Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage
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US6319833B1 (en) * 1998-12-07 2001-11-20 Advanced Micro Devices, Inc. Chemically preventing copper dendrite formation and growth by spraying
JP3708732B2 (ja) 1998-12-25 2005-10-19 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
JP3236576B2 (ja) * 1999-03-24 2001-12-10 キヤノン販売株式会社 層間絶縁膜の形成方法、化学的気相成長装置、及び半導体装置
US6030896A (en) * 1999-04-21 2000-02-29 National Semiconductor Corporation Self-aligned copper interconnect architecture with enhanced copper diffusion barrier
US6261950B1 (en) * 1999-10-18 2001-07-17 Infineon Technologies Ag Self-aligned metal caps for interlevel metal connections
JP2001176967A (ja) * 1999-12-21 2001-06-29 Nec Corp 半導体装置及びその製造方法
JP4064595B2 (ja) * 2000-03-28 2008-03-19 株式会社東芝 半導体装置の製造方法
JP3772059B2 (ja) * 2000-01-25 2006-05-10 株式会社東芝 半導体装置及び半導体装置の製造方法
KR100367734B1 (ko) * 2000-01-27 2003-01-10 주식회사 하이닉스반도체 반도체 소자의 배선형성 방법
US6368953B1 (en) * 2000-05-09 2002-04-09 International Business Machines Corporation Encapsulated metal structures for semiconductor devices and MIM capacitors including the same
JP4425432B2 (ja) * 2000-06-20 2010-03-03 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US6909354B2 (en) * 2001-02-08 2005-06-21 Interlink Electronics, Inc. Electronic pressure sensitive transducer apparatus and method for manufacturing same
JP2002252281A (ja) * 2001-02-27 2002-09-06 Sony Corp 半導体装置およびその製造方法
US6461914B1 (en) * 2001-08-29 2002-10-08 Motorola, Inc. Process for making a MIM capacitor
US7183193B2 (en) * 2001-12-28 2007-02-27 Micrel, Inc. Integrated device technology using a buried power buss for major device and circuit advantages
KR100462762B1 (ko) * 2002-06-18 2004-12-20 동부전자 주식회사 반도체 소자의 구리 배선 형성 방법
US6770491B2 (en) * 2002-08-07 2004-08-03 Micron Technology, Inc. Magnetoresistive memory and method of manufacturing the same
US7825516B2 (en) * 2002-12-11 2010-11-02 International Business Machines Corporation Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures
US6975032B2 (en) * 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating
US7050045B2 (en) * 2003-01-07 2006-05-23 Interlink Electronics, Inc. Miniature highly manufacturable mouse pointing device
EP1610376B1 (en) * 2003-03-28 2014-10-15 Fujitsu Semiconductor Limited Semiconductor device
US7972970B2 (en) 2003-10-20 2011-07-05 Novellus Systems, Inc. Fabrication of semiconductor interconnect structure
US8530359B2 (en) * 2003-10-20 2013-09-10 Novellus Systems, Inc. Modulated metal removal using localized wet etching
US8372757B2 (en) * 2003-10-20 2013-02-12 Novellus Systems, Inc. Wet etching methods for copper removal and planarization in semiconductor processing
US8158532B2 (en) * 2003-10-20 2012-04-17 Novellus Systems, Inc. Topography reduction and control by selective accelerator removal
US7531463B2 (en) * 2003-10-20 2009-05-12 Novellus Systems, Inc. Fabrication of semiconductor interconnect structure
KR100590205B1 (ko) * 2004-01-12 2006-06-15 삼성전자주식회사 반도체 장치의 배선 구조체 및 그 형성 방법
JP2005244031A (ja) * 2004-02-27 2005-09-08 Nec Electronics Corp 半導体装置およびその製造方法
US7605082B1 (en) 2005-10-13 2009-10-20 Novellus Systems, Inc. Capping before barrier-removal IC fabrication method
JP2006080559A (ja) * 2005-10-31 2006-03-23 Toshiba Corp 半導体装置の製造方法、半導体製造装置及び半導体装置
KR100729126B1 (ko) * 2005-11-15 2007-06-14 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 및 그 형성 방법
US7573464B2 (en) * 2006-07-20 2009-08-11 Interlink Electronics, Inc. Shape adaptable resistive touchpad
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Also Published As

Publication number Publication date
KR100218869B1 (ko) 1999-09-01
US5793112A (en) 1998-08-11
KR970072193A (ko) 1997-11-07
JP3304754B2 (ja) 2002-07-22
JPH09283520A (ja) 1997-10-31
US6184124B1 (en) 2001-02-06

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MM4A Annulment or lapse of patent due to non-payment of fees